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{
    "id": 93630,
    "url": "http://patches.dpdk.org/api/patches/93630/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210531141027.13289-8-arkadiuszx.kusztal@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210531141027.13289-8-arkadiuszx.kusztal@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210531141027.13289-8-arkadiuszx.kusztal@intel.com",
    "date": "2021-05-31T14:10:19",
    "name": "[07/15] crypto/qat: rework init common header function",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "34215ff634307dc3e6fa7daa993baee9303b1fe5",
    "submitter": {
        "id": 452,
        "url": "http://patches.dpdk.org/api/people/452/?format=api",
        "name": "Arkadiusz Kusztal",
        "email": "arkadiuszx.kusztal@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210531141027.13289-8-arkadiuszx.kusztal@intel.com/mbox/",
    "series": [
        {
            "id": 17172,
            "url": "http://patches.dpdk.org/api/series/17172/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17172",
            "date": "2021-05-31T14:10:12",
            "name": "Add support for fourth generation of Intel QuickAssist Technology devices",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/17172/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/93630/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/93630/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CA992A0524;\n\tMon, 31 May 2021 16:11:44 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 58FCC4111E;\n\tMon, 31 May 2021 16:10:59 +0200 (CEST)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id CAB78410E3\n for <dev@dpdk.org>; Mon, 31 May 2021 16:10:57 +0200 (CEST)",
            "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 31 May 2021 07:10:57 -0700",
            "from silpixa00400308.ir.intel.com ([10.237.214.61])\n by orsmga004.jf.intel.com with ESMTP; 31 May 2021 07:10:55 -0700"
        ],
        "IronPort-SDR": [
            "\n +ylp9kYPGIyZkLxkdclGTisIiPbKpIsh9H0VmfkiKx8t4lWFWV9TnIAOHDMPAI8RPXPQuasDi2\n HXUyXiSSQjJw==",
            "\n J0p1iQ+t6bc4YAU6/5ykJuaQ2EBTQKyje5ylraerRyaDCCIFAYnNiLMU/UDdQFWCMQAdbjKmPP\n +b0XVsvw6/9g=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10001\"; a=\"201492231\"",
            "E=Sophos;i=\"5.83,237,1616482800\"; d=\"scan'208\";a=\"201492231\"",
            "E=Sophos;i=\"5.83,237,1616482800\"; d=\"scan'208\";a=\"548760145\""
        ],
        "X-ExtLoop1": "1",
        "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>",
        "Date": "Mon, 31 May 2021 15:10:19 +0100",
        "Message-Id": "<20210531141027.13289-8-arkadiuszx.kusztal@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210531141027.13289-1-arkadiuszx.kusztal@intel.com>",
        "References": "<20210531141027.13289-1-arkadiuszx.kusztal@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 07/15] crypto/qat: rework init common header\n function",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Rework init common header function for request\ndescriptor so it can be called only once.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n drivers/crypto/qat/qat_sym.c         |  25 +--\n drivers/crypto/qat/qat_sym_session.c | 264 ++++++++++++++-------------\n drivers/crypto/qat/qat_sym_session.h |  12 ++\n 3 files changed, 157 insertions(+), 144 deletions(-)",
    "diff": "diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 9415ec7d32..eef4a886c5 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -289,8 +289,9 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \tauth_param = (void *)((uint8_t *)cipher_param +\n \t\t\tICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);\n \n-\tif (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||\n-\t\t\tctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {\n+\tif ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||\n+\t\t\tctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) &&\n+\t\t\t!ctx->is_gmac) {\n \t\t/* AES-GCM or AES-CCM */\n \t\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||\n \t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||\n@@ -303,7 +304,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\tdo_auth = 1;\n \t\t\tdo_cipher = 1;\n \t\t}\n-\t} else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {\n+\t} else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH || ctx->is_gmac) {\n \t\tdo_auth = 1;\n \t\tdo_cipher = 0;\n \t} else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {\n@@ -383,15 +384,6 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\tauth_param->u1.aad_adr = 0;\n \t\t\tauth_param->u2.aad_sz = 0;\n \n-\t\t\t/*\n-\t\t\t * If len(iv)==12B fw computes J0\n-\t\t\t */\n-\t\t\tif (ctx->auth_iv.length == 12) {\n-\t\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(\n-\t\t\t\t\tqat_req->comn_hdr.serv_specif_flags,\n-\t\t\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n-\n-\t\t\t}\n \t\t} else {\n \t\t\tauth_ofs = op->sym->auth.data.offset;\n \t\t\tauth_len = op->sym->auth.data.length;\n@@ -416,14 +408,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||\n \t\t\t\tctx->qat_hash_alg ==\n \t\t\t\t\tICP_QAT_HW_AUTH_ALGO_GALOIS_64) {\n-\t\t\t/*\n-\t\t\t * If len(iv)==12B fw computes J0\n-\t\t\t */\n-\t\t\tif (ctx->cipher_iv.length == 12) {\n-\t\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(\n-\t\t\t\t\tqat_req->comn_hdr.serv_specif_flags,\n-\t\t\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n-\t\t\t}\n+\n \t\t\tset_cipher_iv(ctx->cipher_iv.length,\n \t\t\t\t\tctx->cipher_iv.offset,\n \t\t\t\t\tcipher_param, op, qat_req);\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 5140d61a9c..4b52ffd459 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -69,6 +69,15 @@ qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\t\t\t\t\tuint32_t aad_length,\n \t\t\t\t\t\tuint32_t digestsize,\n \t\t\t\t\t\tunsigned int operation);\n+static void\n+qat_sym_session_init_common_hdr(struct qat_sym_session *session);\n+\n+/* Req/cd init functions */\n+\n+static void qat_sym_session_finalize(struct qat_sym_session *session)\n+{\n+\tqat_sym_session_init_common_hdr(session);\n+}\n \n /** Frees a context previously created\n  *  Depends on openssl libcrypto\n@@ -558,6 +567,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \tenum qat_device_gen qat_dev_gen = internals->qat_dev->qat_dev_gen;\n \tint ret;\n \tint qat_cmd_id;\n+\tint handle_mixed = 0;\n \n \t/* Verify the session physical address is known */\n \trte_iova_t session_paddr = rte_mempool_virt2iova(session);\n@@ -573,6 +583,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\toffsetof(struct qat_sym_session, cd);\n \n \tsession->min_qat_dev_gen = QAT_GEN1;\n+\tsession->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_NONE;\n \tsession->is_ucs = 0;\n \n \t/* Get requested QAT command id */\n@@ -612,8 +623,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\t\t\txform, session);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n-\t\t\t/* Special handling of mixed hash+cipher algorithms */\n-\t\t\tqat_sym_session_handle_mixed(dev, session);\n+\t\t\thandle_mixed = 1;\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_HASH_CIPHER:\n@@ -631,8 +641,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\t\t\txform, session);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n-\t\t\t/* Special handling of mixed hash+cipher algorithms */\n-\t\t\tqat_sym_session_handle_mixed(dev, session);\n+\t\t\thandle_mixed = 1;\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:\n@@ -652,72 +661,41 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\tsession->qat_cmd);\n \t\treturn -ENOTSUP;\n \t}\n+\tqat_sym_session_finalize(session);\n+\tif (handle_mixed) {\n+\t\t/* Special handling of mixed hash+cipher algorithms */\n+\t\tqat_sym_session_handle_mixed(dev, session);\n+\t}\n \n \treturn 0;\n }\n \n static int\n qat_sym_session_handle_single_pass(struct qat_sym_session *session,\n-\t\tstruct rte_crypto_aead_xform *aead_xform)\n+\t\tconst struct rte_crypto_aead_xform *aead_xform)\n {\n-\tstruct icp_qat_fw_la_cipher_req_params *cipher_param =\n-\t\t\t(void *) &session->fw_req.serv_specif_rqpars;\n-\n \tsession->is_single_pass = 1;\n+\tsession->is_auth = 1;\n \tsession->min_qat_dev_gen = QAT_GEN3;\n \tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER;\n+\t/* Chacha-Poly is special case that use QAT CTR mode */\n \tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) {\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_AEAD_MODE;\n-\t\tICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(\n-\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n \t} else {\n-\t\t/* Chacha-Poly is special case that use QAT CTR mode */\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t}\n \tsession->cipher_iv.offset = aead_xform->iv.offset;\n \tsession->cipher_iv.length = aead_xform->iv.length;\n-\tif (qat_sym_cd_cipher_set(session,\n-\t\t\taead_xform->key.data, aead_xform->key.length))\n-\t\treturn -EINVAL;\n \tsession->aad_len = aead_xform->aad_length;\n \tsession->digest_length = aead_xform->digest_length;\n+\n \tif (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {\n \t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n \t\tsession->auth_op = ICP_QAT_HW_AUTH_GENERATE;\n-\t\tICP_QAT_FW_LA_RET_AUTH_SET(\n-\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\tICP_QAT_FW_LA_RET_AUTH_RES);\n \t} else {\n \t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n \t\tsession->auth_op = ICP_QAT_HW_AUTH_VERIFY;\n-\t\tICP_QAT_FW_LA_CMP_AUTH_SET(\n-\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\tICP_QAT_FW_LA_CMP_AUTH_RES);\n \t}\n-\tICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(\n-\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO);\n-\tICP_QAT_FW_LA_PROTO_SET(\n-\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\tICP_QAT_FW_LA_NO_PROTO);\n-\tsession->fw_req.comn_hdr.service_cmd_id =\n-\t\t\tICP_QAT_FW_LA_CMD_CIPHER;\n-\tsession->cd.cipher.cipher_config.val =\n-\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD(\n-\t\t\t\tICP_QAT_HW_CIPHER_AEAD_MODE,\n-\t\t\t\tsession->qat_cipher_alg,\n-\t\t\t\tICP_QAT_HW_CIPHER_NO_CONVERT,\n-\t\t\t\tsession->qat_dir);\n-\tQAT_FIELD_SET(session->cd.cipher.cipher_config.val,\n-\t\t\taead_xform->digest_length,\n-\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,\n-\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);\n-\tsession->cd.cipher.cipher_config.reserved =\n-\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(\n-\t\t\t\taead_xform->aad_length);\n-\tcipher_param->spc_aad_sz = aead_xform->aad_length;\n-\tcipher_param->spc_auth_res_sz = aead_xform->digest_length;\n \n \treturn 0;\n }\n@@ -737,6 +715,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \tsession->auth_iv.offset = auth_xform->iv.offset;\n \tsession->auth_iv.length = auth_xform->iv.length;\n \tsession->auth_mode = ICP_QAT_HW_AUTH_MODE1;\n+\tsession->is_auth = 1;\n \n \tswitch (auth_xform->algo) {\n \tcase RTE_CRYPTO_AUTH_SHA1:\n@@ -791,6 +770,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n \t\tif (session->auth_iv.length == 0)\n \t\t\tsession->auth_iv.length = AES_GCM_J0_LEN;\n+\t\telse\n+\t\t\tsession->is_iv12B = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;\n@@ -825,6 +806,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t}\n \n \tif (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {\n+\t\tsession->is_gmac = 1;\n \t\tif (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {\n \t\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n \t\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n@@ -832,7 +814,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\t * It needs to create cipher desc content first,\n \t\t\t * then authentication\n \t\t\t */\n-\n \t\t\tif (qat_sym_cd_cipher_set(session,\n \t\t\t\t\t\tauth_xform->key.data,\n \t\t\t\t\t\tauth_xform->key.length))\n@@ -866,8 +847,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\t\t\t\tauth_xform->key.length))\n \t\t\t\treturn -EINVAL;\n \t\t}\n-\t\t/* Restore to authentication only only */\n-\t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;\n \t} else {\n \t\tif (qat_sym_cd_auth_set(session,\n \t\t\t\tkey_data,\n@@ -902,6 +881,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \tsession->cipher_iv.length = xform->aead.iv.length;\n \n \tsession->auth_mode = ICP_QAT_HW_AUTH_MODE1;\n+\tsession->is_auth = 1;\n+\tsession->digest_length = aead_xform->digest_length;\n \n \tsession->is_single_pass = 0;\n \tswitch (aead_xform->algo) {\n@@ -913,15 +894,19 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n-\t\tif (qat_dev_gen == QAT_GEN3 && aead_xform->iv.length ==\n-\t\t\t\tQAT_AES_GCM_SPC_IV_SIZE) {\n-\t\t\treturn qat_sym_session_handle_single_pass(session,\n-\t\t\t\t\taead_xform);\n-\t\t}\n-\t\tif (session->cipher_iv.length == 0)\n-\t\t\tsession->cipher_iv.length = AES_GCM_J0_LEN;\n+\n \t\tif (qat_dev_gen == QAT_GEN4)\n \t\t\tsession->is_ucs = 1;\n+\n+\t\tif (session->cipher_iv.length == 0) {\n+\t\t\tsession->cipher_iv.length = AES_GCM_J0_LEN;\n+\t\t\tbreak;\n+\t\t}\n+\t\tsession->is_iv12B = 1;\n+\t\tif (qat_dev_gen == QAT_GEN3) {\n+\t\t\tqat_sym_session_handle_single_pass(session,\n+\t\t\t\t\taead_xform);\n+\t\t}\n \t\tbreak;\n \tcase RTE_CRYPTO_AEAD_AES_CCM:\n \t\tif (qat_sym_validate_aes_key(aead_xform->key.length,\n@@ -939,15 +924,20 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\t\treturn -EINVAL;\n \t\tsession->qat_cipher_alg =\n \t\t\t\tICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;\n-\t\treturn qat_sym_session_handle_single_pass(session,\n+\t\tqat_sym_session_handle_single_pass(session,\n \t\t\t\t\t\taead_xform);\n+\t\tbreak;\n \tdefault:\n \t\tQAT_LOG(ERR, \"Crypto: Undefined AEAD specified %u\\n\",\n \t\t\t\taead_xform->algo);\n \t\treturn -EINVAL;\n \t}\n \n-\tif ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&\n+\tif (session->is_single_pass) {\n+\t\tif (qat_sym_cd_cipher_set(session,\n+\t\t\t\taead_xform->key.data, aead_xform->key.length))\n+\t\t\treturn -EINVAL;\n+\t} else if ((aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&\n \t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) ||\n \t\t\t(aead_xform->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&\n \t\t\taead_xform->algo == RTE_CRYPTO_AEAD_AES_CCM)) {\n@@ -995,7 +985,6 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\t\treturn -EINVAL;\n \t}\n \n-\tsession->digest_length = aead_xform->digest_length;\n \treturn 0;\n }\n \n@@ -1467,13 +1456,17 @@ static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,\n }\n \n static void\n-qat_sym_session_init_common_hdr(struct qat_sym_session *session,\n-\t\tstruct icp_qat_fw_comn_req_hdr *header,\n-\t\tenum qat_sym_proto_flag proto_flags)\n+qat_sym_session_init_common_hdr(struct qat_sym_session *session)\n {\n+\tstruct icp_qat_fw_la_bulk_req *req_tmpl = &session->fw_req;\n+\tstruct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;\n+\tenum qat_sym_proto_flag proto_flags = session->qat_proto_flag;\n+\tuint32_t slice_flags = session->slice_types;\n+\n \theader->hdr_flags =\n \t\tICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);\n \theader->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_LA;\n+\theader->service_cmd_id = session->qat_cmd;\n \theader->comn_req_flags =\n \t\tICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_64BIT_ADR,\n \t\t\t\t\tQAT_COMN_PTR_TYPE_FLAT);\n@@ -1505,40 +1498,47 @@ qat_sym_session_init_common_hdr(struct qat_sym_session *session,\n \t\tbreak;\n \t}\n \n-\tICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,\n-\t\t\t\t\t   ICP_QAT_FW_LA_NO_UPDATE_STATE);\n-\tICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,\n-\t\t\t\t\tICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);\n-\n-\tif (session->is_ucs) {\n+\t/* More than one of the following flags can be set at once */\n+\tif (QAT_SESSION_IS_SLICE_SET(slice_flags, QAT_CRYPTO_SLICE_SPC)) {\n+\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(\n+\t\t\theader->serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_SINGLE_PASS_PROTO);\n+\t}\n+\tif (QAT_SESSION_IS_SLICE_SET(slice_flags, QAT_CRYPTO_SLICE_UCS)) {\n \t\tICP_QAT_FW_LA_SLICE_TYPE_SET(\n-\t\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_USE_UCS_SLICE_TYPE);\n+\t\t\theader->serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_USE_UCS_SLICE_TYPE);\n \t}\n-}\n \n-/*\n- *\tSnow3G and ZUC should never use this function\n- *\tand set its protocol flag in both cipher and auth part of content\n- *\tdescriptor building function\n- */\n-static enum qat_sym_proto_flag\n-qat_get_crypto_proto_flag(uint16_t flags)\n-{\n-\tint proto = ICP_QAT_FW_LA_PROTO_GET(flags);\n-\tenum qat_sym_proto_flag qat_proto_flag =\n-\t\t\tQAT_CRYPTO_PROTO_FLAG_NONE;\n+\tif (session->is_auth) {\n+\t\tif (session->auth_op == ICP_QAT_HW_AUTH_VERIFY) {\n+\t\t\tICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_NO_RET_AUTH_RES);\n+\t\t\tICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_CMP_AUTH_RES);\n+\t\t} else if (session->auth_op == ICP_QAT_HW_AUTH_GENERATE) {\n+\t\t\tICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\t\t\tICP_QAT_FW_LA_RET_AUTH_RES);\n+\t\t\tICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\t\t\tICP_QAT_FW_LA_NO_CMP_AUTH_RES);\n+\t\t}\n+\t} else {\n+\t\tICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_NO_RET_AUTH_RES);\n+\t\tICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_NO_CMP_AUTH_RES);\n+\t}\n \n-\tswitch (proto) {\n-\tcase ICP_QAT_FW_LA_GCM_PROTO:\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;\n-\t\tbreak;\n-\tcase ICP_QAT_FW_LA_CCM_PROTO:\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;\n-\t\tbreak;\n+\tif (session->is_iv12B) {\n+\t\tICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(\n+\t\t\theader->serv_specif_flags,\n+\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n \t}\n \n-\treturn qat_proto_flag;\n+\tICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,\n+\t\t\t\t\t   ICP_QAT_FW_LA_NO_UPDATE_STATE);\n+\tICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);\n }\n \n int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n@@ -1554,8 +1554,12 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \tstruct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;\n \tstruct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;\n \tenum icp_qat_hw_cipher_convert key_convert;\n-\tenum qat_sym_proto_flag qat_proto_flag =\n-\t\tQAT_CRYPTO_PROTO_FLAG_NONE;\n+\tstruct icp_qat_fw_la_cipher_20_req_params *req_ucs =\n+\t\t\t(struct icp_qat_fw_la_cipher_20_req_params *)\n+\t\t\t&cdesc->fw_req.serv_specif_rqpars;\n+\tstruct icp_qat_fw_la_cipher_req_params *req_cipher =\n+\t\t\t(struct icp_qat_fw_la_cipher_req_params *)\n+\t\t\t&cdesc->fw_req.serv_specif_rqpars;\n \tuint32_t total_key_size;\n \tuint16_t cipher_offset, cd_size;\n \tuint32_t wordIndex  = 0;\n@@ -1591,9 +1595,16 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \tif (cdesc->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE) {\n \t\t/*\n \t\t * CTR Streaming ciphers are a special case. Decrypt = encrypt\n-\t\t * Overriding default values previously set\n+\t\t * Overriding default values previously set.\n+\t\t * Chacha20-Poly1305 is special case, CTR but single-pass\n+\t\t * so both direction need to be used.\n \t\t */\n \t\tcdesc->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n+\t\tif (cdesc->qat_cipher_alg ==\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 &&\n+\t\t\tcdesc->auth_op == ICP_QAT_HW_AUTH_VERIFY) {\n+\t\t\t\tcdesc->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n+\t\t}\n \t\tkey_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;\n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2\n \t\t|| cdesc->qat_cipher_alg ==\n@@ -1601,6 +1612,8 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t\tkey_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;\n \telse if (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT)\n \t\tkey_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;\n+\telse if (cdesc->qat_mode == ICP_QAT_HW_CIPHER_AEAD_MODE)\n+\t\tkey_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;\n \telse\n \t\tkey_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;\n \n@@ -1609,7 +1622,7 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t\t\tICP_QAT_HW_SNOW_3G_UEA2_IV_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz =\n \t\t\tICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n+\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n \n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {\n \t\ttotal_key_size = ICP_QAT_HW_KASUMI_F8_KEY_SZ;\n@@ -1619,33 +1632,24 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) {\n \t\ttotal_key_size = ICP_QAT_HW_3DES_KEY_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_3DES_BLK_SZ >> 3;\n-\t\tqat_proto_flag =\n-\t\t\tqat_get_crypto_proto_flag(header->serv_specif_flags);\n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_DES) {\n \t\ttotal_key_size = ICP_QAT_HW_DES_KEY_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_DES_BLK_SZ >> 3;\n-\t\tqat_proto_flag =\n-\t\t\tqat_get_crypto_proto_flag(header->serv_specif_flags);\n \t} else if (cdesc->qat_cipher_alg ==\n \t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n \t\ttotal_key_size = ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ +\n \t\t\tICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;\n \t\tcipher_cd_ctrl->cipher_state_sz =\n \t\t\tICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n+\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n \t\tcdesc->min_qat_dev_gen = QAT_GEN2;\n \t} else {\n \t\ttotal_key_size = cipherkeylen;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;\n-\t\tqat_proto_flag =\n-\t\t\tqat_get_crypto_proto_flag(header->serv_specif_flags);\n \t}\n \tcipher_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd);\n \tcipher_cd_ctrl->cipher_cfg_offset = cipher_offset >> 3;\n \n-\theader->service_cmd_id = cdesc->qat_cmd;\n-\tqat_sym_session_init_common_hdr(cdesc, header, qat_proto_flag);\n-\n \tcipher = (struct icp_qat_hw_cipher_algo_blk *)cdesc->cd_cur_ptr;\n \tcipher20 = (struct icp_qat_hw_cipher_algo_blk20 *)cdesc->cd_cur_ptr;\n \tcipher->cipher_config.val =\n@@ -1670,6 +1674,7 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t} else if (cdesc->is_ucs) {\n \t\tconst uint8_t *final_key = cipherkey;\n \n+\t\tcdesc->slice_types |= QAT_CRYPTO_SLICE_UCS;\n \t\ttotal_key_size = RTE_ALIGN_CEIL(cipherkeylen,\n \t\t\tICP_QAT_HW_AES_128_KEY_SZ);\n \t\tcipher20->cipher_config.reserved[0] = 0;\n@@ -1686,6 +1691,18 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t\t\t\t\tcipherkeylen;\n \t}\n \n+\tif (cdesc->is_single_pass) {\n+\t\tQAT_FIELD_SET(cipher->cipher_config.val,\n+\t\t\tcdesc->digest_length,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS,\n+\t\t\tQAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);\n+\t\t/* UCS and SPC 1.8/2.0 share configuration of 2nd config word */\n+\t\tcdesc->cd.cipher.cipher_config.reserved =\n+\t\t\t\tICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(\n+\t\t\t\t\tcdesc->aad_len);\n+\t\tcdesc->slice_types |= QAT_CRYPTO_SLICE_SPC;\n+\t}\n+\n \tif (total_key_size > cipherkeylen) {\n \t\tuint32_t padding_size =  total_key_size-cipherkeylen;\n \t\tif ((cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES)\n@@ -1704,6 +1721,20 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \n \t\tcdesc->cd_cur_ptr += padding_size;\n \t}\n+\tif (cdesc->is_ucs) {\n+\t\t/*\n+\t\t * These values match in terms of position auth\n+\t\t * slice request fields\n+\t\t */\n+\t\treq_ucs->spc_auth_res_sz = cdesc->digest_length;\n+\t\tif (!cdesc->is_gmac) {\n+\t\t\treq_ucs->spc_aad_sz = cdesc->aad_len;\n+\t\t\treq_ucs->spc_aad_offset = 0;\n+\t\t}\n+\t} else if (cdesc->is_single_pass) {\n+\t\treq_cipher->spc_aad_sz = cdesc->aad_len;\n+\t\treq_cipher->spc_auth_res_sz = cdesc->digest_length;\n+\t}\n \tcd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;\n \tcd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3;\n \tcipher_cd_ctrl->cipher_key_sz = total_key_size >> 3;\n@@ -1722,7 +1753,6 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \tstruct icp_qat_hw_cipher_algo_blk *cipherconfig;\n \tstruct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;\n \tstruct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;\n-\tstruct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;\n \tvoid *ptr = &req_tmpl->cd_ctrl;\n \tstruct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;\n \tstruct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;\n@@ -1735,8 +1765,6 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \tuint32_t *aad_len = NULL;\n \tuint32_t wordIndex  = 0;\n \tuint32_t *pTempKey;\n-\tenum qat_sym_proto_flag qat_proto_flag =\n-\t\tQAT_CRYPTO_PROTO_FLAG_NONE;\n \n \tif (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {\n \t\tICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl,\n@@ -1759,19 +1787,10 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\treturn -EFAULT;\n \t}\n \n-\tif (operation == RTE_CRYPTO_AUTH_OP_VERIFY) {\n-\t\tICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_NO_RET_AUTH_RES);\n-\t\tICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,\n-\t\t\t\tICP_QAT_FW_LA_CMP_AUTH_RES);\n+\tif (operation == RTE_CRYPTO_AUTH_OP_VERIFY)\n \t\tcdesc->auth_op = ICP_QAT_HW_AUTH_VERIFY;\n-\t} else {\n-\t\tICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,\n-\t\t\t\t\t   ICP_QAT_FW_LA_RET_AUTH_RES);\n-\t\tICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,\n-\t\t\t\t\t   ICP_QAT_FW_LA_NO_CMP_AUTH_RES);\n+\telse\n \t\tcdesc->auth_op = ICP_QAT_HW_AUTH_GENERATE;\n-\t}\n \n \t/*\n \t * Setup the inner hash config\n@@ -1913,7 +1932,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;\n+\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;\n \t\tstate1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;\n \t\tif (qat_sym_do_precomputes(cdesc->qat_hash_alg, authkey,\n \t\t\tauthkeylen, cdesc->cd_cur_ptr + state1_size,\n@@ -1936,7 +1955,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tcdesc->aad_len = aad_length;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n+\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n \t\tstate1_size = qat_hash_get_state1_size(\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2);\n \t\tstate2_size = ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ;\n@@ -1960,7 +1979,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\thash->auth_config.config =\n \t\t\tICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE0,\n \t\t\t\tcdesc->qat_hash_alg, digestsize);\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n+\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n \t\tstate1_size = qat_hash_get_state1_size(\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3);\n \t\tstate2_size = ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ;\n@@ -1988,7 +2007,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tstate2_size = ICP_QAT_HW_NULL_STATE2_SZ;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:\n-\t\tqat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;\n+\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;\n \t\tstate1_size = qat_hash_get_state1_size(\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC);\n \t\tstate2_size = ICP_QAT_HW_AES_CBC_MAC_KEY_SZ +\n@@ -2036,10 +2055,6 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\treturn -EFAULT;\n \t}\n \n-\t/* Request template setup */\n-\tqat_sym_session_init_common_hdr(cdesc, header, qat_proto_flag);\n-\theader->service_cmd_id = cdesc->qat_cmd;\n-\n \t/* Auth CD config setup */\n \thash_cd_ctrl->hash_cfg_offset = hash_offset >> 3;\n \thash_cd_ctrl->hash_flags = ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;\n@@ -2248,6 +2263,7 @@ qat_sec_session_set_docsis_parameters(struct rte_cryptodev *dev,\n \tret = qat_sym_session_configure_cipher(dev, xform, session);\n \tif (ret < 0)\n \t\treturn ret;\n+\tqat_sym_session_finalize(session);\n \n \treturn 0;\n }\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex e003a34f7f..1568e09200 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -48,6 +48,13 @@\n \n #define QAT_AES_CMAC_CONST_RB 0x87\n \n+#define QAT_CRYPTO_SLICE_SPC\t1\n+#define QAT_CRYPTO_SLICE_UCS\t2\n+#define QAT_CRYPTO_SLICE_WCP\t4\n+\n+#define QAT_SESSION_IS_SLICE_SET(flags, flag)\t\\\n+\t(!!((flags) & (flag)))\n+\n enum qat_sym_proto_flag {\n \tQAT_CRYPTO_PROTO_FLAG_NONE = 0,\n \tQAT_CRYPTO_PROTO_FLAG_CCM = 1,\n@@ -93,6 +100,11 @@ struct qat_sym_session {\n \tuint8_t is_single_pass;\n \tuint8_t is_single_pass_gmac;\n \tuint8_t is_ucs;\n+\tuint8_t is_iv12B;\n+\tuint8_t is_gmac;\n+\tuint8_t is_auth;\n+\tuint32_t slice_types;\n+\tenum qat_sym_proto_flag qat_proto_flag;\n };\n \n int\n",
    "prefixes": [
        "07/15"
    ]
}