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GET /api/patches/93627/?format=api
{ "id": 93627, "url": "http://patches.dpdk.org/api/patches/93627/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210531141027.13289-5-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210531141027.13289-5-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210531141027.13289-5-arkadiuszx.kusztal@intel.com", "date": "2021-05-31T14:10:16", "name": "[04/15] crypto/qat: add fourth generation ucs slice type, add ctr mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5223b60fbe85938ebcbf868eaade67ea3e2a5c6a", "submitter": { "id": 452, "url": "http://patches.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210531141027.13289-5-arkadiuszx.kusztal@intel.com/mbox/", "series": [ { "id": 17172, "url": "http://patches.dpdk.org/api/series/17172/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17172", "date": "2021-05-31T14:10:12", "name": "Add support for fourth generation of Intel QuickAssist Technology devices", "version": 1, "mbox": "http://patches.dpdk.org/series/17172/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/93627/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/93627/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6FD31A0524;\n\tMon, 31 May 2021 16:11:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6C481410F5;\n\tMon, 31 May 2021 16:10:53 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 7B6B0410DF\n for <dev@dpdk.org>; Mon, 31 May 2021 16:10:51 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 31 May 2021 07:10:51 -0700", "from silpixa00400308.ir.intel.com ([10.237.214.61])\n by orsmga004.jf.intel.com with ESMTP; 31 May 2021 07:10:49 -0700" ], "IronPort-SDR": [ "\n 17jiTcXrCiLfSkFOJYfeoTberP7QAxefQ+IfIJrb8cvSbXZnkAKcbIplWc97ho8Fr6LPuE40vb\n HoK5DQzsU2PQ==", "\n R1oTRpfE+GfF7dSH+03VVOzLJsHIrbWWM7bdlzhMuqUoiuywuMnd/NAGXGbpSpm6EO0kB7UGGE\n bfAYHSSRfiYg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10001\"; a=\"201492217\"", "E=Sophos;i=\"5.83,237,1616482800\"; d=\"scan'208\";a=\"201492217\"", "E=Sophos;i=\"5.83,237,1616482800\"; d=\"scan'208\";a=\"548760081\"" ], "X-ExtLoop1": "1", "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>", "Date": "Mon, 31 May 2021 15:10:16 +0100", "Message-Id": "<20210531141027.13289-5-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210531141027.13289-1-arkadiuszx.kusztal@intel.com>", "References": "<20210531141027.13289-1-arkadiuszx.kusztal@intel.com>", "Subject": "[dpdk-dev] [PATCH 04/15] crypto/qat: add fourth generation ucs\n slice type, add ctr mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds unified cipher slice to Intel QuickAssist\nTechnology PMD and enables AES-CTR algorithm.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n drivers/common/qat/qat_adf/icp_qat_fw_la.h | 28 ++++++++++++++++++++++\n drivers/common/qat/qat_adf/icp_qat_hw.h | 10 ++++++++\n drivers/crypto/qat/qat_sym_capabilities.h | 20 ++++++++++++++++\n drivers/crypto/qat/qat_sym_session.c | 27 ++++++++++++++++++++-\n drivers/crypto/qat/qat_sym_session.h | 1 +\n 5 files changed, 85 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\nindex 20eb145def..c4901eb869 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n@@ -371,4 +371,32 @@ struct icp_qat_fw_la_resp {\n \t& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \\\n \t((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }\n \n+#define ICP_QAT_FW_LA_USE_WIRELESS_SLICE_TYPE 2\n+#define ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE 1\n+#define ICP_QAT_FW_LA_USE_LEGACY_SLICE_TYPE 0\n+#define QAT_LA_SLICE_TYPE_BITPOS 14\n+#define QAT_LA_SLICE_TYPE_MASK 0x3\n+#define ICP_QAT_FW_LA_SLICE_TYPE_SET(flags, val)\t\\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_SLICE_TYPE_BITPOS,\t\\\n+\t\tQAT_LA_SLICE_TYPE_MASK)\n+\n+struct icp_qat_fw_la_cipher_20_req_params {\n+\tuint32_t cipher_offset;\n+\tuint32_t cipher_length;\n+\tunion {\n+\tuint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];\n+\tstruct {\n+\t\tuint64_t cipher_IV_ptr;\n+\t\tuint64_t resrvd1;\n+\t\t} s;\n+\n+\t} u;\n+\tuint32_t spc_aad_offset;\n+\tuint32_t spc_aad_sz;\n+\tuint64_t spc_aad_addr;\n+\tuint64_t spc_auth_res_addr;\n+\tuint8_t reserved[3];\n+\tuint8_t spc_auth_res_sz;\n+};\n+\n #endif\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h\nindex fdc0f191a2..b1e6a1fa15 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_hw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h\n@@ -342,6 +342,16 @@ struct icp_qat_hw_cipher_algo_blk {\n \tuint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];\n } __rte_cache_aligned;\n \n+struct icp_qat_hw_ucs_cipher_config {\n+\tuint32_t val;\n+\tuint32_t reserved[3];\n+};\n+\n+struct icp_qat_hw_cipher_algo_blk20 {\n+\tstruct icp_qat_hw_ucs_cipher_config cipher_config;\n+\tuint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];\n+} __rte_cache_aligned;\n+\n /* ========================================================================= */\n /* COMPRESSION SLICE */\n /* ========================================================================= */\ndiff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h\nindex 21c817bccc..aca528b991 100644\n--- a/drivers/crypto/qat/qat_sym_capabilities.h\n+++ b/drivers/crypto/qat/qat_sym_capabilities.h\n@@ -1064,6 +1064,26 @@\n \t\t\t\t.iv_size = { 0 }\t\t\t\\\n \t\t\t}, }\t\t\t\t\t\t\\\n \t\t}, }\t\t\t\t\t\t\t\\\n+\t},\t\t\t\t\t\t\t\t\\\n+\t{\t/* AES CTR */\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\t\\\n+\t\t\t{.cipher = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CTR,\t\\\n+\t\t\t\t.block_size = 16,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 16,\t\t\t\\\n+\t\t\t\t\t.max = 32,\t\t\t\\\n+\t\t\t\t\t.increment = 8\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 16,\t\t\t\\\n+\t\t\t\t\t.max = 16,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \n \ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 506ffddd20..2c44b1f1aa 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -246,6 +246,8 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n {\n \tstruct qat_sym_dev_private *internals = dev->data->dev_private;\n \tstruct rte_crypto_cipher_xform *cipher_xform = NULL;\n+\tenum qat_device_gen qat_dev_gen =\n+\t\t\t\tinternals->qat_dev->qat_dev_gen;\n \tint ret;\n \n \t/* Get cipher xform from crypto xform chain */\n@@ -272,6 +274,13 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\t\tgoto error_out;\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tif (qat_dev_gen == QAT_GEN4) {\n+\t\t\t/* TODO: Filter WCP */\n+\t\t\tICP_QAT_FW_LA_SLICE_TYPE_SET(\n+\t\t\t\tsession->fw_req.comn_hdr.serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_USE_UCS_SLICE_TYPE);\n+\t\t\tsession->is_ucs = 1;\n+\t\t}\n \t\tbreak;\n \tcase RTE_CRYPTO_CIPHER_SNOW3G_UEA2:\n \t\tif (qat_sym_validate_snow3g_key(cipher_xform->key.length,\n@@ -556,6 +565,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\toffsetof(struct qat_sym_session, cd);\n \n \tsession->min_qat_dev_gen = QAT_GEN1;\n+\tsession->is_ucs = 0;\n \n \t/* Get requested QAT command id */\n \tqat_cmd_id = qat_get_cmd_id(xform);\n@@ -1518,6 +1528,7 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc,\n \t\t\t\t\t\tuint32_t cipherkeylen)\n {\n \tstruct icp_qat_hw_cipher_algo_blk *cipher;\n+\tstruct icp_qat_hw_cipher_algo_blk20 *cipher20;\n \tstruct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;\n \tstruct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;\n \tstruct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;\n@@ -1611,7 +1622,6 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc,\n \t\tqat_proto_flag =\n \t\t\tqat_get_crypto_proto_flag(header->serv_specif_flags);\n \t}\n-\tcipher_cd_ctrl->cipher_key_sz = total_key_size >> 3;\n \tcipher_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd);\n \tcipher_cd_ctrl->cipher_cfg_offset = cipher_offset >> 3;\n \n@@ -1619,6 +1629,7 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc,\n \tqat_sym_session_init_common_hdr(header, qat_proto_flag);\n \n \tcipher = (struct icp_qat_hw_cipher_algo_blk *)cdesc->cd_cur_ptr;\n+\tcipher20 = (struct icp_qat_hw_cipher_algo_blk20 *)cdesc->cd_cur_ptr;\n \tcipher->cipher_config.val =\n \t ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode,\n \t\t\t\t\tcdesc->qat_cipher_alg, key_convert,\n@@ -1638,6 +1649,19 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc,\n \n \t\tcdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +\n \t\t\t\t\tcipherkeylen + cipherkeylen;\n+\t} else if (cdesc->is_ucs) {\n+\t\tconst uint8_t *final_key = cipherkey;\n+\n+\t\ttotal_key_size = RTE_ALIGN_CEIL(cipherkeylen,\n+\t\t\tICP_QAT_HW_AES_128_KEY_SZ);\n+\t\tcipher20->cipher_config.reserved[0] = 0;\n+\t\tcipher20->cipher_config.reserved[1] = 0;\n+\t\tcipher20->cipher_config.reserved[2] = 0;\n+\n+\t\trte_memcpy(cipher20->key, final_key, cipherkeylen);\n+\t\tcdesc->cd_cur_ptr +=\n+\t\t\tsizeof(struct icp_qat_hw_ucs_cipher_config) +\n+\t\t\t\t\tcipherkeylen;\n \t} else {\n \t\tmemcpy(cipher->key, cipherkey, cipherkeylen);\n \t\tcdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +\n@@ -1664,6 +1688,7 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc,\n \t}\n \tcd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;\n \tcd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3;\n+\tcipher_cd_ctrl->cipher_key_sz = total_key_size >> 3;\n \n \treturn 0;\n }\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 72eee06597..4450df6911 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -92,6 +92,7 @@ struct qat_sym_session {\n \tuint8_t aes_cmac;\n \tuint8_t is_single_pass;\n \tuint8_t is_single_pass_gmac;\n+\tuint8_t is_ucs;\n };\n \n int\n", "prefixes": [ "04/15" ] }