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GET /api/patches/92831/?format=api
{ "id": 92831, "url": "http://patches.dpdk.org/api/patches/92831/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210505065008.30680-17-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210505065008.30680-17-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210505065008.30680-17-bingz@nvidia.com", "date": "2021-05-05T06:50:07", "name": "[v3,16/17] net/mlx5: add support of CT between two ports", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fdf304e0098ed1a750f24ee0a2dd529d49a80660", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210505065008.30680-17-bingz@nvidia.com/mbox/", "series": [ { "id": 16818, "url": "http://patches.dpdk.org/api/series/16818/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16818", "date": "2021-05-05T06:49:53", "name": "[v3,01/17] common/mlx5: add connection tracking object definition", "version": 3, "mbox": "http://patches.dpdk.org/series/16818/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92831/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92831/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A3508A0524;\n\tWed, 5 May 2021 08:53:12 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CC105410E2;\n\tWed, 5 May 2021 08:51:45 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2067.outbound.protection.outlook.com [40.107.237.67])\n by mails.dpdk.org (Postfix) with ESMTP id 160CD4116F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Wed, 5 May 2021 09:50:07 +0300", "Message-ID": "<20210505065008.30680-17-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210505065008.30680-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>\n <20210505065008.30680-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "0f913caf-1b16-409d-94c1-08d90f923da9", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3628:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB36289F3AED17ED007CBDEAFBD0599@DM6PR12MB3628.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:352;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n tg20PXJtlm7zh6LBZ2iLmNBX+M3ZGc9l5antOV/9CKtiX2wNx/VXn1xD0byjNVH8KQsBMXwbCaU9U3VsM35w6ZHt1Ko8VvBLT+cmsVVd1BdrO1C7RPEviWO51bUjW77vxeceNDO+R8tcKhmkL8WFzZLd0nPC7SpFU2NDWg0Rw3EgbnKv/qJ8B6I3EBtP20LB9eUNe2jQryMl98ir+zzlHpGQi5BSjDRaEwBsEBoTIcsGJbUZ86BfO1kdiKGJ3nFHtx9xVNhyF9a/CF+gK0+QcpidxcaVIkJWYlZRPQ/wDVvJOBv/iL7maRbhtF/i/xschomwpRTokGpmaXEa3Xsw/U6b7cj0Etf4Lyt1eETKywjbPRXOCSQXGpR6LTYkNFfeObv3qcSh/ey9wI97ks6hWxPzZwv3960dyibVdZVlpzKZKM1R/qSPzd9MoX5sIxDiRGNtfrFNgYoDmBIX4VpJmG403UMAqO5axpIqv+x4Bxf2DrzElX+IMx3aYv/795Mg50HpOniJxDVqB0vGxGFTEnGnt+C2DI98/J0VffpXzD7EaxCfqZdg6SuOfHXvqoVFLQNgbyNWwHd20wU0Qzaz75BBI8vH7lw0J7rs1Olv7BXLHWZEJ9Ux1RUdt3UnVIux1C7gzseXvShWHZbtbRjYOR0jF8wweaZuDEIRRREBNpfkG+O+D8Hlg+xF48oayksF", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(39860400002)(376002)(136003)(346002)(36840700001)(46966006)(36860700001)(186003)(82310400003)(1076003)(2906002)(5660300002)(7636003)(83380400001)(107886003)(7696005)(6666004)(4326008)(36756003)(54906003)(478600001)(82740400003)(26005)(86362001)(316002)(110136005)(36906005)(70586007)(2616005)(356005)(16526019)(8676002)(55016002)(426003)(336012)(47076005)(8936002)(6286002)(70206006)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2021 06:51:42.2062 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0f913caf-1b16-409d-94c1-08d90f923da9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3628", "Subject": "[dpdk-dev] [PATCH v3 16/17] net/mlx5: add support of CT between two\n ports", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "After creating a connection tracking context, it can be used between\ntwo ports. For each port, the flow for one direction traffic will\nbe created.\n\nThe context can only be shared between the owner port and the peer\nport that was specified when being created. Only the owner port\ncould update the context or query it in current implementation.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 57 +++++++++++++++++++++++++-\n drivers/net/mlx5/mlx5_flow_dv.c | 71 +++++++++++++++++++++++++--------\n 2 files changed, 110 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 238befa2d4..ddaba40f72 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -48,6 +48,25 @@ enum {\n \tMLX5_INDIRECT_ACTION_TYPE_CT,\n };\n \n+/* Now, the maximal ports will be supported is 256, action number is 4M. */\n+#define MLX5_INDIRECT_ACT_CT_MAX_PORT 0x100\n+\n+#define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 22\n+#define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)\n+\n+/* 30-31: type, 22-29: owner port, 0-21: index. */\n+#define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \\\n+\t((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \\\n+\t (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \\\n+\t MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) | (index))\n+\n+#define MLX5_INDIRECT_ACT_CT_GET_OWNER(index) \\\n+\t(((index) >> MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) & \\\n+\t MLX5_INDIRECT_ACT_CT_OWNER_MASK)\n+\n+#define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \\\n+\t((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))\n+\n /* Matches on selected register. */\n struct mlx5_rte_flow_item_tag {\n \tenum modify_reg id;\n@@ -1304,7 +1323,7 @@ mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)\n }\n \n /*\n- * Get ASO CT action by index.\n+ * Get ASO CT action by device and index.\n *\n * @param[in] dev\n * Pointer to the Ethernet device structure.\n@@ -1315,7 +1334,7 @@ mlx5_aso_meter_by_idx(struct mlx5_priv *priv, uint32_t idx)\n * The specified ASO CT action pointer.\n */\n static inline struct mlx5_aso_ct_action *\n-flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t idx)\n+flow_aso_ct_get_by_dev_idx(struct rte_eth_dev *dev, uint32_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;\n@@ -1330,6 +1349,40 @@ flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t idx)\n \treturn &pool->actions[idx % MLX5_ASO_CT_ACTIONS_PER_POOL];\n }\n \n+/*\n+ * Get ASO CT action by owner & index.\n+ *\n+ * @param[in] dev\n+ * Pointer to the Ethernet device structure.\n+ * @param[in] idx\n+ * Index to the ASO CT action and owner port combination.\n+ *\n+ * @return\n+ * The specified ASO CT action pointer.\n+ */\n+static inline struct mlx5_aso_ct_action *\n+flow_aso_ct_get_by_idx(struct rte_eth_dev *dev, uint32_t own_idx)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_aso_ct_action *ct;\n+\tuint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);\n+\tuint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);\n+\n+\tif (owner == PORT_ID(priv)) {\n+\t\tct = flow_aso_ct_get_by_dev_idx(dev, idx);\n+\t} else {\n+\t\tstruct rte_eth_dev *owndev = &rte_eth_devices[owner];\n+\n+\t\tMLX5_ASSERT(owner < RTE_MAX_ETHPORTS);\n+\t\tif (dev->data->dev_started != 1)\n+\t\t\treturn NULL;\n+\t\tct = flow_aso_ct_get_by_dev_idx(owndev, idx);\n+\t\tif (ct->peer != PORT_ID(priv))\n+\t\t\treturn NULL;\n+\t}\n+\treturn ct;\n+}\n+\n int mlx5_flow_group_to_table(struct rte_eth_dev *dev,\n \t\t\t const struct mlx5_flow_tunnel *tunnel,\n \t\t\t uint32_t group, uint32_t *table,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex aa0a5acdca..ca55cff48b 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -11289,7 +11289,7 @@ flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,\n }\n \n /*\n- * Release an ASO CT action.\n+ * Release an ASO CT action by its own device.\n *\n * @param[in] dev\n * Pointer to the Ethernet device structure.\n@@ -11300,12 +11300,12 @@ flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,\n * 0 when CT action was removed, otherwise the number of references.\n */\n static inline int\n-flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t idx)\n+flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;\n \tuint32_t ret;\n-\tstruct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_idx(dev, idx);\n+\tstruct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);\n \tenum mlx5_aso_ct_state state =\n \t\t\t__atomic_load_n(&ct->state, __ATOMIC_RELAXED);\n \n@@ -11334,7 +11334,21 @@ flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t idx)\n \t\tLIST_INSERT_HEAD(&mng->free_cts, ct, next);\n \t\trte_spinlock_unlock(&mng->ct_sl);\n \t}\n-\treturn ret;\n+\treturn (int)ret;\n+}\n+\n+static inline int\n+flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx)\n+{\n+\tuint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);\n+\tuint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);\n+\tstruct rte_eth_dev *owndev = &rte_eth_devices[owner];\n+\tRTE_SET_USED(dev);\n+\n+\tMLX5_ASSERT(owner < RTE_MAX_ETHPORTS);\n+\tif (dev->data->dev_started != 1)\n+\t\treturn -1;\n+\treturn flow_dv_aso_ct_dev_release(owndev, idx);\n }\n \n /*\n@@ -11486,7 +11500,7 @@ flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)\n \t\tRTE_SET_USED(reg_c);\n #endif\n \t\tif (!ct->dr_action_orig) {\n-\t\t\tflow_dv_aso_ct_release(dev, ct_idx);\n+\t\t\tflow_dv_aso_ct_dev_release(dev, ct_idx);\n \t\t\trte_flow_error_set(error, rte_errno,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t \"failed to create ASO CT action\");\n@@ -11502,7 +11516,7 @@ flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)\n \t\t\t reg_c - REG_C_0);\n #endif\n \t\tif (!ct->dr_action_rply) {\n-\t\t\tflow_dv_aso_ct_release(dev, ct_idx);\n+\t\t\tflow_dv_aso_ct_dev_release(dev, ct_idx);\n \t\t\trte_flow_error_set(error, rte_errno,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t \"failed to create ASO CT action\");\n@@ -11544,12 +11558,13 @@ flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,\n \t\treturn rte_flow_error_set(error, rte_errno,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t \"Failed to allocate CT object\");\n-\tct = flow_aso_ct_get_by_idx(dev, idx);\n+\tct = flow_aso_ct_get_by_dev_idx(dev, idx);\n \tif (mlx5_aso_ct_update_by_wqe(sh, ct, pro))\n \t\treturn rte_flow_error_set(error, EBUSY,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t \"Failed to update CT\");\n \tct->is_original = !!pro->is_original_dir;\n+\tct->peer = pro->peer_port;\n \treturn idx;\n }\n \n@@ -11713,7 +11728,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\tconst struct rte_flow_action *found_action = NULL;\n \t\tuint32_t jump_group = 0;\n \t\tstruct mlx5_flow_counter *cnt;\n-\t\tuint32_t ct_idx;\n+\t\tuint32_t owner_idx;\n \t\tstruct mlx5_aso_ct_action *ct;\n \n \t\tif (!mlx5_flow_os_action_supported(action_type))\n@@ -12189,8 +12204,13 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\taction_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n-\t\t\tct_idx = (uint32_t)(uintptr_t)action->conf;\n-\t\t\tct = flow_aso_ct_get_by_idx(dev, ct_idx);\n+\t\t\towner_idx = (uint32_t)(uintptr_t)action->conf;\n+\t\t\tct = flow_aso_ct_get_by_idx(dev, owner_idx);\n+\t\t\tif (!ct)\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\tNULL,\n+\t\t\t\t\t\t\"Failed to get CT object.\");\n \t\t\tif (mlx5_aso_ct_available(priv->sh, ct))\n \t\t\t\treturn rte_flow_error_set(error, rte_errno,\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION,\n@@ -12203,7 +12223,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t\tdev_flow->dv.actions[actions_n] =\n \t\t\t\t\t\t\tct->dr_action_rply;\n \t\t\tflow->indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;\n-\t\t\tflow->ct = ct_idx;\n+\t\t\tflow->ct = owner_idx;\n \t\t\t__atomic_fetch_add(&ct->refcnt, 1, __ATOMIC_RELAXED);\n \t\t\tactions_n++;\n \t\t\taction_flags |= MLX5_FLOW_ACTION_CT;\n@@ -13803,8 +13823,7 @@ flow_dv_action_create(struct rte_eth_dev *dev,\n \tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n \t\tret = flow_dv_translate_create_conntrack(dev, action->conf,\n \t\t\t\t\t\t\t err);\n-\t\tidx = (MLX5_INDIRECT_ACTION_TYPE_CT <<\n-\t\t MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;\n+\t\tidx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);\n \t\tbreak;\n \tdefault:\n \t\trte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,\n@@ -13856,7 +13875,9 @@ flow_dv_action_destroy(struct rte_eth_dev *dev,\n \t\treturn 0;\n \tcase MLX5_INDIRECT_ACTION_TYPE_CT:\n \t\tret = flow_dv_aso_ct_release(dev, idx);\n-\t\tif (ret)\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tif (ret > 0)\n \t\t\tDRV_LOG(DEBUG, \"Connection tracking object %u still \"\n \t\t\t\t\"has references %d.\", idx, ret);\n \t\treturn 0;\n@@ -13960,8 +13981,16 @@ __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,\n \tstruct mlx5_aso_ct_action *ct;\n \tconst struct rte_flow_action_conntrack *new_prf;\n \tint ret = 0;\n+\tuint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);\n+\tuint32_t dev_idx;\n \n-\tct = flow_aso_ct_get_by_idx(dev, idx);\n+\tif (PORT_ID(priv) != owner)\n+\t\treturn rte_flow_error_set(error, EACCES,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL,\n+\t\t\t\t\t \"CT object owned by another port\");\n+\tdev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);\n+\tct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);\n \tif (!ct->refcnt)\n \t\treturn rte_flow_error_set(error, ENOMEM,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -14049,6 +14078,8 @@ flow_dv_action_query(struct rte_eth_dev *dev,\n \tuint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_ct_action *ct;\n+\tuint16_t owner;\n+\tuint32_t dev_idx;\n \n \tswitch (type) {\n \tcase MLX5_INDIRECT_ACTION_TYPE_AGE:\n@@ -14063,7 +14094,15 @@ flow_dv_action_query(struct rte_eth_dev *dev,\n \t\t\t (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);\n \t\treturn 0;\n \tcase MLX5_INDIRECT_ACTION_TYPE_CT:\n-\t\tct = flow_aso_ct_get_by_idx(dev, idx);\n+\t\towner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);\n+\t\tif (owner != PORT_ID(priv))\n+\t\t\treturn rte_flow_error_set(error, EACCES,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\tNULL,\n+\t\t\t\t\t\"CT object owned by another port\");\n+\t\tdev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);\n+\t\tct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);\n+\t\tMLX5_ASSERT(ct);\n \t\tif (!ct->refcnt)\n \t\t\treturn rte_flow_error_set(error, EFAULT,\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n", "prefixes": [ "v3", "16/17" ] }