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GET /api/patches/92821/?format=api
{ "id": 92821, "url": "http://patches.dpdk.org/api/patches/92821/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210505065008.30680-7-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210505065008.30680-7-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210505065008.30680-7-bingz@nvidia.com", "date": "2021-05-05T06:49:57", "name": "[v3,06/17] net/mlx5: add modify support for CT", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "baf21d9a22ebca5163041d474aa626de377373b2", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210505065008.30680-7-bingz@nvidia.com/mbox/", "series": [ { "id": 16818, "url": "http://patches.dpdk.org/api/series/16818/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16818", "date": "2021-05-05T06:49:53", "name": "[v3,01/17] common/mlx5: add connection tracking object definition", "version": 3, "mbox": "http://patches.dpdk.org/series/16818/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92821/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92821/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 100FDA0524;\n\tWed, 5 May 2021 08:51:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 732B041117;\n\tWed, 5 May 2021 08:51:23 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2089.outbound.protection.outlook.com [40.107.243.89])\n by mails.dpdk.org (Postfix) with ESMTP id 218BF410F0\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Wed, 5 May 2021 09:49:57 +0300", "Message-ID": "<20210505065008.30680-7-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210505065008.30680-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>\n <20210505065008.30680-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "edb5eba8-0fc1-4727-b902-08d90f922db6", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3643:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB364331B2CACD352DF456F5CBD0599@DM6PR12MB3643.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:40;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n nQte5NK4i7M1bYSJMhGE06ifY1VedizmNavpURbYvlBxDw3/VRXbwM/4qNRzIDjGF4plHkOr8y0eYEicwuWw52PkCUueWy7dUxEq3oaYI4wIsKKVkVFOwsUiHJqpfI6IMLixRNcyunKC+SNBSbPGBVj7UE1dgrq2UyA4mzxrSr+JZP1sEfv1GBkte/VUtK0cGdiI9ub66dlBNH2YKypDa0nYYwH9e3FR0GYLXXB1/0zzOKDaPgWjT1zfkPpF9FsYRFCNBNWta5T8IvFOZE4UQmTObdut2W5jOiYx5VLaRStKx8pP/oNm+HpEd/po/8N/hfg9oq6DmbZ/l745ScYflx2/VU5id5sOt2YU700IxXo0+NbEaeZT38/fgt1+w6lCHaSwfzjgCxTPrVaYMODBM6OLzSHdrYUb0PMK+n3lTTNQe9h2vkYr2njIFqv+fhT0G8RzOgHnM93lQ/hhQwXkk2wyu+C9O6qv7QremwlwtGIUJgdbQq5rkAu0mu8vB5iKXPix7c8cM2+OJDy4bX5LyFO8jqiay2VjsGCUFNOFv5a3KoZVu7R79KC71D15NoHXbIgk4dJReVO+PJFyAK2gz3tDsLsv46TTTX2K8u0cRCRbmunaCXLT5zo/LrNPDVN2qp1ffMa/16PJdr7S/0HkKlDJctEWzomTGdBG/JH0QKk=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(346002)(136003)(376002)(39860400002)(46966006)(36840700001)(2906002)(36906005)(30864003)(316002)(8676002)(55016002)(186003)(70206006)(16526019)(426003)(36860700001)(6286002)(1076003)(336012)(54906003)(86362001)(8936002)(110136005)(2616005)(478600001)(4326008)(107886003)(82310400003)(47076005)(70586007)(356005)(5660300002)(82740400003)(7696005)(36756003)(83380400001)(7636003)(26005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2021 06:51:15.4598 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n edb5eba8-0fc1-4727-b902-08d90f922db6", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT046.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3643", "Subject": "[dpdk-dev] [PATCH v3 06/17] net/mlx5: add modify support for CT", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "After the connection tracking object bulk is allocated, all the\nobjects' contents are filled with zero by default. Every\nnew-allocated object must be modified via WQE operation before it is\nused.\n\nIn order to reduce the latency for the flow creation, an asynchronous\nway is used instead of busy waiting for the CQE to be generated.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 8 +\n drivers/net/mlx5/mlx5_flow.h | 3 +\n drivers/net/mlx5/mlx5_flow_aso.c | 252 +++++++++++++++++++++++++++++++\n 3 files changed, 263 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 1a5c78fa3a..1898a0401f 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -490,6 +490,7 @@ struct mlx5_aso_sq_elem {\n \t\t\tuint16_t burst_size;\n \t\t};\n \t\tstruct mlx5_aso_mtr *mtr;\n+\t\tstruct mlx5_aso_ct_action *ct;\n \t};\n };\n \n@@ -1007,6 +1008,10 @@ struct mlx5_aso_ct_action {\n \tbool is_original; /* The direction of the DR action to be used. */\n };\n \n+/* CT action object state update. */\n+#define MLX5_ASO_CT_UPDATE_STATE(c, s) \\\n+\t__atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED)\n+\n /* ASO connection tracking software pool definition. */\n struct mlx5_aso_ct_pool {\n \tuint16_t index; /* Pool index in pools array. */\n@@ -1690,5 +1695,8 @@ int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,\n \t\tstruct mlx5_aso_mtr *mtr);\n int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,\n \t\tstruct mlx5_aso_mtr *mtr);\n+int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,\n+\t\t\t struct mlx5_aso_ct_action *ct,\n+\t\t\t const struct rte_flow_action_conntrack *profile);\n \n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 964e13a869..eb5b53ac6a 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -45,6 +45,7 @@ enum mlx5_rte_flow_action_type {\n enum {\n \tMLX5_INDIRECT_ACTION_TYPE_RSS,\n \tMLX5_INDIRECT_ACTION_TYPE_AGE,\n+\tMLX5_INDIRECT_ACTION_TYPE_AGE,\n };\n \n /* Matches on selected register. */\n@@ -839,6 +840,8 @@ struct mlx5_flow {\n #define MLX5_ASO_WQE_CQE_RESPONSE_DELAY 10u\n #define MLX5_MTR_POLL_WQE_CQE_TIMES 100000u\n \n+#define MLX5_CT_POLL_WQE_CQE_TIMES MLX5_MTR_POLL_WQE_CQE_TIMES\n+\n #define MLX5_MAN_WIDTH 8\n /* Legacy Meter parameter structure. */\n struct mlx5_legacy_flow_meter {\ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex c24d865284..0ff19e6171 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -887,3 +887,255 @@ mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,\n \t\t\tmtr->offset);\n \treturn -1;\n }\n+\n+/*\n+ * Post a WQE to the ASO CT SQ to modify the context.\n+ *\n+ * @param[in] mng\n+ * Pointer to the CT pools management structure.\n+ * @param[in] ct\n+ * Pointer to the generic CT structure related to the context.\n+ * @param[in] profile\n+ * Pointer to configuration profile.\n+ *\n+ * @return\n+ * 1 on success (WQE number), 0 on failure.\n+ */\n+static uint16_t\n+mlx5_aso_ct_sq_enqueue_single(struct mlx5_aso_ct_pools_mng *mng,\n+\t\t\t struct mlx5_aso_ct_action *ct,\n+\t\t\t const struct rte_flow_action_conntrack *profile)\n+{\n+\tvolatile struct mlx5_aso_wqe *wqe = NULL;\n+\tstruct mlx5_aso_sq *sq = &mng->aso_sq;\n+\tuint16_t size = 1 << sq->log_desc_n;\n+\tuint16_t mask = size - 1;\n+\tuint16_t res;\n+\tstruct mlx5_aso_ct_pool *pool;\n+\tvoid *desg;\n+\tvoid *orig_dir;\n+\tvoid *reply_dir;\n+\n+\trte_spinlock_lock(&sq->sqsl);\n+\t/* Prevent other threads to update the index. */\n+\tres = size - (uint16_t)(sq->head - sq->tail);\n+\tif (unlikely(!res)) {\n+\t\trte_spinlock_unlock(&sq->sqsl);\n+\t\tDRV_LOG(ERR, \"Fail: SQ is full and no free WQE to send\");\n+\t\treturn 0;\n+\t}\n+\twqe = &sq->sq_obj.aso_wqes[sq->head & mask];\n+\trte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);\n+\t/* Fill next WQE. */\n+\tMLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_WAIT);\n+\tsq->elts[sq->head & mask].ct = ct;\n+\tpool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);\n+\t/* Each WQE will have a single CT object. */\n+\twqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +\n+\t\t\t\t\t\t ct->offset);\n+\twqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |\n+\t\t\t(ASO_OPC_MOD_CONNECTION_TRACKING <<\n+\t\t\t WQE_CSEG_OPC_MOD_OFFSET) |\n+\t\t\tsq->pi << WQE_CSEG_WQE_INDEX_OFFSET);\n+\twqe->aso_cseg.operand_masks = rte_cpu_to_be_32\n+\t\t\t(0u |\n+\t\t\t (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |\n+\t\t\t (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |\n+\t\t\t (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |\n+\t\t\t (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));\n+\twqe->aso_cseg.data_mask = UINT64_MAX;\n+\t/* To make compiler happy. */\n+\tdesg = (void *)(uintptr_t)wqe->aso_dseg.data;\n+\tMLX5_SET(conn_track_aso, desg, valid, 1);\n+\tMLX5_SET(conn_track_aso, desg, state, profile->state);\n+\tMLX5_SET(conn_track_aso, desg, freeze_track, !profile->enable);\n+\tMLX5_SET(conn_track_aso, desg, connection_assured,\n+\t\t profile->live_connection);\n+\tMLX5_SET(conn_track_aso, desg, sack_permitted, profile->selective_ack);\n+\tMLX5_SET(conn_track_aso, desg, challenged_acked,\n+\t\t profile->challenge_ack_passed);\n+\t/* Heartbeat, retransmission_counter, retranmission_limit_exceeded: 0 */\n+\tMLX5_SET(conn_track_aso, desg, heartbeat, 0);\n+\tMLX5_SET(conn_track_aso, desg, max_ack_window,\n+\t\t profile->max_ack_window);\n+\tMLX5_SET(conn_track_aso, desg, retransmission_counter, 0);\n+\tMLX5_SET(conn_track_aso, desg, retranmission_limit_exceeded, 0);\n+\tMLX5_SET(conn_track_aso, desg, retranmission_limit,\n+\t\t profile->retransmission_limit);\n+\tMLX5_SET(conn_track_aso, desg, reply_direction_tcp_scale,\n+\t\t profile->reply_dir.scale);\n+\tMLX5_SET(conn_track_aso, desg, reply_direction_tcp_close_initiated,\n+\t\t profile->reply_dir.close_initiated);\n+\t/* Both directions will use the same liberal mode. */\n+\tMLX5_SET(conn_track_aso, desg, reply_direction_tcp_liberal_enabled,\n+\t\t profile->liberal_mode);\n+\tMLX5_SET(conn_track_aso, desg, reply_direction_tcp_data_unacked,\n+\t\t profile->reply_dir.data_unacked);\n+\tMLX5_SET(conn_track_aso, desg, reply_direction_tcp_max_ack,\n+\t\t profile->reply_dir.last_ack_seen);\n+\tMLX5_SET(conn_track_aso, desg, original_direction_tcp_scale,\n+\t\t profile->original_dir.scale);\n+\tMLX5_SET(conn_track_aso, desg, original_direction_tcp_close_initiated,\n+\t\t profile->original_dir.close_initiated);\n+\tMLX5_SET(conn_track_aso, desg, original_direction_tcp_liberal_enabled,\n+\t\t profile->liberal_mode);\n+\tMLX5_SET(conn_track_aso, desg, original_direction_tcp_data_unacked,\n+\t\t profile->original_dir.data_unacked);\n+\tMLX5_SET(conn_track_aso, desg, original_direction_tcp_max_ack,\n+\t\t profile->original_dir.last_ack_seen);\n+\tMLX5_SET(conn_track_aso, desg, last_win, profile->last_window);\n+\tMLX5_SET(conn_track_aso, desg, last_dir, profile->last_direction);\n+\tMLX5_SET(conn_track_aso, desg, last_index, profile->last_index);\n+\tMLX5_SET(conn_track_aso, desg, last_seq, profile->last_seq);\n+\tMLX5_SET(conn_track_aso, desg, last_ack, profile->last_ack);\n+\tMLX5_SET(conn_track_aso, desg, last_end, profile->last_end);\n+\torig_dir = MLX5_ADDR_OF(conn_track_aso, desg, original_dir);\n+\tMLX5_SET(tcp_window_params, orig_dir, sent_end,\n+\t\t profile->original_dir.sent_end);\n+\tMLX5_SET(tcp_window_params, orig_dir, reply_end,\n+\t\t profile->original_dir.reply_end);\n+\tMLX5_SET(tcp_window_params, orig_dir, max_win,\n+\t\t profile->original_dir.max_win);\n+\tMLX5_SET(tcp_window_params, orig_dir, max_ack,\n+\t\t profile->original_dir.max_ack);\n+\treply_dir = MLX5_ADDR_OF(conn_track_aso, desg, reply_dir);\n+\tMLX5_SET(tcp_window_params, reply_dir, sent_end,\n+\t\t profile->reply_dir.sent_end);\n+\tMLX5_SET(tcp_window_params, reply_dir, reply_end,\n+\t\t profile->reply_dir.reply_end);\n+\tMLX5_SET(tcp_window_params, reply_dir, max_win,\n+\t\t profile->reply_dir.max_win);\n+\tMLX5_SET(tcp_window_params, reply_dir, max_ack,\n+\t\t profile->reply_dir.max_ack);\n+\tsq->head++;\n+\tsq->pi += 2; /* Each WQE contains 2 WQEBB's. */\n+\trte_io_wmb();\n+\tsq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);\n+\trte_wmb();\n+\t*sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */\n+\trte_wmb();\n+\trte_spinlock_unlock(&sq->sqsl);\n+\treturn 1;\n+}\n+\n+/*\n+ * Update the status field of CTs to indicate ready to be used by flows.\n+ * A continuous number of CTs since last update.\n+ *\n+ * @param[in] sq\n+ * Pointer to ASO CT SQ.\n+ * @param[in] num\n+ * Number of CT structures to be updated.\n+ *\n+ * @return\n+ * 0 on success, a negative value.\n+ */\n+static void\n+mlx5_aso_ct_status_update(struct mlx5_aso_sq *sq, uint16_t num)\n+{\n+\tuint16_t size = 1 << sq->log_desc_n;\n+\tuint16_t mask = size - 1;\n+\tuint16_t i;\n+\tstruct mlx5_aso_ct_action *ct = NULL;\n+\tuint16_t idx;\n+\n+\tfor (i = 0; i < num; i++) {\n+\t\tidx = (uint16_t)((sq->tail + i) & mask);\n+\t\tct = sq->elts[idx].ct;\n+\t\tMLX5_ASSERT(ct);\n+\t\tMLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_READY);\n+\t}\n+}\n+\n+/*\n+ * Handle completions from WQEs sent to ASO CT.\n+ *\n+ * @param[in] mng\n+ * Pointer to the CT pools management structure.\n+ */\n+static void\n+mlx5_aso_ct_completion_handle(struct mlx5_aso_ct_pools_mng *mng)\n+{\n+\tstruct mlx5_aso_sq *sq = &mng->aso_sq;\n+\tstruct mlx5_aso_cq *cq = &sq->cq;\n+\tvolatile struct mlx5_cqe *restrict cqe;\n+\tconst uint32_t cq_size = 1 << cq->log_desc_n;\n+\tconst uint32_t mask = cq_size - 1;\n+\tuint32_t idx;\n+\tuint32_t next_idx;\n+\tuint16_t max;\n+\tuint16_t n = 0;\n+\tint ret;\n+\n+\trte_spinlock_lock(&sq->sqsl);\n+\tmax = (uint16_t)(sq->head - sq->tail);\n+\tif (unlikely(!max)) {\n+\t\trte_spinlock_unlock(&sq->sqsl);\n+\t\treturn;\n+\t}\n+\tnext_idx = cq->cq_ci & mask;\n+\tdo {\n+\t\tidx = next_idx;\n+\t\tnext_idx = (cq->cq_ci + 1) & mask;\n+\t\t/* Need to confirm the position of the prefetch. */\n+\t\trte_prefetch0(&cq->cq_obj.cqes[next_idx]);\n+\t\tcqe = &cq->cq_obj.cqes[idx];\n+\t\tret = check_cqe(cqe, cq_size, cq->cq_ci);\n+\t\t/*\n+\t\t * Be sure owner read is done before any other cookie field or\n+\t\t * opaque field.\n+\t\t */\n+\t\trte_io_rmb();\n+\t\tif (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {\n+\t\t\tif (likely(ret == MLX5_CQE_STATUS_HW_OWN))\n+\t\t\t\tbreak;\n+\t\t\tmlx5_aso_cqe_err_handle(sq);\n+\t\t} else {\n+\t\t\tn++;\n+\t\t}\n+\t\tcq->cq_ci++;\n+\t} while (1);\n+\tif (likely(n)) {\n+\t\tmlx5_aso_ct_status_update(sq, n);\n+\t\tsq->tail += n;\n+\t\trte_io_wmb();\n+\t\tcq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n+\t}\n+\trte_spinlock_unlock(&sq->sqsl);\n+}\n+\n+/*\n+ * Update connection tracking ASO context by sending WQE.\n+ *\n+ * @param[in] sh\n+ * Pointer to mlx5_dev_ctx_shared object.\n+ * @param[in] ct\n+ * Pointer to connection tracking offload object.\n+ * @param[in] profile\n+ * Pointer to connection tracking TCP parameter.\n+ *\n+ * @return\n+ * 0 on success, -1 on failure.\n+ */\n+int\n+mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,\n+\t\t\t struct mlx5_aso_ct_action *ct,\n+\t\t\t const struct rte_flow_action_conntrack *profile)\n+{\n+\tstruct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;\n+\tuint32_t poll_wqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;\n+\tstruct mlx5_aso_ct_pool *pool;\n+\n+\tMLX5_ASSERT(ct);\n+\tdo {\n+\t\tmlx5_aso_ct_completion_handle(mng);\n+\t\tif (mlx5_aso_ct_sq_enqueue_single(mng, ct, profile))\n+\t\t\treturn 0;\n+\t\t/* Waiting for wqe resource. */\n+\t\trte_delay_us_sleep(10u);\n+\t} while (--poll_wqe_times);\n+\tpool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);\n+\tDRV_LOG(ERR, \"Fail to send WQE for ASO CT %d in pool %d\",\n+\t\tct->offset, pool->index);\n+\treturn -1;\n+}\n", "prefixes": [ "v3", "06/17" ] }