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GET /api/patches/92820/?format=api
{ "id": 92820, "url": "http://patches.dpdk.org/api/patches/92820/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210505065008.30680-5-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210505065008.30680-5-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210505065008.30680-5-bingz@nvidia.com", "date": "2021-05-05T06:49:55", "name": "[v3,04/17] net/mlx5: initialization of CT management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "99e53d999dfb997032becafc39dee3ae686ad606", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210505065008.30680-5-bingz@nvidia.com/mbox/", "series": [ { "id": 16818, "url": "http://patches.dpdk.org/api/series/16818/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16818", "date": "2021-05-05T06:49:53", "name": "[v3,01/17] common/mlx5: add connection tracking object definition", "version": 3, "mbox": "http://patches.dpdk.org/series/16818/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92820/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92820/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5E698A0524;\n\tWed, 5 May 2021 08:51:45 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4060341110;\n\tWed, 5 May 2021 08:51:22 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2049.outbound.protection.outlook.com [40.107.244.49])\n by mails.dpdk.org (Postfix) with ESMTP id BA171410F3\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Wed, 5 May 2021 09:49:55 +0300", "Message-ID": "<20210505065008.30680-5-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210505065008.30680-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>\n <20210505065008.30680-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b20f0fb6-29e6-4b85-1348-08d90f922d49", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB4711:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB47117FC894924984E5C75F00D0599@BYAPR12MB4711.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:4941;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n MI/McWlf1yaplkvFu2d18FmF0XTd1wtRi0TlmzTJNyiuxkyC86QhhhF3F3zN+ZDfF3OBkUZPr8CrCMhQVVLg1wC4bP4OPzl/P4ipjbvalX0ktWB4/Z2bLz0GyQVufgiptpO/MAPz9If4vtnQNgkx6eW7J9gHMvuNbtXGL4+YtOAiPs1EmKoL2n3h1LEx+Hq1B97PpVRThI0s4FIBj+lEPcUTknN376zWRdeIAbmloP1l0x0+5YHDLZyTvRnyIFnIx5UdQCrPhPjkbWc+VxEaAdSyYCO3MNEgG79ohLsrkkTqtIkIvJqpW/i+Kb3r4LqC6btq+GgDbGRUU5dAcI2vaizMafLd4cOqm/yMxy/qzTmLhPCcBAonF/T7Sf22b88aE1SBq9JDY7GRLoZ6L6xr/Vi8oslBb9s3OZZIZ5WxslN3W/LiPFA+Z4AQf70+yOUm737aGcpOKz65zZnYIyDUCzN6xNWX4zfm1XStOCWhRTBC+VScTCgmx/8T5FkH/uvOjBt/AE/G1BulXEd1w0nUOZLByLLbF9hlS4HSvobbxiK6Br6/CrivUVulm0QcDp2zJ3ff99MdUqN5os8O2wy3gBcYB0t/IXHe1fD0KAEpNT7rWLiC0qTsHXIEytheYmIypBXIrJTeTeBi0ZlokOfiGPIL41PsDaLjUUuBNlIDbWs=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(346002)(396003)(376002)(39860400002)(36840700001)(46966006)(70206006)(26005)(110136005)(107886003)(86362001)(70586007)(6666004)(186003)(426003)(82740400003)(336012)(7636003)(8676002)(47076005)(82310400003)(316002)(7696005)(478600001)(5660300002)(16526019)(6286002)(2906002)(36756003)(36860700001)(54906003)(2616005)(55016002)(1076003)(83380400001)(356005)(36906005)(8936002)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2021 06:51:14.7372 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b20f0fb6-29e6-4b85-1348-08d90f922d49", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT046.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB4711", "Subject": "[dpdk-dev] [PATCH v3 04/17] net/mlx5: initialization of CT\n management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The definitions of ASO connection tracking objects management\nstructures are added.\n\nConsidering performance, the bulk allocation of ASO CT objects\nshould be used. The maximal value per bulk and the granularity could\nbe fetched from HCA capabilities 2. Right now, a fixed number of 64\nis used for each bulk for a better management purpose.\n\nThe ASO QP for CT is initialized, the SQ will be used for both\nmodify and query command.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 13 +++++++++\n drivers/net/mlx5/mlx5.c | 36 +++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 50 ++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_aso.c | 50 ++++++++++++++++++++++++++++++++\n 4 files changed, 149 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 479ee7d8d1..5ac787106d 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1323,6 +1323,19 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tDRV_LOG(DEBUG, \"Flow Hit ASO is supported.\");\n \t\t}\n #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */\n+#if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \\\n+\tdefined(HAVE_MLX5_DR_ACTION_ASO_CT)\n+\t\tif (config->hca_attr.ct_offload &&\n+\t\t priv->mtr_color_reg == REG_C_3) {\n+\t\t\terr = mlx5_flow_aso_ct_mng_init(sh);\n+\t\t\tif (err) {\n+\t\t\t\terr = -err;\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t\tDRV_LOG(DEBUG, \"CT ASO is supported.\");\n+\t\t\tsh->ct_aso_en = 1;\n+\t\t}\n+#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */\n #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE)\n \t\tif (config->hca_attr.log_max_ft_sampler_num > 0 &&\n \t\t config->dv_flow_en) {\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 8cd6f1eaee..86dbe6d573 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -670,6 +670,42 @@ mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)\n \t}\n }\n \n+/*\n+ * Initialize the ASO connection tracking structure.\n+ *\n+ * @param[in] sh\n+ * Pointer to mlx5_dev_ctx_shared object.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tint err;\n+\n+\tif (sh->ct_mng)\n+\t\treturn 0;\n+\tsh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n+\tif (!sh->ct_mng) {\n+\t\tDRV_LOG(ERR, \"ASO CT management allocation failed.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\terr = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);\n+\tif (err) {\n+\t\tmlx5_free(sh->ct_mng);\n+\t\t/* rte_errno should be extracted from the failure. */\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\trte_spinlock_init(&sh->ct_mng->ct_sl);\n+\trte_rwlock_init(&sh->ct_mng->resize_rwl);\n+\tLIST_INIT(&sh->ct_mng->free_cts);\n+\treturn 0;\n+}\n+\n /**\n * Initialize the flow resources' indexed mempool.\n *\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex c62977613a..1a5c78fa3a 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -983,6 +983,52 @@ struct mlx5_bond_info {\n \t} ports[MLX5_BOND_MAX_PORTS];\n };\n \n+/* Number of connection tracking objects per pool: must be a power of 2. */\n+#define MLX5_ASO_CT_ACTIONS_PER_POOL 64\n+\n+/* ASO Conntrack state. */\n+enum mlx5_aso_ct_state {\n+\tASO_CONNTRACK_FREE, /* Inactive, in the free list. */\n+\tASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */\n+\tASO_CONNTRACK_READY, /* CQE received w/o error. */\n+\tASO_CONNTRACK_QUERY, /* WQE for query sent. */\n+\tASO_CONNTRACK_MAX, /* Guard. */\n+};\n+\n+/* Generic ASO connection tracking structure. */\n+struct mlx5_aso_ct_action {\n+\tLIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */\n+\tvoid *dr_action_orig; /* General action object for original dir. */\n+\tvoid *dr_action_rply; /* General action object for reply dir. */\n+\tuint32_t refcnt; /* Action used count in device flows. */\n+\tuint16_t offset; /* Offset of ASO CT in DevX objects bulk. */\n+\tuint16_t peer; /* The only peer port index could also use this CT. */\n+\tenum mlx5_aso_ct_state state; /* ASO CT state. */\n+\tbool is_original; /* The direction of the DR action to be used. */\n+};\n+\n+/* ASO connection tracking software pool definition. */\n+struct mlx5_aso_ct_pool {\n+\tuint16_t index; /* Pool index in pools array. */\n+\tstruct mlx5_devx_obj *devx_obj;\n+\t/* The first devx object in the bulk, used for freeing (not yet). */\n+\tstruct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL];\n+\t/* CT action structures bulk. */\n+};\n+\n+LIST_HEAD(aso_ct_list, mlx5_aso_ct_action);\n+\n+/* Pools management structure for ASO connection tracking pools. */\n+struct mlx5_aso_ct_pools_mng {\n+\tstruct mlx5_aso_ct_pool **pools;\n+\tuint16_t n; /* Total number of pools. */\n+\tuint16_t next; /* Number of pools in use, index of next free pool. */\n+\trte_spinlock_t ct_sl; /* The ASO CT free list lock. */\n+\trte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */\n+\tstruct aso_ct_list free_cts; /* Free ASO CT objects list. */\n+\tstruct mlx5_aso_sq aso_sq; /* ASO queue objects. */\n+};\n+\n /*\n * Shared Infiniband device context for Master/Representors\n * which belong to same IB device with multiple IB ports.\n@@ -996,6 +1042,7 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t sq_ts_format:2; /* SQ timestamp formats supported. */\n \tuint32_t qp_ts_format:2; /* QP timestamp formats supported. */\n \tuint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */\n+\tuint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */\n \tuint32_t max_port; /* Maximal IB device port index. */\n \tstruct mlx5_bond_info bond; /* Bonding information. */\n \tvoid *ctx; /* Verbs/DV/DevX context. */\n@@ -1058,6 +1105,8 @@ struct mlx5_dev_ctx_shared {\n \trte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */\n \tstruct mlx5_flow_mtr_mng *mtrmng;\n \t/* Meter management structure. */\n+\tstruct mlx5_aso_ct_pools_mng *ct_mng;\n+\t/* Management data for ASO connection tracking. */\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\n \n@@ -1355,6 +1404,7 @@ bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);\n int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);\n int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);\n int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);\n+int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);\n \n /* mlx5_ethdev.c */\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex 300987d0e9..c24d865284 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -186,6 +186,43 @@ mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)\n \t}\n }\n \n+/*\n+ * Initialize Send Queue used for ASO connection tracking.\n+ *\n+ * @param[in] sq\n+ * ASO SQ to initialize.\n+ */\n+static void\n+mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)\n+{\n+\tvolatile struct mlx5_aso_wqe *restrict wqe;\n+\tint i;\n+\tint size = 1 << sq->log_desc_n;\n+\tuint64_t addr;\n+\n+\t/* All the next fields state should stay constant. */\n+\tfor (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {\n+\t\twqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |\n+\t\t\t\t\t\t\t (sizeof(*wqe) >> 4));\n+\t\t/* One unique MR for the query data. */\n+\t\twqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id);\n+\t\t/* Magic number 64 represents the length of a ASO CT obj. */\n+\t\taddr = (uint64_t)((uintptr_t)sq->mr.addr + i * 64);\n+\t\twqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));\n+\t\twqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);\n+\t\t/*\n+\t\t * The values of operand_masks are different for modify\n+\t\t * and query.\n+\t\t * And data_mask may be different for each modification. In\n+\t\t * query, it could be zero and ignored.\n+\t\t * CQE generation is always needed, in order to decide when\n+\t\t * it is available to create the flow or read the data.\n+\t\t */\n+\t\twqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n+\t\t\t\t\t\t MLX5_COMP_MODE_OFFSET);\n+\t}\n+}\n+\n /**\n * Create Send Queue used for ASO access.\n *\n@@ -293,6 +330,19 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,\n \t\t\treturn -1;\n \t\tmlx5_aso_mtr_init_sq(&sh->mtrmng->pools_mng.sq);\n \t\tbreak;\n+\tcase ASO_OPC_MOD_CONNECTION_TRACKING:\n+\t\t/* 64B per object for query. */\n+\t\tif (mlx5_aso_reg_mr(sh, 64 * sq_desc_n,\n+\t\t\t\t &sh->ct_mng->aso_sq.mr, 0))\n+\t\t\treturn -1;\n+\t\tif (mlx5_aso_sq_create(sh->ctx, &sh->ct_mng->aso_sq, 0,\n+\t\t\t\tsh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,\n+\t\t\t\tsh->sq_ts_format)) {\n+\t\t\tmlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tmlx5_aso_ct_init_sq(&sh->ct_mng->aso_sq);\n+\t\tbreak;\n \tdefault:\n \t\tDRV_LOG(ERR, \"Unknown ASO operation mode\");\n \t\treturn -1;\n", "prefixes": [ "v3", "04/17" ] }