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GET /api/patches/92745/?format=api
{ "id": 92745, "url": "http://patches.dpdk.org/api/patches/92745/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-2-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210504175500.3385811-2-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210504175500.3385811-2-matan@nvidia.com", "date": "2021-05-04T17:54:46", "name": "[v3,01/15] common/mlx5: remove redundant spaces in header file", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3cb97405a7def0cac324b98df3597fca4d0ff3c1", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210504175500.3385811-2-matan@nvidia.com/mbox/", "series": [ { "id": 16811, "url": "http://patches.dpdk.org/api/series/16811/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16811", "date": "2021-05-04T17:54:45", "name": "mlx5 common part for crypto driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16811/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92745/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92745/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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SFS:(4636009)(346002)(39860400002)(136003)(396003)(376002)(36840700001)(46966006)(356005)(8676002)(336012)(7636003)(1076003)(82310400003)(83380400001)(2616005)(426003)(47076005)(7696005)(36756003)(4326008)(86362001)(8936002)(107886003)(6286002)(36906005)(6916009)(54906003)(16526019)(186003)(36860700001)(478600001)(316002)(70586007)(6666004)(55016002)(26005)(70206006)(5660300002)(2906002)(82740400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 May 2021 17:55:33.9383 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 908953d4-4513-46dc-8496-08d90f25d0cd", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT014.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5159", "Subject": "[dpdk-dev] [PATCH v3 01/15] common/mlx5: remove redundant spaces in\n header file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@nvidia.com>\n\nFile drivers/common/mlx5/mlx5_prm.h includes structs representing\ndata items as defined in PRM document.\nSome of these structs were copied as-is from kernel file mlx5_ifc.h.\nAs result the structs are not all aligned with the same spacing.\n\nThis patch removes redundant spaces and new lines from several structs,\nto align all structs in mlx5_prm.h to the same format.\n\nSigned-off-by: Dekel Peled <dekelp@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 334 +++++++++++++++------------------\n 1 file changed, 155 insertions(+), 179 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex efa5ae67bf..da1510ac1e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -953,163 +953,139 @@ enum {\n \n /* Flow counters. */\n struct mlx5_ifc_alloc_flow_counter_out_bits {\n-\tu8 status[0x8];\n-\tu8 reserved_at_8[0x18];\n-\tu8 syndrome[0x20];\n-\tu8 flow_counter_id[0x20];\n-\tu8 reserved_at_60[0x20];\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 flow_counter_id[0x20];\n+\tu8 reserved_at_60[0x20];\n };\n \n struct mlx5_ifc_alloc_flow_counter_in_bits {\n-\tu8 opcode[0x10];\n-\tu8 reserved_at_10[0x10];\n-\tu8 reserved_at_20[0x10];\n-\tu8 op_mod[0x10];\n-\tu8 flow_counter_id[0x20];\n-\tu8 reserved_at_40[0x18];\n-\tu8 flow_counter_bulk[0x8];\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 flow_counter_id[0x20];\n+\tu8 reserved_at_40[0x18];\n+\tu8 flow_counter_bulk[0x8];\n };\n \n struct mlx5_ifc_dealloc_flow_counter_out_bits {\n-\tu8 status[0x8];\n-\tu8 reserved_at_8[0x18];\n-\tu8 syndrome[0x20];\n-\tu8 reserved_at_40[0x40];\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n };\n \n struct mlx5_ifc_dealloc_flow_counter_in_bits {\n-\tu8 opcode[0x10];\n-\tu8 reserved_at_10[0x10];\n-\tu8 reserved_at_20[0x10];\n-\tu8 op_mod[0x10];\n-\tu8 flow_counter_id[0x20];\n-\tu8 reserved_at_60[0x20];\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 flow_counter_id[0x20];\n+\tu8 reserved_at_60[0x20];\n };\n \n struct mlx5_ifc_traffic_counter_bits {\n-\tu8 packets[0x40];\n-\tu8 octets[0x40];\n+\tu8 packets[0x40];\n+\tu8 octets[0x40];\n };\n \n struct mlx5_ifc_query_flow_counter_out_bits {\n-\tu8 status[0x8];\n-\tu8 reserved_at_8[0x18];\n-\tu8 syndrome[0x20];\n-\tu8 reserved_at_40[0x40];\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n \tstruct mlx5_ifc_traffic_counter_bits flow_statistics[];\n };\n \n struct mlx5_ifc_query_flow_counter_in_bits {\n-\tu8 opcode[0x10];\n-\tu8 reserved_at_10[0x10];\n-\tu8 reserved_at_20[0x10];\n-\tu8 op_mod[0x10];\n-\tu8 reserved_at_40[0x20];\n-\tu8 mkey[0x20];\n-\tu8 address[0x40];\n-\tu8 clear[0x1];\n-\tu8 dump_to_memory[0x1];\n-\tu8 num_of_counters[0x1e];\n-\tu8 flow_counter_id[0x20];\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x20];\n+\tu8 mkey[0x20];\n+\tu8 address[0x40];\n+\tu8 clear[0x1];\n+\tu8 dump_to_memory[0x1];\n+\tu8 num_of_counters[0x1e];\n+\tu8 flow_counter_id[0x20];\n };\n \n #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u\n #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u\n \n-\n struct mlx5_ifc_klm_bits {\n-\tu8 byte_count[0x20];\n-\tu8 mkey[0x20];\n-\tu8 address[0x40];\n+\tu8 byte_count[0x20];\n+\tu8 mkey[0x20];\n+\tu8 address[0x40];\n };\n \n struct mlx5_ifc_mkc_bits {\n-\tu8 reserved_at_0[0x1];\n-\tu8 free[0x1];\n-\tu8 reserved_at_2[0x1];\n-\tu8 access_mode_4_2[0x3];\n-\tu8 reserved_at_6[0x7];\n-\tu8 relaxed_ordering_write[0x1];\n-\tu8 reserved_at_e[0x1];\n-\tu8 small_fence_on_rdma_read_response[0x1];\n-\tu8 umr_en[0x1];\n-\tu8 a[0x1];\n-\tu8 rw[0x1];\n-\tu8 rr[0x1];\n-\tu8 lw[0x1];\n-\tu8 lr[0x1];\n-\tu8 access_mode_1_0[0x2];\n-\tu8 reserved_at_18[0x8];\n-\n-\tu8 qpn[0x18];\n-\tu8 mkey_7_0[0x8];\n-\n-\tu8 reserved_at_40[0x20];\n-\n-\tu8 length64[0x1];\n-\tu8 bsf_en[0x1];\n-\tu8 sync_umr[0x1];\n-\tu8 reserved_at_63[0x2];\n-\tu8 expected_sigerr_count[0x1];\n-\tu8 reserved_at_66[0x1];\n-\tu8 en_rinval[0x1];\n-\tu8 pd[0x18];\n-\n-\tu8 start_addr[0x40];\n-\n-\tu8 len[0x40];\n-\n-\tu8 bsf_octword_size[0x20];\n-\n-\tu8 reserved_at_120[0x80];\n-\n-\tu8 translations_octword_size[0x20];\n-\n-\tu8 reserved_at_1c0[0x19];\n-\tu8\t\t relaxed_ordering_read[0x1];\n-\tu8\t\t reserved_at_1da[0x1];\n-\tu8 log_page_size[0x5];\n-\n-\tu8 reserved_at_1e0[0x20];\n+\tu8 reserved_at_0[0x1];\n+\tu8 free[0x1];\n+\tu8 reserved_at_2[0x1];\n+\tu8 access_mode_4_2[0x3];\n+\tu8 reserved_at_6[0x7];\n+\tu8 relaxed_ordering_write[0x1];\n+\tu8 reserved_at_e[0x1];\n+\tu8 small_fence_on_rdma_read_response[0x1];\n+\tu8 umr_en[0x1];\n+\tu8 a[0x1];\n+\tu8 rw[0x1];\n+\tu8 rr[0x1];\n+\tu8 lw[0x1];\n+\tu8 lr[0x1];\n+\tu8 access_mode_1_0[0x2];\n+\tu8 reserved_at_18[0x8];\n+\tu8 qpn[0x18];\n+\tu8 mkey_7_0[0x8];\n+\tu8 reserved_at_40[0x20];\n+\tu8 length64[0x1];\n+\tu8 bsf_en[0x1];\n+\tu8 sync_umr[0x1];\n+\tu8 reserved_at_63[0x2];\n+\tu8 expected_sigerr_count[0x1];\n+\tu8 reserved_at_66[0x1];\n+\tu8 en_rinval[0x1];\n+\tu8 pd[0x18];\n+\tu8 start_addr[0x40];\n+\tu8 len[0x40];\n+\tu8 bsf_octword_size[0x20];\n+\tu8 reserved_at_120[0x80];\n+\tu8 translations_octword_size[0x20];\n+\tu8 reserved_at_1c0[0x19];\n+\tu8 relaxed_ordering_read[0x1];\n+\tu8 reserved_at_1da[0x1];\n+\tu8 log_page_size[0x5];\n+\tu8 reserved_at_1e0[0x20];\n };\n \n struct mlx5_ifc_create_mkey_out_bits {\n-\tu8 status[0x8];\n-\tu8 reserved_at_8[0x18];\n-\n-\tu8 syndrome[0x20];\n-\n-\tu8 reserved_at_40[0x8];\n-\tu8 mkey_index[0x18];\n-\n-\tu8 reserved_at_60[0x20];\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 mkey_index[0x18];\n+\tu8 reserved_at_60[0x20];\n };\n \n struct mlx5_ifc_create_mkey_in_bits {\n-\tu8 opcode[0x10];\n-\tu8 reserved_at_10[0x10];\n-\n-\tu8 reserved_at_20[0x10];\n-\tu8 op_mod[0x10];\n-\n-\tu8 reserved_at_40[0x20];\n-\n-\tu8 pg_access[0x1];\n-\tu8 reserved_at_61[0x1f];\n-\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x20];\n+\tu8 pg_access[0x1];\n+\tu8 reserved_at_61[0x1f];\n \tstruct mlx5_ifc_mkc_bits memory_key_mkey_entry;\n-\n-\tu8 reserved_at_280[0x80];\n-\n-\tu8 translations_octword_actual_size[0x20];\n-\n-\tu8 mkey_umem_id[0x20];\n-\n-\tu8 mkey_umem_offset[0x40];\n-\n-\tu8 reserved_at_380[0x500];\n-\n-\tu8 klm_pas_mtt[][0x20];\n+\tu8 reserved_at_280[0x80];\n+\tu8 translations_octword_actual_size[0x20];\n+\tu8 mkey_umem_id[0x20];\n+\tu8 mkey_umem_offset[0x40];\n+\tu8 reserved_at_380[0x500];\n+\tu8 klm_pas_mtt[][0x20];\n };\n \n enum {\n@@ -2272,27 +2248,27 @@ enum {\n };\n \n struct mlx5_ifc_flow_meter_parameters_bits {\n-\tu8 valid[0x1];\t\t\t// 00h\n-\tu8 bucket_overflow[0x1];\n-\tu8 start_color[0x2];\n-\tu8 both_buckets_on_green[0x1];\n-\tu8 meter_mode[0x2];\n-\tu8 reserved_at_1[0x19];\n-\tu8 reserved_at_2[0x20]; //04h\n-\tu8 reserved_at_3[0x3];\n-\tu8 cbs_exponent[0x5];\t\t// 08h\n-\tu8 cbs_mantissa[0x8];\n-\tu8 reserved_at_4[0x3];\n-\tu8 cir_exponent[0x5];\n-\tu8 cir_mantissa[0x8];\n-\tu8 reserved_at_5[0x20];\t\t// 0Ch\n-\tu8 reserved_at_6[0x3];\n-\tu8 ebs_exponent[0x5];\t\t// 10h\n-\tu8 ebs_mantissa[0x8];\n-\tu8 reserved_at_7[0x3];\n-\tu8 eir_exponent[0x5];\n-\tu8 eir_mantissa[0x8];\n-\tu8 reserved_at_8[0x60];\t\t// 14h-1Ch\n+\tu8 valid[0x1];\n+\tu8 bucket_overflow[0x1];\n+\tu8 start_color[0x2];\n+\tu8 both_buckets_on_green[0x1];\n+\tu8 meter_mode[0x2];\n+\tu8 reserved_at_1[0x19];\n+\tu8 reserved_at_2[0x20];\n+\tu8 reserved_at_3[0x3];\n+\tu8 cbs_exponent[0x5];\n+\tu8 cbs_mantissa[0x8];\n+\tu8 reserved_at_4[0x3];\n+\tu8 cir_exponent[0x5];\n+\tu8 cir_mantissa[0x8];\n+\tu8 reserved_at_5[0x20];\n+\tu8 reserved_at_6[0x3];\n+\tu8 ebs_exponent[0x5];\n+\tu8 ebs_mantissa[0x8];\n+\tu8 reserved_at_7[0x3];\n+\tu8 eir_exponent[0x5];\n+\tu8 eir_mantissa[0x8];\n+\tu8 reserved_at_8[0x60];\n };\n #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)\n #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8\n@@ -2359,46 +2335,46 @@ struct mlx5_ifc_cqc_bits {\n };\n \n struct mlx5_ifc_health_buffer_bits {\n-\tu8 reserved_0[0x100];\n-\tu8 assert_existptr[0x20];\n-\tu8 assert_callra[0x20];\n-\tu8 reserved_1[0x40];\n-\tu8 fw_version[0x20];\n-\tu8 hw_id[0x20];\n-\tu8 reserved_2[0x20];\n-\tu8 irisc_index[0x8];\n-\tu8 synd[0x8];\n-\tu8 ext_synd[0x10];\n+\tu8 reserved_0[0x100];\n+\tu8 assert_existptr[0x20];\n+\tu8 assert_callra[0x20];\n+\tu8 reserved_1[0x40];\n+\tu8 fw_version[0x20];\n+\tu8 hw_id[0x20];\n+\tu8 reserved_2[0x20];\n+\tu8 irisc_index[0x8];\n+\tu8 synd[0x8];\n+\tu8 ext_synd[0x10];\n };\n \n struct mlx5_ifc_initial_seg_bits {\n-\tu8 fw_rev_minor[0x10];\n-\tu8 fw_rev_major[0x10];\n-\tu8 cmd_interface_rev[0x10];\n-\tu8 fw_rev_subminor[0x10];\n-\tu8 reserved_0[0x40];\n-\tu8 cmdq_phy_addr_63_32[0x20];\n-\tu8 cmdq_phy_addr_31_12[0x14];\n-\tu8 reserved_1[0x2];\n-\tu8 nic_interface[0x2];\n-\tu8 log_cmdq_size[0x4];\n-\tu8 log_cmdq_stride[0x4];\n-\tu8 command_doorbell_vector[0x20];\n-\tu8 reserved_2[0xf00];\n-\tu8 initializing[0x1];\n-\tu8 nic_interface_supported[0x7];\n-\tu8 reserved_4[0x18];\n+\tu8 fw_rev_minor[0x10];\n+\tu8 fw_rev_major[0x10];\n+\tu8 cmd_interface_rev[0x10];\n+\tu8 fw_rev_subminor[0x10];\n+\tu8 reserved_0[0x40];\n+\tu8 cmdq_phy_addr_63_32[0x20];\n+\tu8 cmdq_phy_addr_31_12[0x14];\n+\tu8 reserved_1[0x2];\n+\tu8 nic_interface[0x2];\n+\tu8 log_cmdq_size[0x4];\n+\tu8 log_cmdq_stride[0x4];\n+\tu8 command_doorbell_vector[0x20];\n+\tu8 reserved_2[0xf00];\n+\tu8 initializing[0x1];\n+\tu8 nic_interface_supported[0x7];\n+\tu8 reserved_4[0x18];\n \tstruct mlx5_ifc_health_buffer_bits health_buffer;\n-\tu8 no_dram_nic_offset[0x20];\n-\tu8 reserved_5[0x6de0];\n-\tu8 internal_timer_h[0x20];\n-\tu8 internal_timer_l[0x20];\n-\tu8 reserved_6[0x20];\n-\tu8 reserved_7[0x1f];\n-\tu8 clear_int[0x1];\n-\tu8 health_syndrome[0x8];\n-\tu8 health_counter[0x18];\n-\tu8 reserved_8[0x17fc0];\n+\tu8 no_dram_nic_offset[0x20];\n+\tu8 reserved_5[0x6de0];\n+\tu8 internal_timer_h[0x20];\n+\tu8 internal_timer_l[0x20];\n+\tu8 reserved_6[0x20];\n+\tu8 reserved_7[0x1f];\n+\tu8 clear_int[0x1];\n+\tu8 health_syndrome[0x8];\n+\tu8 health_counter[0x18];\n+\tu8 reserved_8[0x17fc0];\n };\n \n struct mlx5_ifc_create_cq_out_bits {\n", "prefixes": [ "v3", "01/15" ] }