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GET /api/patches/92670/?format=api
{ "id": 92670, "url": "http://patches.dpdk.org/api/patches/92670/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-33-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-33-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-33-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:35", "name": "[v4,32/34] event/cnxk: add timer stats get and reset", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ba7cadf970c24b68354da097edf23d47bb51fa07", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-33-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92670/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92670/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C550AA0562;\n\tMon, 3 May 2021 17:26:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B43E34113C;\n\tMon, 3 May 2021 17:24:42 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0327D4118F\n for <dev@dpdk.org>; Mon, 3 May 2021 17:24:40 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FA9tL032495 for <dev@dpdk.org>; Mon, 3 May 2021 08:24:40 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 38ad05herb-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 03 May 2021 08:24:40 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:24:38 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:24:38 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 7A5213F703F;\n Mon, 3 May 2021 08:24:36 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=VLerbvCYDRMQyLw9SUPECMAGfCDV9Uh6w8+xs8tjtKs=;\n b=aePi46M0na0W8IV209RDYEKLD3RT2Xk+7qFyaJ/kUBip8Sq8BiubbqMBfzPN4/AaY3hC\n Q5HQh5A/gFbT/qh1C0DIfyLzrTOuQjAAb8CxB/nxWFGIlXgn4PozQes+tZM2Orer+oOa\n zimjBXPeA/5qMk2L0XSywBjWy5a8Vdob3qwiEzUdaIkN/uHgqkt27Kj8DEqh55F89zjL\n 8m+EuPOwzBtlEecJfpz0sYWzkr+nK/KPENqq29jClS4aFtp7PqJCNGU2ourDVH0v4V88\n ByvjjrB/xtnVf8MpSMiAk2h37ihtcNXu+DNUoI8/9rwAdPoIy32bP7aXLN4ix2gQitEy eA==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:35 +0530", "Message-ID": "<20210503152238.2437-33-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "qkeEy_LEHTdaI3J_DiBEy0rN3O5ey5ac", "X-Proofpoint-ORIG-GUID": "qkeEy_LEHTdaI3J_DiBEy0rN3O5ey5ac", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 32/34] event/cnxk: add timer stats get and\n reset", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nAdd event timer adapter statistics get and reset functions.\nStats are disabled by default and can be enabled through devargs.\n\nExample:\n\t--dev \"0002:1e:00.0,tim_stats_ena=1\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 9 +++++\n drivers/event/cnxk/cn10k_eventdev.c | 3 +-\n drivers/event/cnxk/cn9k_eventdev.c | 3 +-\n drivers/event/cnxk/cnxk_tim_evdev.c | 50 ++++++++++++++++++++++++----\n drivers/event/cnxk/cnxk_tim_evdev.h | 38 ++++++++++++++-------\n drivers/event/cnxk/cnxk_tim_worker.c | 11 ++++--\n 6 files changed, 91 insertions(+), 23 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex a8199aac7..11145dd7d 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -115,6 +115,15 @@ Runtime Config Options\n \n -a 0002:0e:00.0,tim_chnk_slots=1023\n \n+- ``TIM enable arm/cancel statistics``\n+\n+ The ``tim_stats_ena`` devargs can be used to enable arm and cancel stats of\n+ event timer adapter.\n+\n+ For example::\n+\n+ -a 0002:0e:00.0,tim_stats_ena=1\n+\n - ``TIM limit max rings reserved``\n \n The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex cadc792a7..bf4052c76 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -505,4 +505,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\"\n \t\t\t CN10K_SSO_GW_MODE \"=<int>\"\n \t\t\t CNXK_TIM_DISABLE_NPA \"=1\"\n \t\t\t CNXK_TIM_CHNK_SLOTS \"=<int>\"\n-\t\t\t CNXK_TIM_RINGS_LMT \"=<int>\");\n+\t\t\t CNXK_TIM_RINGS_LMT \"=<int>\"\n+\t\t\t CNXK_TIM_STATS_ENA \"=1\");\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex e503f6b1c..0684417ea 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -574,4 +574,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT \"=<int>\"\n \t\t\t CN9K_SSO_SINGLE_WS \"=1\"\n \t\t\t CNXK_TIM_DISABLE_NPA \"=1\"\n \t\t\t CNXK_TIM_CHNK_SLOTS \"=<int>\"\n-\t\t\t CNXK_TIM_RINGS_LMT \"=<int>\");\n+\t\t\t CNXK_TIM_RINGS_LMT \"=<int>\"\n+\t\t\t CNXK_TIM_STATS_ENA \"=1\");\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex 62a15a4a1..a73ca33d8 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -81,21 +81,25 @@ cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)\n {\n \tuint8_t prod_flag = !tim_ring->prod_type_sp;\n \n-\t/* [DFB/FB] [SP][MP]*/\n-\tconst rte_event_timer_arm_burst_t arm_burst[2][2] = {\n-#define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name,\n+\t/* [STATS] [DFB/FB] [SP][MP]*/\n+\tconst rte_event_timer_arm_burst_t arm_burst[2][2][2] = {\n+#define FP(_name, _f3, _f2, _f1, flags) \\\n+\t[_f3][_f2][_f1] = cnxk_tim_arm_burst_##_name,\n \t\tTIM_ARM_FASTPATH_MODES\n #undef FP\n \t};\n \n-\tconst rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2] = {\n-#define FP(_name, _f1, flags) [_f1] = cnxk_tim_arm_tmo_tick_burst_##_name,\n+\tconst rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2] = {\n+#define FP(_name, _f2, _f1, flags) \\\n+\t[_f2][_f1] = cnxk_tim_arm_tmo_tick_burst_##_name,\n \t\tTIM_ARM_TMO_FASTPATH_MODES\n #undef FP\n \t};\n \n-\tcnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag];\n-\tcnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb];\n+\tcnxk_tim_ops.arm_burst =\n+\t\tarm_burst[tim_ring->enable_stats][tim_ring->ena_dfb][prod_flag];\n+\tcnxk_tim_ops.arm_tmo_tick_burst =\n+\t\tarm_tmo_burst[tim_ring->enable_stats][tim_ring->ena_dfb];\n \tcnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst;\n }\n \n@@ -159,6 +163,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->nb_timers = rcfg->nb_timers;\n \ttim_ring->chunk_sz = dev->chunk_sz;\n \ttim_ring->disable_npa = dev->disable_npa;\n+\ttim_ring->enable_stats = dev->enable_stats;\n \n \tif (tim_ring->disable_npa) {\n \t\ttim_ring->nb_chunks =\n@@ -241,6 +246,30 @@ cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr)\n \treturn 0;\n }\n \n+static int\n+cnxk_tim_stats_get(const struct rte_event_timer_adapter *adapter,\n+\t\t struct rte_event_timer_adapter_stats *stats)\n+{\n+\tstruct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv;\n+\tuint64_t bkt_cyc = cnxk_tim_cntvct() - tim_ring->ring_start_cyc;\n+\n+\tstats->evtim_exp_count =\n+\t\t__atomic_load_n(&tim_ring->arm_cnt, __ATOMIC_RELAXED);\n+\tstats->ev_enq_count = stats->evtim_exp_count;\n+\tstats->adapter_tick_count =\n+\t\trte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div);\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_tim_stats_reset(const struct rte_event_timer_adapter *adapter)\n+{\n+\tstruct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv;\n+\n+\t__atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED);\n+\treturn 0;\n+}\n+\n int\n cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \t\t uint32_t *caps,\n@@ -258,6 +287,11 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \tcnxk_tim_ops.uninit = cnxk_tim_ring_free;\n \tcnxk_tim_ops.get_info = cnxk_tim_ring_info_get;\n \n+\tif (dev->enable_stats) {\n+\t\tcnxk_tim_ops.stats_get = cnxk_tim_stats_get;\n+\t\tcnxk_tim_ops.stats_reset = cnxk_tim_stats_reset;\n+\t}\n+\n \t/* Store evdev pointer for later use. */\n \tdev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;\n \t*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;\n@@ -281,6 +315,8 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)\n \t\t\t &dev->disable_npa);\n \trte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,\n \t\t\t &dev->chunk_slots);\n+\trte_kvargs_process(kvlist, CNXK_TIM_STATS_ENA, &parse_kvargs_flag,\n+\t\t\t &dev->enable_stats);\n \trte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,\n \t\t\t &dev->min_ring_cnt);\n \ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex 001f448d5..b5e4cfc9e 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -36,12 +36,14 @@\n \n #define CNXK_TIM_DISABLE_NPA \"tim_disable_npa\"\n #define CNXK_TIM_CHNK_SLOTS \"tim_chnk_slots\"\n+#define CNXK_TIM_STATS_ENA \"tim_stats_ena\"\n #define CNXK_TIM_RINGS_LMT \"tim_rings_lmt\"\n \n-#define CNXK_TIM_SP\t 0x1\n-#define CNXK_TIM_MP\t 0x2\n-#define CNXK_TIM_ENA_FB\t 0x10\n-#define CNXK_TIM_ENA_DFB 0x20\n+#define CNXK_TIM_SP\t 0x1\n+#define CNXK_TIM_MP\t 0x2\n+#define CNXK_TIM_ENA_FB\t 0x10\n+#define CNXK_TIM_ENA_DFB 0x20\n+#define CNXK_TIM_ENA_STATS 0x40\n \n #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48)\n #define TIM_BUCKET_W1_M_CHUNK_REMAINDER \\\n@@ -82,6 +84,7 @@ struct cnxk_tim_evdev {\n \tuint8_t disable_npa;\n \tuint16_t chunk_slots;\n \tuint16_t min_ring_cnt;\n+\tuint8_t enable_stats;\n };\n \n enum cnxk_tim_clk_src {\n@@ -123,6 +126,7 @@ struct cnxk_tim_ring {\n \tstruct rte_reciprocal_u64 fast_bkt;\n \tuint64_t arm_cnt;\n \tuint8_t prod_type_sp;\n+\tuint8_t enable_stats;\n \tuint8_t disable_npa;\n \tuint8_t ena_dfb;\n \tuint16_t ring_id;\n@@ -212,23 +216,33 @@ cnxk_tim_cntfrq(void)\n #endif\n \n #define TIM_ARM_FASTPATH_MODES \\\n-\tFP(sp, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \\\n-\tFP(mp, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \\\n-\tFP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \\\n-\tFP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP)\n+\tFP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \\\n+\tFP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \\\n+\tFP(fb_sp, 0, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \\\n+\tFP(fb_mp, 0, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) \\\n+\tFP(stats_sp, 1, 0, 0, \\\n+\t CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \\\n+\tFP(stats_mp, 1, 0, 1, \\\n+\t CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \\\n+\tFP(stats_fb_sp, 1, 1, 0, \\\n+\t CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_SP) \\\n+\tFP(stats_fb_mp, 1, 1, 1, \\\n+\t CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_MP)\n \n #define TIM_ARM_TMO_FASTPATH_MODES \\\n-\tFP(dfb, 0, CNXK_TIM_ENA_DFB) \\\n-\tFP(fb, 1, CNXK_TIM_ENA_FB)\n+\tFP(dfb, 0, 0, CNXK_TIM_ENA_DFB) \\\n+\tFP(fb, 0, 1, CNXK_TIM_ENA_FB) \\\n+\tFP(stats_dfb, 1, 0, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB) \\\n+\tFP(stats_fb, 1, 1, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB)\n \n-#define FP(_name, _f2, _f1, flags) \\\n+#define FP(_name, _f3, _f2, _f1, flags) \\\n \tuint16_t cnxk_tim_arm_burst_##_name( \\\n \t\tconst struct rte_event_timer_adapter *adptr, \\\n \t\tstruct rte_event_timer **tim, const uint16_t nb_timers);\n TIM_ARM_FASTPATH_MODES\n #undef FP\n \n-#define FP(_name, _f1, flags) \\\n+#define FP(_name, _f2, _f1, flags) \\\n \tuint16_t cnxk_tim_arm_tmo_tick_burst_##_name( \\\n \t\tconst struct rte_event_timer_adapter *adptr, \\\n \t\tstruct rte_event_timer **tim, const uint64_t timeout_tick, \\\ndiff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c\nindex 98ff143c3..3ce99864a 100644\n--- a/drivers/event/cnxk/cnxk_tim_worker.c\n+++ b/drivers/event/cnxk/cnxk_tim_worker.c\n@@ -86,10 +86,13 @@ cnxk_tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr,\n \t\t}\n \t}\n \n+\tif (flags & CNXK_TIM_ENA_STATS)\n+\t\t__atomic_fetch_add(&tim_ring->arm_cnt, index, __ATOMIC_RELAXED);\n+\n \treturn index;\n }\n \n-#define FP(_name, _f2, _f1, _flags) \\\n+#define FP(_name, _f3, _f2, _f1, _flags) \\\n \tuint16_t __rte_noinline cnxk_tim_arm_burst_##_name( \\\n \t\tconst struct rte_event_timer_adapter *adptr, \\\n \t\tstruct rte_event_timer **tim, const uint16_t nb_timers) \\\n@@ -138,10 +141,14 @@ cnxk_tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr,\n \t\t\tbreak;\n \t}\n \n+\tif (flags & CNXK_TIM_ENA_STATS)\n+\t\t__atomic_fetch_add(&tim_ring->arm_cnt, set_timers,\n+\t\t\t\t __ATOMIC_RELAXED);\n+\n \treturn set_timers;\n }\n \n-#define FP(_name, _f1, _flags) \\\n+#define FP(_name, _f2, _f1, _flags) \\\n \tuint16_t __rte_noinline cnxk_tim_arm_tmo_tick_burst_##_name( \\\n \t\tconst struct rte_event_timer_adapter *adptr, \\\n \t\tstruct rte_event_timer **tim, const uint64_t timeout_tick, \\\n", "prefixes": [ "v4", "32/34" ] }