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GET /api/patches/92661/?format=api
{ "id": 92661, "url": "http://patches.dpdk.org/api/patches/92661/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-24-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-24-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-24-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:26", "name": "[v4,23/34] event/cnxk: create and free timer adapter", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "514f5ffbe71c71d671bcbc23647c744e766f7ca0", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-24-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92661/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92661/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6BE9BA0562;\n\tMon, 3 May 2021 17:25:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3D80B4114D;\n\tMon, 3 May 2021 17:24:12 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 039A04114D\n for <dev@dpdk.org>; Mon, 3 May 2021 17:24:10 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FA9eJ032504 for <dev@dpdk.org>; Mon, 3 May 2021 08:24:10 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 38ad05hepa-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 03 May 2021 08:24:09 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:24:06 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:24:06 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 81DE23F7040;\n Mon, 3 May 2021 08:24:05 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=wQkIuJLy8+HalecaToJLwbvjt0kqHHVHltKdikSmVI4=;\n b=F4yKkQJ75P3b4Mho0SA2zTf1U2KoMli50c9SItEZ3VPSchXs/iCkA1+phBBXGMHp8mNS\n yxRDvDH7+deUgGK8kRyyuK1x7yn27P1/CVnBwBlrQGqrocW6jxx+pyGXm5Noq1urwNfZ\n DeKna1Pl1Yi2VOVdleuPSmdvk2N0kiRyPFEhBQxTwDFm8uUxSMfAj1Vd3nKPs2SUUXab\n yraMFXAlzCgMJRxEXLLvMsLAiaPmn1I6bFtlr0SKtBIz6gLf5INrmY0CHE98ChbC67P9\n 5jmd5m9mDKopAQ24I5oJwJn/i7/ffARm82POdHiMbFq1xi6vzopvKalu8CVxlUBngUWW 1A==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:26 +0530", "Message-ID": "<20210503152238.2437-24-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "22jieWbrpprjufujA1yBSjNX7IbQNnpo", "X-Proofpoint-ORIG-GUID": "22jieWbrpprjufujA1yBSjNX7IbQNnpo", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 23/34] event/cnxk: create and free timer\n adapter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nWhen the application calls timer adapter create the following is used:\n- Allocate a TIM LF based on number of LF's provisioned.\n- Verify the config parameters supplied.\n- Allocate memory required for\n\t* Buckets based on min and max timeout supplied.\n\t* Allocate the chunk pool based on the number of timers.\n\nOn Free:\n\t- Free the allocated bucket and chunk memory.\n\t- Free the TIM lf allocated.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cnxk_tim_evdev.c | 174 ++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_tim_evdev.h | 128 +++++++++++++++++++-\n 2 files changed, 300 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex 265bee533..655540a72 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -5,6 +5,177 @@\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_tim_evdev.h\"\n \n+static struct rte_event_timer_adapter_ops cnxk_tim_ops;\n+\n+static int\n+cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,\n+\t\t\t struct rte_event_timer_adapter_conf *rcfg)\n+{\n+\tunsigned int cache_sz = (tim_ring->nb_chunks / 1.5);\n+\tunsigned int mp_flags = 0;\n+\tchar pool_name[25];\n+\tint rc;\n+\n+\tcache_sz /= rte_lcore_count();\n+\t/* Create chunk pool. */\n+\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {\n+\t\tmp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;\n+\t\tplt_tim_dbg(\"Using single producer mode\");\n+\t\ttim_ring->prod_type_sp = true;\n+\t}\n+\n+\tsnprintf(pool_name, sizeof(pool_name), \"cnxk_tim_chunk_pool%d\",\n+\t\t tim_ring->ring_id);\n+\n+\tif (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)\n+\t\tcache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;\n+\tcache_sz = cache_sz != 0 ? cache_sz : 2;\n+\ttim_ring->nb_chunks += (cache_sz * rte_lcore_count());\n+\ttim_ring->chunk_pool = rte_mempool_create_empty(\n+\t\tpool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, cache_sz, 0,\n+\t\trte_socket_id(), mp_flags);\n+\n+\tif (tim_ring->chunk_pool == NULL) {\n+\t\tplt_err(\"Unable to create chunkpool.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n+\t\t\t\t\trte_mbuf_platform_mempool_ops(), NULL);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to set chunkpool ops\");\n+\t\tgoto free;\n+\t}\n+\n+\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to set populate chunkpool.\");\n+\t\tgoto free;\n+\t}\n+\ttim_ring->aura =\n+\t\troc_npa_aura_handle_to_aura(tim_ring->chunk_pool->pool_id);\n+\ttim_ring->ena_dfb = 0;\n+\n+\treturn 0;\n+\n+free:\n+\trte_mempool_free(tim_ring->chunk_pool);\n+\treturn rc;\n+}\n+\n+static int\n+cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n+{\n+\tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n+\tstruct cnxk_tim_evdev *dev = cnxk_tim_priv_get();\n+\tstruct cnxk_tim_ring *tim_ring;\n+\tint rc;\n+\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\tif (adptr->data->id >= dev->nb_rings)\n+\t\treturn -ENODEV;\n+\n+\ttim_ring = rte_zmalloc(\"cnxk_tim_prv\", sizeof(struct cnxk_tim_ring), 0);\n+\tif (tim_ring == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trc = roc_tim_lf_alloc(&dev->tim, adptr->data->id, NULL);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to create timer ring\");\n+\t\tgoto tim_ring_free;\n+\t}\n+\n+\tif (NSEC2TICK(RTE_ALIGN_MUL_CEIL(\n+\t\t\t rcfg->timer_tick_ns,\n+\t\t\t cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())),\n+\t\t cnxk_tim_cntfrq()) <\n+\t cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) {\n+\t\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)\n+\t\t\trcfg->timer_tick_ns = TICK2NSEC(\n+\t\t\t\tcnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()),\n+\t\t\t\tcnxk_tim_cntfrq());\n+\t\telse {\n+\t\t\trc = -ERANGE;\n+\t\t\tgoto tim_hw_free;\n+\t\t}\n+\t}\n+\ttim_ring->ring_id = adptr->data->id;\n+\ttim_ring->clk_src = (int)rcfg->clk_src;\n+\ttim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(\n+\t\trcfg->timer_tick_ns,\n+\t\tcnxk_tim_min_resolution_ns(cnxk_tim_cntfrq()));\n+\ttim_ring->max_tout = rcfg->max_tmo_ns;\n+\ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n+\ttim_ring->nb_timers = rcfg->nb_timers;\n+\ttim_ring->chunk_sz = dev->chunk_sz;\n+\n+\ttim_ring->nb_chunks = tim_ring->nb_timers;\n+\ttim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n+\t/* Create buckets. */\n+\ttim_ring->bkt =\n+\t\trte_zmalloc(\"cnxk_tim_bucket\",\n+\t\t\t (tim_ring->nb_bkts) * sizeof(struct cnxk_tim_bkt),\n+\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (tim_ring->bkt == NULL)\n+\t\tgoto tim_hw_free;\n+\n+\trc = cnxk_tim_chnk_pool_create(tim_ring, rcfg);\n+\tif (rc < 0)\n+\t\tgoto tim_bkt_free;\n+\n+\trc = roc_tim_lf_config(\n+\t\t&dev->tim, tim_ring->ring_id,\n+\t\tcnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0,\n+\t\ttim_ring->nb_bkts, tim_ring->chunk_sz,\n+\t\tNSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()));\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to configure timer ring\");\n+\t\tgoto tim_chnk_free;\n+\t}\n+\n+\ttim_ring->base = roc_tim_lf_base_get(&dev->tim, tim_ring->ring_id);\n+\tplt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);\n+\tplt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);\n+\n+\tplt_tim_dbg(\n+\t\t\"Total memory used %\" PRIu64 \"MB\\n\",\n+\t\t(uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +\n+\t\t\t (tim_ring->nb_bkts * sizeof(struct cnxk_tim_bkt))) /\n+\t\t\t BIT_ULL(20)));\n+\n+\tadptr->data->adapter_priv = tim_ring;\n+\treturn rc;\n+\n+tim_chnk_free:\n+\trte_mempool_free(tim_ring->chunk_pool);\n+tim_bkt_free:\n+\trte_free(tim_ring->bkt);\n+tim_hw_free:\n+\troc_tim_lf_free(&dev->tim, tim_ring->ring_id);\n+tim_ring_free:\n+\trte_free(tim_ring);\n+\treturn rc;\n+}\n+\n+static int\n+cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr)\n+{\n+\tstruct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;\n+\tstruct cnxk_tim_evdev *dev = cnxk_tim_priv_get();\n+\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\troc_tim_lf_free(&dev->tim, tim_ring->ring_id);\n+\trte_free(tim_ring->bkt);\n+\trte_mempool_free(tim_ring->chunk_pool);\n+\trte_free(tim_ring);\n+\n+\treturn 0;\n+}\n+\n int\n cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \t\t uint32_t *caps,\n@@ -18,6 +189,9 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \tif (dev == NULL)\n \t\treturn -ENODEV;\n \n+\tcnxk_tim_ops.init = cnxk_tim_ring_create;\n+\tcnxk_tim_ops.uninit = cnxk_tim_ring_free;\n+\n \t/* Store evdev pointer for later use. */\n \tdev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;\n \t*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex ece66ab25..2335707cd 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -12,12 +12,26 @@\n \n #include <eventdev_pmd_pci.h>\n #include <rte_event_timer_adapter.h>\n+#include <rte_malloc.h>\n #include <rte_memzone.h>\n \n #include \"roc_api.h\"\n \n-#define CNXK_TIM_EVDEV_NAME\t cnxk_tim_eventdev\n-#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)\n+#define NSECPERSEC\t\t 1E9\n+#define USECPERSEC\t\t 1E6\n+#define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))\n+\n+#define CNXK_TIM_EVDEV_NAME\t cnxk_tim_eventdev\n+#define CNXK_TIM_MAX_BUCKETS\t (0xFFFFF)\n+#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)\n+#define CNXK_TIM_CHUNK_ALIGNMENT (16)\n+#define CNXK_TIM_MAX_BURST\t \\\n+\t\t\t(RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)\n+#define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)\n+#define CNXK_TIM_MIN_CHUNK_SLOTS (0x1)\n+#define CNXK_TIM_MAX_CHUNK_SLOTS (0x1FFE)\n+\n+#define CN9K_TIM_MIN_TMO_TKS (256)\n \n struct cnxk_tim_evdev {\n \tstruct roc_tim tim;\n@@ -26,6 +40,57 @@ struct cnxk_tim_evdev {\n \tuint32_t chunk_sz;\n };\n \n+enum cnxk_tim_clk_src {\n+\tCNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,\n+\tCNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,\n+\tCNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,\n+\tCNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,\n+};\n+\n+struct cnxk_tim_bkt {\n+\tuint64_t first_chunk;\n+\tunion {\n+\t\tuint64_t w1;\n+\t\tstruct {\n+\t\t\tuint32_t nb_entry;\n+\t\t\tuint8_t sbt : 1;\n+\t\t\tuint8_t hbt : 1;\n+\t\t\tuint8_t bsk : 1;\n+\t\t\tuint8_t rsvd : 5;\n+\t\t\tuint8_t lock;\n+\t\t\tint16_t chunk_remainder;\n+\t\t};\n+\t};\n+\tuint64_t current_chunk;\n+\tuint64_t pad;\n+};\n+\n+struct cnxk_tim_ring {\n+\tuintptr_t base;\n+\tuint16_t nb_chunk_slots;\n+\tuint32_t nb_bkts;\n+\tuint64_t tck_int;\n+\tuint64_t tot_int;\n+\tstruct cnxk_tim_bkt *bkt;\n+\tstruct rte_mempool *chunk_pool;\n+\tuint64_t arm_cnt;\n+\tuint8_t prod_type_sp;\n+\tuint8_t ena_dfb;\n+\tuint16_t ring_id;\n+\tuint32_t aura;\n+\tuint64_t nb_timers;\n+\tuint64_t tck_nsec;\n+\tuint64_t max_tout;\n+\tuint64_t nb_chunks;\n+\tuint64_t chunk_sz;\n+\tenum cnxk_tim_clk_src clk_src;\n+} __rte_cache_aligned;\n+\n+struct cnxk_tim_ent {\n+\tuint64_t w0;\n+\tuint64_t wqe;\n+};\n+\n static inline struct cnxk_tim_evdev *\n cnxk_tim_priv_get(void)\n {\n@@ -38,6 +103,65 @@ cnxk_tim_priv_get(void)\n \treturn mz->addr;\n }\n \n+static inline uint64_t\n+cnxk_tim_min_tmo_ticks(uint64_t freq)\n+{\n+\tif (roc_model_runtime_is_cn9k())\n+\t\treturn CN9K_TIM_MIN_TMO_TKS;\n+\telse /* CN10K min tick is of 1us */\n+\t\treturn freq / USECPERSEC;\n+}\n+\n+static inline uint64_t\n+cnxk_tim_min_resolution_ns(uint64_t freq)\n+{\n+\treturn NSECPERSEC / freq;\n+}\n+\n+static inline enum roc_tim_clk_src\n+cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)\n+{\n+\tswitch (clk_src) {\n+\tcase RTE_EVENT_TIMER_ADAPTER_CPU_CLK:\n+\t\treturn roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :\n+\t\t\t\t\t\t\t ROC_TIM_CLK_SRC_GTI;\n+\tdefault:\n+\t\treturn ROC_TIM_CLK_SRC_INVALID;\n+\t}\n+}\n+\n+#ifdef RTE_ARCH_ARM64\n+static inline uint64_t\n+cnxk_tim_cntvct(void)\n+{\n+\tuint64_t tsc;\n+\n+\tasm volatile(\"mrs %0, cntvct_el0\" : \"=r\"(tsc));\n+\treturn tsc;\n+}\n+\n+static inline uint64_t\n+cnxk_tim_cntfrq(void)\n+{\n+\tuint64_t freq;\n+\n+\tasm volatile(\"mrs %0, cntfrq_el0\" : \"=r\"(freq));\n+\treturn freq;\n+}\n+#else\n+static inline uint64_t\n+cnxk_tim_cntvct(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline uint64_t\n+cnxk_tim_cntfrq(void)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\t uint32_t *caps,\n \t\t const struct rte_event_timer_adapter_ops **ops);\n", "prefixes": [ "v4", "23/34" ] }