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GET /api/patches/92658/?format=api
{ "id": 92658, "url": "http://patches.dpdk.org/api/patches/92658/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-21-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-21-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-21-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:23", "name": "[v4,20/34] event/cnxk: add event port and queue xstats", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "670b928fedfd43cd8b7258efb9ec9798e8d632c1", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-21-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92658/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92658/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE1BDA0562;\n\tMon, 3 May 2021 17:25:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 09CFF41113;\n\tMon, 3 May 2021 17:24:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 83E5F41153\n for <dev@dpdk.org>; Mon, 3 May 2021 17:24:01 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FAqEY032464; Mon, 3 May 2021 08:23:58 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 38agtfgv3p-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 03 May 2021 08:23:58 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:23:56 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:23:56 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 00B3E3F703F;\n Mon, 3 May 2021 08:23:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=uBF+UsGDnFLx/5AhGznfAqHC6L6DMPhcy+82GzHqa84=;\n b=QK4NU9//Cp+zRBLgOp5sKVAG8FS1akn0FJRAz38CC9WbCgr1grz502LT5Y95ms909WUs\n eDNTr7aiaPX9pQhFFDjkX3dQ93WvTOk6R5CeHX4h2utPe0xiAgXqTF2MNNL6Rakzexon\n 1RfpJN1oyTpfiBJ2ZoxkC0+kh97s2xA+Z3DdIPHYNJle7Yiv7hZv5zSvhbfiwhObZN9I\n MZeWbhQtWSHRaBDXRJlAyEgsMo/qoD9VSlNjlwKHeIVwjefBJ6Gwz9UvJ5/swAcuHGel\n 1V/Lbwc7pkQ/VDEBE5Cr8QMAa1fupUGHkUlz8fZoYCOwiDLa8AQ9yo/Lymm0P9wcttf8 mQ==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>,\n Neil Horman <nhorman@tuxdriver.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:23 +0530", "Message-ID": "<20210503152238.2437-21-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "GCvNPCckWgs2L8ceB3q06czzLUK73-Pf", "X-Proofpoint-ORIG-GUID": "GCvNPCckWgs2L8ceB3q06czzLUK73-Pf", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 20/34] event/cnxk: add event port and queue\n xstats", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd support for retrieving statistics from SSO HWS and HWGRP.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/roc_sso.c | 63 +++++\n drivers/common/cnxk/roc_sso.h | 19 ++\n drivers/common/cnxk/version.map | 2 +\n drivers/event/cnxk/cnxk_eventdev.h | 15 ++\n drivers/event/cnxk/cnxk_eventdev_stats.c | 289 +++++++++++++++++++++++\n drivers/event/cnxk/meson.build | 3 +-\n 6 files changed, 390 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/cnxk/cnxk_eventdev_stats.c", "diff": "diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex 80d032039..1ccf2626b 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -279,6 +279,69 @@ roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n \treturn nb_hwgrp;\n }\n \n+int\n+roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws,\n+\t\t struct roc_sso_hws_stats *stats)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso_hws_stats *req_rsp;\n+\tint rc;\n+\n+\treq_rsp = (struct sso_hws_stats *)mbox_alloc_msg_sso_hws_get_stats(\n+\t\tdev->mbox);\n+\tif (req_rsp == NULL) {\n+\t\trc = mbox_process(dev->mbox);\n+\t\tif (rc < 0)\n+\t\t\treturn rc;\n+\t\treq_rsp = (struct sso_hws_stats *)\n+\t\t\tmbox_alloc_msg_sso_hws_get_stats(dev->mbox);\n+\t\tif (req_rsp == NULL)\n+\t\t\treturn -ENOSPC;\n+\t}\n+\treq_rsp->hws = hws;\n+\trc = mbox_process_msg(dev->mbox, (void **)&req_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tstats->arbitration = req_rsp->arbitration;\n+\treturn 0;\n+}\n+\n+int\n+roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp,\n+\t\t\tstruct roc_sso_hwgrp_stats *stats)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso_grp_stats *req_rsp;\n+\tint rc;\n+\n+\treq_rsp = (struct sso_grp_stats *)mbox_alloc_msg_sso_grp_get_stats(\n+\t\tdev->mbox);\n+\tif (req_rsp == NULL) {\n+\t\trc = mbox_process(dev->mbox);\n+\t\tif (rc < 0)\n+\t\t\treturn rc;\n+\t\treq_rsp = (struct sso_grp_stats *)\n+\t\t\tmbox_alloc_msg_sso_grp_get_stats(dev->mbox);\n+\t\tif (req_rsp == NULL)\n+\t\t\treturn -ENOSPC;\n+\t}\n+\treq_rsp->grp = hwgrp;\n+\trc = mbox_process_msg(dev->mbox, (void **)&req_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tstats->aw_status = req_rsp->aw_status;\n+\tstats->dq_pc = req_rsp->dq_pc;\n+\tstats->ds_pc = req_rsp->ds_pc;\n+\tstats->ext_pc = req_rsp->ext_pc;\n+\tstats->page_cnt = req_rsp->page_cnt;\n+\tstats->ts_pc = req_rsp->ts_pc;\n+\tstats->wa_pc = req_rsp->wa_pc;\n+\tstats->ws_pc = req_rsp->ws_pc;\n+\treturn 0;\n+}\n+\n int\n roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws,\n \t\t\t uint16_t hwgrp)\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex f85799ba8..a6030e7d8 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -12,6 +12,21 @@ struct roc_sso_hwgrp_qos {\n \tuint8_t taq_prcnt;\n };\n \n+struct roc_sso_hws_stats {\n+\tuint64_t arbitration;\n+};\n+\n+struct roc_sso_hwgrp_stats {\n+\tuint64_t ws_pc;\n+\tuint64_t ext_pc;\n+\tuint64_t wa_pc;\n+\tuint64_t ts_pc;\n+\tuint64_t ds_pc;\n+\tuint64_t dq_pc;\n+\tuint64_t aw_status;\n+\tuint64_t page_cnt;\n+};\n+\n struct roc_sso {\n \tstruct plt_pci_device *pci_dev;\n \t/* Public data. */\n@@ -61,5 +76,9 @@ uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso,\n /* Debug */\n void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws,\n \t\t\t uint16_t hwgrp, FILE *f);\n+int __roc_api roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp,\n+\t\t\t\t struct roc_sso_hwgrp_stats *stats);\n+int __roc_api roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws,\n+\t\t\t\t struct roc_sso_hws_stats *stats);\n \n #endif /* _ROC_SSOW_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 5f2264f23..8e67c83a6 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -183,8 +183,10 @@ INTERNAL {\n \troc_sso_hwgrp_qos_config;\n \troc_sso_hwgrp_release_xaq;\n \troc_sso_hwgrp_set_priority;\n+\troc_sso_hwgrp_stats_get;\n \troc_sso_hws_base_get;\n \troc_sso_hws_link;\n+\troc_sso_hws_stats_get;\n \troc_sso_hws_unlink;\n \troc_sso_ns_to_gw;\n \troc_sso_rsrc_fini;\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 9af04bc3d..abe36f21f 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -214,6 +214,21 @@ int cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn);\n int cnxk_sso_selftest(const char *dev_name);\n void cnxk_sso_dump(struct rte_eventdev *event_dev, FILE *f);\n \n+/* Stats API. */\n+int cnxk_sso_xstats_get_names(const struct rte_eventdev *event_dev,\n+\t\t\t enum rte_event_dev_xstats_mode mode,\n+\t\t\t uint8_t queue_port_id,\n+\t\t\t struct rte_event_dev_xstats_name *xstats_names,\n+\t\t\t unsigned int *ids, unsigned int size);\n+int cnxk_sso_xstats_get(const struct rte_eventdev *event_dev,\n+\t\t\tenum rte_event_dev_xstats_mode mode,\n+\t\t\tuint8_t queue_port_id, const unsigned int ids[],\n+\t\t\tuint64_t values[], unsigned int n);\n+int cnxk_sso_xstats_reset(struct rte_eventdev *event_dev,\n+\t\t\t enum rte_event_dev_xstats_mode mode,\n+\t\t\t int16_t queue_port_id, const uint32_t ids[],\n+\t\t\t uint32_t n);\n+\n /* CN9K */\n void cn9k_sso_set_rsrc(void *arg);\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev_stats.c b/drivers/event/cnxk/cnxk_eventdev_stats.c\nnew file mode 100644\nindex 000000000..a3b548f46\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_eventdev_stats.c\n@@ -0,0 +1,289 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cnxk_eventdev.h\"\n+\n+struct cnxk_sso_xstats_name {\n+\tconst char name[RTE_EVENT_DEV_XSTATS_NAME_SIZE];\n+\tconst size_t offset;\n+\tconst uint64_t mask;\n+\tconst uint8_t shift;\n+\tuint64_t reset_snap[CNXK_SSO_MAX_HWGRP];\n+};\n+\n+static struct cnxk_sso_xstats_name sso_hws_xstats[] = {\n+\t{\n+\t\t\"last_grp_serviced\",\n+\t\toffsetof(struct roc_sso_hws_stats, arbitration),\n+\t\t0x3FF,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"affinity_arbitration_credits\",\n+\t\toffsetof(struct roc_sso_hws_stats, arbitration),\n+\t\t0xF,\n+\t\t16,\n+\t\t{0},\n+\t},\n+};\n+\n+static struct cnxk_sso_xstats_name sso_hwgrp_xstats[] = {\n+\t{\n+\t\t\"wrk_sched\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, ws_pc),\n+\t\t~0x0,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"xaq_dram\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, ext_pc),\n+\t\t~0x0,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"add_wrk\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, wa_pc),\n+\t\t~0x0,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"tag_switch_req\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, ts_pc),\n+\t\t~0x0,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"desched_req\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, ds_pc),\n+\t\t~0x0,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"desched_wrk\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, dq_pc),\n+\t\t~0x0,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"xaq_cached\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, aw_status),\n+\t\t0x3,\n+\t\t0,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"work_inflight\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, aw_status),\n+\t\t0x3F,\n+\t\t16,\n+\t\t{0},\n+\t},\n+\t{\n+\t\t\"inuse_pages\",\n+\t\toffsetof(struct roc_sso_hwgrp_stats, page_cnt),\n+\t\t0xFFFFFFFF,\n+\t\t0,\n+\t\t{0},\n+\t},\n+};\n+\n+#define CNXK_SSO_NUM_HWS_XSTATS RTE_DIM(sso_hws_xstats)\n+#define CNXK_SSO_NUM_GRP_XSTATS RTE_DIM(sso_hwgrp_xstats)\n+\n+#define CNXK_SSO_NUM_XSTATS (CNXK_SSO_NUM_HWS_XSTATS + CNXK_SSO_NUM_GRP_XSTATS)\n+\n+int\n+cnxk_sso_xstats_get(const struct rte_eventdev *event_dev,\n+\t\t enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,\n+\t\t const unsigned int ids[], uint64_t values[], unsigned int n)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tstruct roc_sso_hwgrp_stats hwgrp_stats;\n+\tstruct cnxk_sso_xstats_name *xstats;\n+\tstruct cnxk_sso_xstats_name *xstat;\n+\tstruct roc_sso_hws_stats hws_stats;\n+\tuint32_t xstats_mode_count = 0;\n+\tuint32_t start_offset = 0;\n+\tunsigned int i;\n+\tuint64_t value;\n+\tvoid *rsp;\n+\tint rc;\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\treturn 0;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = CNXK_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_hws_xstats;\n+\n+\t\trc = roc_sso_hws_stats_get(&dev->sso, queue_port_id,\n+\t\t\t\t\t &hws_stats);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\t\trsp = &hws_stats;\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = CNXK_SSO_NUM_GRP_XSTATS;\n+\t\tstart_offset = CNXK_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_hwgrp_xstats;\n+\n+\t\trc = roc_sso_hwgrp_stats_get(&dev->sso, queue_port_id,\n+\t\t\t\t\t &hwgrp_stats);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\t\trsp = &hwgrp_stats;\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tplt_err(\"Invalid mode received\");\n+\t\tgoto invalid_value;\n+\t};\n+\n+\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n+\t\txstat = &xstats[ids[i] - start_offset];\n+\t\tvalue = *(uint64_t *)((char *)rsp + xstat->offset);\n+\t\tvalue = (value >> xstat->shift) & xstat->mask;\n+\n+\t\tvalues[i] = value;\n+\t\tvalues[i] -= xstat->reset_snap[queue_port_id];\n+\t}\n+\n+\treturn i;\n+invalid_value:\n+\treturn -EINVAL;\n+}\n+\n+int\n+cnxk_sso_xstats_reset(struct rte_eventdev *event_dev,\n+\t\t enum rte_event_dev_xstats_mode mode,\n+\t\t int16_t queue_port_id, const uint32_t ids[], uint32_t n)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tstruct roc_sso_hwgrp_stats hwgrp_stats;\n+\tstruct cnxk_sso_xstats_name *xstats;\n+\tstruct cnxk_sso_xstats_name *xstat;\n+\tstruct roc_sso_hws_stats hws_stats;\n+\tuint32_t xstats_mode_count = 0;\n+\tuint32_t start_offset = 0;\n+\tunsigned int i;\n+\tuint64_t value;\n+\tvoid *rsp;\n+\tint rc;\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\treturn 0;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = CNXK_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_hws_xstats;\n+\t\trc = roc_sso_hws_stats_get(&dev->sso, queue_port_id,\n+\t\t\t\t\t &hws_stats);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\t\trsp = &hws_stats;\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = CNXK_SSO_NUM_GRP_XSTATS;\n+\t\tstart_offset = CNXK_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_hwgrp_xstats;\n+\n+\t\trc = roc_sso_hwgrp_stats_get(&dev->sso, queue_port_id,\n+\t\t\t\t\t &hwgrp_stats);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\t\trsp = &hwgrp_stats;\n+\t\tbreak;\n+\tdefault:\n+\t\tplt_err(\"Invalid mode received\");\n+\t\tgoto invalid_value;\n+\t};\n+\n+\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n+\t\txstat = &xstats[ids[i] - start_offset];\n+\t\tvalue = *(uint64_t *)((char *)rsp + xstat->offset);\n+\t\tvalue = (value >> xstat->shift) & xstat->mask;\n+\n+\t\txstat->reset_snap[queue_port_id] = value;\n+\t}\n+\treturn i;\n+invalid_value:\n+\treturn -EINVAL;\n+}\n+\n+int\n+cnxk_sso_xstats_get_names(const struct rte_eventdev *event_dev,\n+\t\t\t enum rte_event_dev_xstats_mode mode,\n+\t\t\t uint8_t queue_port_id,\n+\t\t\t struct rte_event_dev_xstats_name *xstats_names,\n+\t\t\t unsigned int *ids, unsigned int size)\n+{\n+\tstruct rte_event_dev_xstats_name xstats_names_copy[CNXK_SSO_NUM_XSTATS];\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tuint32_t xstats_mode_count = 0;\n+\tuint32_t start_offset = 0;\n+\tunsigned int xidx = 0;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < CNXK_SSO_NUM_HWS_XSTATS; i++) {\n+\t\tsnprintf(xstats_names_copy[i].name,\n+\t\t\t sizeof(xstats_names_copy[i].name), \"%s\",\n+\t\t\t sso_hws_xstats[i].name);\n+\t}\n+\n+\tfor (; i < CNXK_SSO_NUM_XSTATS; i++) {\n+\t\tsnprintf(xstats_names_copy[i].name,\n+\t\t\t sizeof(xstats_names_copy[i].name), \"%s\",\n+\t\t\t sso_hwgrp_xstats[i - CNXK_SSO_NUM_HWS_XSTATS].name);\n+\t}\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n+\t\t\tbreak;\n+\t\txstats_mode_count = CNXK_SSO_NUM_HWS_XSTATS;\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n+\t\t\tbreak;\n+\t\txstats_mode_count = CNXK_SSO_NUM_GRP_XSTATS;\n+\t\tstart_offset = CNXK_SSO_NUM_HWS_XSTATS;\n+\t\tbreak;\n+\tdefault:\n+\t\tplt_err(\"Invalid mode received\");\n+\t\treturn -EINVAL;\n+\t};\n+\n+\tif (xstats_mode_count > size || !ids || !xstats_names)\n+\t\treturn xstats_mode_count;\n+\n+\tfor (i = 0; i < xstats_mode_count; i++) {\n+\t\txidx = i + start_offset;\n+\t\tstrncpy(xstats_names[i].name, xstats_names_copy[xidx].name,\n+\t\t\tsizeof(xstats_names[i].name));\n+\t\tids[i] = xidx;\n+\t}\n+\n+\treturn i;\n+}\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex e37ea3478..5b215b73f 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -13,7 +13,8 @@ sources = files('cn10k_worker.c',\n 'cn9k_worker.c',\n 'cn9k_eventdev.c',\n 'cnxk_eventdev.c',\n- 'cnxk_eventdev_selftest.c'\n+ 'cnxk_eventdev_selftest.c',\n+ 'cnxk_eventdev_stats.c',\n )\n \n deps += ['bus_pci', 'common_cnxk']\n", "prefixes": [ "v4", "20/34" ] }