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GET /api/patches/92649/?format=api
{ "id": 92649, "url": "http://patches.dpdk.org/api/patches/92649/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-12-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-12-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-12-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:14", "name": "[v4,11/34] event/cnxk: add port config functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4c5372fe4b5c19942fe8a833452bb0ab10789fc0", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-12-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92649/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92649/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B69D3A0562;\n\tMon, 3 May 2021 17:24:09 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 81B8141155;\n\tMon, 3 May 2021 17:23:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id E7FC541155\n for <dev@dpdk.org>; Mon, 3 May 2021 17:23:25 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FAqET032464 for <dev@dpdk.org>; Mon, 3 May 2021 08:23:25 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 38agtfgv1g-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 03 May 2021 08:23:25 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:23:23 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:23:23 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id C9E3E3F703F;\n Mon, 3 May 2021 08:23:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=0CvCilzLAo6P/a+yQnAWloq4vPjOzaMKIvX0KAUIpbs=;\n b=bAGPm1vmBjvAmlma4/uGSiBQR6Mo+a5+dn8D5TweZMtzHuqq51dfF9s2UI/NHIYac9z7\n HwkpY1pqd5J54X5udBpEwGMVpJQ7v+2LRTvwYdHKv/F88IU2QG7W7ZUJvtAiEP2pzC9j\n D7IcKwrxkM4p9u4Gd5+JRtHw4uJQ0QCs3EnEbOK7er86RJD1yfy7Zks4JwL1Qqwv0Djf\n X9MOF0ircGbp9ZQsVngeypDxPl99pHoeWoWgOic+nlLQyhHfKrwhjMCXMdT7+XEYAc11\n 35MeZ1z9exiscUg7TYbEOmiP3xUBfYZkmhyrmG4XeoY/NPrCvHObmv5JhZpA2E9aSJTn 0w==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:14 +0530", "Message-ID": "<20210503152238.2437-12-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "CkPK0g3FSU2B4koi5Mu_geZQ-K2TLAWy", "X-Proofpoint-ORIG-GUID": "CkPK0g3FSU2B4koi5Mu_geZQ-K2TLAWy", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 11/34] event/cnxk: add port config functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nAdd SSO HWS a.k.a event port setup and release functions.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 121 +++++++++++++++++++++++\n drivers/event/cnxk/cn9k_eventdev.c | 147 ++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.c | 65 ++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h | 91 +++++++++++++++++\n 4 files changed, 424 insertions(+)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 0b39c6c09..fcdc1cf84 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -4,6 +4,91 @@\n \n #include \"cnxk_eventdev.h\"\n \n+static void\n+cn10k_init_hws_ops(struct cn10k_sso_hws *ws, uintptr_t base)\n+{\n+\tws->tag_wqe_op = base + SSOW_LF_GWS_WQE0;\n+\tws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0;\n+\tws->updt_wqe_op = base + SSOW_LF_GWS_OP_UPD_WQP_GRP1;\n+\tws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;\n+\tws->swtag_untag_op = base + SSOW_LF_GWS_OP_SWTAG_UNTAG;\n+\tws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH;\n+\tws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;\n+}\n+\n+static uint32_t\n+cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)\n+{\n+\tuint32_t wdata = BIT(16) | 1;\n+\n+\tswitch (dev->gw_mode) {\n+\tcase CN10K_GW_MODE_NONE:\n+\tdefault:\n+\t\tbreak;\n+\tcase CN10K_GW_MODE_PREF:\n+\t\twdata |= BIT(19);\n+\t\tbreak;\n+\tcase CN10K_GW_MODE_PREF_WFE:\n+\t\twdata |= BIT(20) | BIT(19);\n+\t\tbreak;\n+\t}\n+\n+\treturn wdata;\n+}\n+\n+static void *\n+cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)\n+{\n+\tstruct cnxk_sso_evdev *dev = arg;\n+\tstruct cn10k_sso_hws *ws;\n+\n+\t/* Allocate event port memory */\n+\tws = rte_zmalloc(\"cn10k_ws\",\n+\t\t\t sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,\n+\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (ws == NULL) {\n+\t\tplt_err(\"Failed to alloc memory for port=%d\", port_id);\n+\t\treturn NULL;\n+\t}\n+\n+\t/* First cache line is reserved for cookie */\n+\tws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);\n+\tws->base = roc_sso_hws_base_get(&dev->sso, port_id);\n+\tcn10k_init_hws_ops(ws, ws->base);\n+\tws->hws_id = port_id;\n+\tws->swtag_req = 0;\n+\tws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);\n+\tws->lmt_base = dev->sso.lmt_base;\n+\n+\treturn ws;\n+}\n+\n+static void\n+cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)\n+{\n+\tstruct cnxk_sso_evdev *dev = arg;\n+\tstruct cn10k_sso_hws *ws = hws;\n+\tuint64_t val;\n+\n+\trte_memcpy(ws->grps_base, grps_base,\n+\t\t sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);\n+\tws->fc_mem = dev->fc_mem;\n+\tws->xaq_lmt = dev->xaq_lmt;\n+\n+\t/* Set get_work timeout for HWS */\n+\tval = NSEC2USEC(dev->deq_tmo_ns) - 1;\n+\tplt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);\n+}\n+\n+static void\n+cn10k_sso_hws_release(void *arg, void *hws)\n+{\n+\tstruct cn10k_sso_hws *ws = hws;\n+\n+\tRTE_SET_USED(arg);\n+\tmemset(ws, 0, sizeof(*ws));\n+}\n+\n static void\n cn10k_sso_set_rsrc(void *arg)\n {\n@@ -59,12 +144,46 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)\n \tif (rc < 0)\n \t\tgoto cnxk_rsrc_fini;\n \n+\trc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,\n+\t\t\t\t cn10k_sso_hws_setup);\n+\tif (rc < 0)\n+\t\tgoto cnxk_rsrc_fini;\n+\n \treturn 0;\n cnxk_rsrc_fini:\n \troc_sso_rsrc_fini(&dev->sso);\n+\tdev->nb_event_ports = 0;\n \treturn rc;\n }\n \n+static int\n+cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t const struct rte_event_port_conf *port_conf)\n+{\n+\n+\tRTE_SET_USED(port_conf);\n+\treturn cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);\n+}\n+\n+static void\n+cn10k_sso_port_release(void *port)\n+{\n+\tstruct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);\n+\tstruct cnxk_sso_evdev *dev;\n+\n+\tif (port == NULL)\n+\t\treturn;\n+\n+\tdev = cnxk_sso_pmd_priv(gws_cookie->event_dev);\n+\tif (!gws_cookie->configured)\n+\t\tgoto free;\n+\n+\tcn10k_sso_hws_release(dev, port);\n+\tmemset(gws_cookie, 0, sizeof(*gws_cookie));\n+free:\n+\trte_free(gws_cookie);\n+}\n+\n static struct rte_eventdev_ops cn10k_sso_dev_ops = {\n \t.dev_infos_get = cn10k_sso_info_get,\n \t.dev_configure = cn10k_sso_dev_configure,\n@@ -72,6 +191,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = {\n \t.queue_setup = cnxk_sso_queue_setup,\n \t.queue_release = cnxk_sso_queue_release,\n \t.port_def_conf = cnxk_sso_port_def_conf,\n+\t.port_setup = cn10k_sso_port_setup,\n+\t.port_release = cn10k_sso_port_release,\n };\n \n static int\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex ab165c850..b8c74633b 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -7,6 +7,63 @@\n #define CN9K_DUAL_WS_NB_WS\t 2\n #define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)\n \n+static void\n+cn9k_init_hws_ops(struct cn9k_sso_hws_state *ws, uintptr_t base)\n+{\n+\tws->tag_op = base + SSOW_LF_GWS_TAG;\n+\tws->wqp_op = base + SSOW_LF_GWS_WQP;\n+\tws->getwrk_op = base + SSOW_LF_GWS_OP_GET_WORK0;\n+\tws->swtag_flush_op = base + SSOW_LF_GWS_OP_SWTAG_FLUSH;\n+\tws->swtag_norm_op = base + SSOW_LF_GWS_OP_SWTAG_NORM;\n+\tws->swtag_desched_op = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;\n+}\n+\n+static void\n+cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)\n+{\n+\tstruct cnxk_sso_evdev *dev = arg;\n+\tstruct cn9k_sso_hws_dual *dws;\n+\tstruct cn9k_sso_hws *ws;\n+\tuint64_t val;\n+\n+\t/* Set get_work tmo for HWS */\n+\tval = NSEC2USEC(dev->deq_tmo_ns) - 1;\n+\tif (dev->dual_ws) {\n+\t\tdws = hws;\n+\t\trte_memcpy(dws->grps_base, grps_base,\n+\t\t\t sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);\n+\t\tdws->fc_mem = dev->fc_mem;\n+\t\tdws->xaq_lmt = dev->xaq_lmt;\n+\n+\t\tplt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);\n+\t\tplt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM);\n+\t} else {\n+\t\tws = hws;\n+\t\trte_memcpy(ws->grps_base, grps_base,\n+\t\t\t sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);\n+\t\tws->fc_mem = dev->fc_mem;\n+\t\tws->xaq_lmt = dev->xaq_lmt;\n+\n+\t\tplt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);\n+\t}\n+}\n+\n+static void\n+cn9k_sso_hws_release(void *arg, void *hws)\n+{\n+\tstruct cnxk_sso_evdev *dev = arg;\n+\tstruct cn9k_sso_hws_dual *dws;\n+\tstruct cn9k_sso_hws *ws;\n+\n+\tif (dev->dual_ws) {\n+\t\tdws = hws;\n+\t\tmemset(dws, 0, sizeof(*dws));\n+\t} else {\n+\t\tws = hws;\n+\t\tmemset(ws, 0, sizeof(*ws));\n+\t}\n+}\n+\n static void\n cn9k_sso_set_rsrc(void *arg)\n {\n@@ -33,6 +90,60 @@ cn9k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)\n \treturn roc_sso_rsrc_init(&dev->sso, hws, hwgrp);\n }\n \n+static void *\n+cn9k_sso_init_hws_mem(void *arg, uint8_t port_id)\n+{\n+\tstruct cnxk_sso_evdev *dev = arg;\n+\tstruct cn9k_sso_hws_dual *dws;\n+\tstruct cn9k_sso_hws *ws;\n+\tvoid *data;\n+\n+\tif (dev->dual_ws) {\n+\t\tdws = rte_zmalloc(\"cn9k_dual_ws\",\n+\t\t\t\t sizeof(struct cn9k_sso_hws_dual) +\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\t\tif (dws == NULL) {\n+\t\t\tplt_err(\"Failed to alloc memory for port=%d\", port_id);\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t\tdws = RTE_PTR_ADD(dws, sizeof(struct cnxk_sso_hws_cookie));\n+\t\tdws->base[0] = roc_sso_hws_base_get(\n+\t\t\t&dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 0));\n+\t\tdws->base[1] = roc_sso_hws_base_get(\n+\t\t\t&dev->sso, CN9K_DUAL_WS_PAIR_ID(port_id, 1));\n+\t\tcn9k_init_hws_ops(&dws->ws_state[0], dws->base[0]);\n+\t\tcn9k_init_hws_ops(&dws->ws_state[1], dws->base[1]);\n+\t\tdws->hws_id = port_id;\n+\t\tdws->swtag_req = 0;\n+\t\tdws->vws = 0;\n+\n+\t\tdata = dws;\n+\t} else {\n+\t\t/* Allocate event port memory */\n+\t\tws = rte_zmalloc(\"cn9k_ws\",\n+\t\t\t\t sizeof(struct cn9k_sso_hws) +\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\t\tif (ws == NULL) {\n+\t\t\tplt_err(\"Failed to alloc memory for port=%d\", port_id);\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t\t/* First cache line is reserved for cookie */\n+\t\tws = RTE_PTR_ADD(ws, sizeof(struct cnxk_sso_hws_cookie));\n+\t\tws->base = roc_sso_hws_base_get(&dev->sso, port_id);\n+\t\tcn9k_init_hws_ops((struct cn9k_sso_hws_state *)ws, ws->base);\n+\t\tws->hws_id = port_id;\n+\t\tws->swtag_req = 0;\n+\n+\t\tdata = ws;\n+\t}\n+\n+\treturn data;\n+}\n+\n static void\n cn9k_sso_info_get(struct rte_eventdev *event_dev,\n \t\t struct rte_event_dev_info *dev_info)\n@@ -67,12 +178,46 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)\n \tif (rc < 0)\n \t\tgoto cnxk_rsrc_fini;\n \n+\trc = cnxk_setup_event_ports(event_dev, cn9k_sso_init_hws_mem,\n+\t\t\t\t cn9k_sso_hws_setup);\n+\tif (rc < 0)\n+\t\tgoto cnxk_rsrc_fini;\n+\n \treturn 0;\n cnxk_rsrc_fini:\n \troc_sso_rsrc_fini(&dev->sso);\n+\tdev->nb_event_ports = 0;\n \treturn rc;\n }\n \n+static int\n+cn9k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t const struct rte_event_port_conf *port_conf)\n+{\n+\n+\tRTE_SET_USED(port_conf);\n+\treturn cnxk_sso_port_setup(event_dev, port_id, cn9k_sso_hws_setup);\n+}\n+\n+static void\n+cn9k_sso_port_release(void *port)\n+{\n+\tstruct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);\n+\tstruct cnxk_sso_evdev *dev;\n+\n+\tif (port == NULL)\n+\t\treturn;\n+\n+\tdev = cnxk_sso_pmd_priv(gws_cookie->event_dev);\n+\tif (!gws_cookie->configured)\n+\t\tgoto free;\n+\n+\tcn9k_sso_hws_release(dev, port);\n+\tmemset(gws_cookie, 0, sizeof(*gws_cookie));\n+free:\n+\trte_free(gws_cookie);\n+}\n+\n static struct rte_eventdev_ops cn9k_sso_dev_ops = {\n \t.dev_infos_get = cn9k_sso_info_get,\n \t.dev_configure = cn9k_sso_dev_configure,\n@@ -80,6 +225,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = {\n \t.queue_setup = cnxk_sso_queue_setup,\n \t.queue_release = cnxk_sso_queue_release,\n \t.port_def_conf = cnxk_sso_port_def_conf,\n+\t.port_setup = cn9k_sso_port_setup,\n+\t.port_release = cn9k_sso_port_release,\n };\n \n static int\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex e93aaccd8..daf24d84a 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -125,6 +125,42 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)\n \treturn rc;\n }\n \n+int\n+cnxk_setup_event_ports(const struct rte_eventdev *event_dev,\n+\t\t cnxk_sso_init_hws_mem_t init_hws_fn,\n+\t\t cnxk_sso_hws_setup_t setup_hws_fn)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tint i;\n+\n+\tfor (i = 0; i < dev->nb_event_ports; i++) {\n+\t\tstruct cnxk_sso_hws_cookie *ws_cookie;\n+\t\tvoid *ws;\n+\n+\t\t/* Free memory prior to re-allocation if needed */\n+\t\tif (event_dev->data->ports[i] != NULL)\n+\t\t\tws = event_dev->data->ports[i];\n+\t\telse\n+\t\t\tws = init_hws_fn(dev, i);\n+\t\tif (ws == NULL)\n+\t\t\tgoto hws_fini;\n+\t\tws_cookie = cnxk_sso_hws_get_cookie(ws);\n+\t\tws_cookie->event_dev = event_dev;\n+\t\tws_cookie->configured = 1;\n+\t\tevent_dev->data->ports[i] = ws;\n+\t\tcnxk_sso_port_setup((struct rte_eventdev *)(uintptr_t)event_dev,\n+\t\t\t\t i, setup_hws_fn);\n+\t}\n+\n+\treturn 0;\n+hws_fini:\n+\tfor (i = i - 1; i >= 0; i--) {\n+\t\tevent_dev->data->ports[i] = NULL;\n+\t\trte_free(cnxk_sso_hws_get_cookie(event_dev->data->ports[i]));\n+\t}\n+\treturn -ENOMEM;\n+}\n+\n int\n cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)\n {\n@@ -225,6 +261,35 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n \tport_conf->enqueue_depth = 1;\n }\n \n+int\n+cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t cnxk_sso_hws_setup_t hws_setup_fn)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tuintptr_t grps_base[CNXK_SSO_MAX_HWGRP] = {0};\n+\tuint16_t q;\n+\n+\tplt_sso_dbg(\"Port=%d\", port_id);\n+\tif (event_dev->data->ports[port_id] == NULL) {\n+\t\tplt_err(\"Invalid port Id %d\", port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (q = 0; q < dev->nb_event_queues; q++) {\n+\t\tgrps_base[q] = roc_sso_hwgrp_base_get(&dev->sso, q);\n+\t\tif (grps_base[q] == 0) {\n+\t\t\tplt_err(\"Failed to get grp[%d] base addr\", q);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\thws_setup_fn(dev, event_dev->data->ports[port_id], grps_base);\n+\tplt_sso_dbg(\"Port=%d ws=%p\", port_id, event_dev->data->ports[port_id]);\n+\trte_mb();\n+\n+\treturn 0;\n+}\n+\n static void\n parse_queue_param(char *value, void *opaque)\n {\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex b96a6a908..79eab1829 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -17,13 +17,23 @@\n #define CNXK_SSO_XAE_CNT \"xae_cnt\"\n #define CNXK_SSO_GGRP_QOS \"qos\"\n \n+#define NSEC2USEC(__ns) ((__ns) / 1E3)\n #define USEC2NSEC(__us) ((__us)*1E3)\n \n+#define CNXK_SSO_MAX_HWGRP (RTE_EVENT_MAX_QUEUES_PER_DEV + 1)\n #define CNXK_SSO_FC_NAME \"cnxk_evdev_xaq_fc\"\n #define CNXK_SSO_MZ_NAME \"cnxk_evdev_mz\"\n #define CNXK_SSO_XAQ_CACHE_CNT (0x7)\n #define CNXK_SSO_XAQ_SLACK (8)\n \n+#define CN10K_GW_MODE_NONE 0\n+#define CN10K_GW_MODE_PREF 1\n+#define CN10K_GW_MODE_PREF_WFE 2\n+\n+typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);\n+typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);\n+typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);\n+\n struct cnxk_sso_qos {\n \tuint16_t queue;\n \tuint8_t xaq_prcnt;\n@@ -53,6 +63,76 @@ struct cnxk_sso_evdev {\n \tstruct cnxk_sso_qos *qos_parse_data;\n \t/* CN9K */\n \tuint8_t dual_ws;\n+\t/* CN10K */\n+\tuint8_t gw_mode;\n+} __rte_cache_aligned;\n+\n+/* CN10K HWS ops */\n+#define CN10K_SSO_HWS_OPS \\\n+\tuintptr_t swtag_desched_op; \\\n+\tuintptr_t swtag_flush_op; \\\n+\tuintptr_t swtag_untag_op; \\\n+\tuintptr_t swtag_norm_op; \\\n+\tuintptr_t updt_wqe_op; \\\n+\tuintptr_t tag_wqe_op; \\\n+\tuintptr_t getwrk_op\n+\n+struct cn10k_sso_hws {\n+\t/* Get Work Fastpath data */\n+\tCN10K_SSO_HWS_OPS;\n+\tuint32_t gw_wdata;\n+\tuint8_t swtag_req;\n+\tuint8_t hws_id;\n+\t/* Add Work Fastpath data */\n+\tuint64_t xaq_lmt __rte_cache_aligned;\n+\tuint64_t *fc_mem;\n+\tuintptr_t grps_base[CNXK_SSO_MAX_HWGRP];\n+\tuint64_t base;\n+\tuintptr_t lmt_base;\n+} __rte_cache_aligned;\n+\n+/* CN9K HWS ops */\n+#define CN9K_SSO_HWS_OPS \\\n+\tuintptr_t swtag_desched_op; \\\n+\tuintptr_t swtag_flush_op; \\\n+\tuintptr_t swtag_norm_op; \\\n+\tuintptr_t getwrk_op; \\\n+\tuintptr_t tag_op; \\\n+\tuintptr_t wqp_op\n+\n+/* Event port a.k.a GWS */\n+struct cn9k_sso_hws {\n+\t/* Get Work Fastpath data */\n+\tCN9K_SSO_HWS_OPS;\n+\tuint8_t swtag_req;\n+\tuint8_t hws_id;\n+\t/* Add Work Fastpath data */\n+\tuint64_t xaq_lmt __rte_cache_aligned;\n+\tuint64_t *fc_mem;\n+\tuintptr_t grps_base[CNXK_SSO_MAX_HWGRP];\n+\tuint64_t base;\n+} __rte_cache_aligned;\n+\n+struct cn9k_sso_hws_state {\n+\tCN9K_SSO_HWS_OPS;\n+};\n+\n+struct cn9k_sso_hws_dual {\n+\t/* Get Work Fastpath data */\n+\tstruct cn9k_sso_hws_state ws_state[2]; /* Ping and Pong */\n+\tuint8_t swtag_req;\n+\tuint8_t vws; /* Ping pong bit */\n+\tuint8_t hws_id;\n+\t/* Add Work Fastpath data */\n+\tuint64_t xaq_lmt __rte_cache_aligned;\n+\tuint64_t *fc_mem;\n+\tuintptr_t grps_base[CNXK_SSO_MAX_HWGRP];\n+\tuint64_t base[2];\n+} __rte_cache_aligned;\n+\n+struct cnxk_sso_hws_cookie {\n+\tconst struct rte_eventdev *event_dev;\n+\tbool configured;\n } __rte_cache_aligned;\n \n static inline int\n@@ -70,6 +150,12 @@ cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)\n \treturn event_dev->data->dev_private;\n }\n \n+static inline struct cnxk_sso_hws_cookie *\n+cnxk_sso_hws_get_cookie(void *ws)\n+{\n+\treturn RTE_PTR_SUB(ws, sizeof(struct cnxk_sso_hws_cookie));\n+}\n+\n /* Configuration functions */\n int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);\n \n@@ -80,6 +166,9 @@ int cnxk_sso_remove(struct rte_pci_device *pci_dev);\n void cnxk_sso_info_get(struct cnxk_sso_evdev *dev,\n \t\t struct rte_event_dev_info *dev_info);\n int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev);\n+int cnxk_setup_event_ports(const struct rte_eventdev *event_dev,\n+\t\t\t cnxk_sso_init_hws_mem_t init_hws_mem,\n+\t\t\t cnxk_sso_hws_setup_t hws_setup);\n void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,\n \t\t\t struct rte_event_queue_conf *queue_conf);\n int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,\n@@ -87,5 +176,7 @@ int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,\n void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id);\n void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n \t\t\t struct rte_event_port_conf *port_conf);\n+int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t\tcnxk_sso_hws_setup_t hws_setup_fn);\n \n #endif /* __CNXK_EVENTDEV_H__ */\n", "prefixes": [ "v4", "11/34" ] }