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GET /api/patches/92593/?format=api
{ "id": 92593, "url": "http://patches.dpdk.org/api/patches/92593/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1619895841-7467-6-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1619895841-7467-6-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1619895841-7467-6-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-05-01T19:03:40", "name": "[v5,05/26] event/dlb2: add v2.5 get resources", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1fd55f60825022edc104a9d231b689462bba5fb1", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1619895841-7467-6-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16784, "url": "http://patches.dpdk.org/api/series/16784/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16784", "date": "2021-05-01T19:03:37", "name": "Add DLB v2.5", "version": 5, "mbox": "http://patches.dpdk.org/series/16784/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92593/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92593/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1E45EA0546;\n\tSat, 1 May 2021 21:05:59 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 565C541152;\n\tSat, 1 May 2021 21:05:39 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id B353C4013F\n for <dev@dpdk.org>; Sat, 1 May 2021 21:05:34 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 May 2021 12:05:32 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga002.fm.intel.com with ESMTP; 01 May 2021 12:05:31 -0700" ], "IronPort-SDR": [ "\n 3StIBycZBpH4VacjJBl2PKrCiltI1IEQTKyPXuRvapp/ig6zKO2i62cnC9MC5AYh3+DyOhtb79\n NiSZvdwNqytA==", "\n Io0WoiCyiEkxlp4Sk2doMUYc93QF1leAhMu7A0VcqHqpkSISZQKt8kL08ME3EC/JFJBftDgcop\n ZpRG97BDA/aA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9971\"; a=\"282865180\"", "E=Sophos;i=\"5.82,266,1613462400\"; d=\"scan'208\";a=\"282865180\"", "E=Sophos;i=\"5.82,266,1613462400\"; d=\"scan'208\";a=\"460767012\"" ], "X-ExtLoop1": "1", "From": "\"McDaniel, Timothy\" <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, harry.van.haaren@intel.com,\n jerinj@marvell.com, thomas@monjalon.net,\n Timothy McDaniel <timothy.mcdaniel@intel.com>", "Date": "Sat, 1 May 2021 14:03:40 -0500", "Message-Id": "<1619895841-7467-6-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1619895841-7467-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1619895841-7467-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 05/26] event/dlb2: add v2.5 get resources", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Timothy McDaniel <timothy.mcdaniel@intel.com>\n\nDLB v2.5 uses a new credit scheme, where directed and load balanced\ncredits are unified, instead of having separate directed and load\nbalanced credit pools.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 20 ++++--\n drivers/event/dlb2/dlb2_user.h | 14 +++-\n drivers/event/dlb2/pf/base/dlb2_resource.c | 48 --------------\n .../event/dlb2/pf/base/dlb2_resource_new.c | 66 +++++++++++++++++++\n 4 files changed, 92 insertions(+), 56 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 7f5b9141b..0048f6a1b 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -132,17 +132,25 @@ dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)\n \tevdev_dlb2_default_info.max_event_ports =\n \t\tdlb2->hw_rsrc_query_results.num_ldb_ports;\n \n-\tevdev_dlb2_default_info.max_num_events =\n-\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n-\n+\tif (dlb2->version == DLB2_HW_V2_5) {\n+\t\tevdev_dlb2_default_info.max_num_events =\n+\t\t\tdlb2->hw_rsrc_query_results.num_credits;\n+\t} else {\n+\t\tevdev_dlb2_default_info.max_num_events =\n+\t\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n+\t}\n \t/* Save off values used when creating the scheduling domain. */\n \n \thandle->info.num_sched_domains =\n \t\tdlb2->hw_rsrc_query_results.num_sched_domains;\n \n-\thandle->info.hw_rsrc_max.nb_events_limit =\n-\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n-\n+\tif (dlb2->version == DLB2_HW_V2_5) {\n+\t\thandle->info.hw_rsrc_max.nb_events_limit =\n+\t\t\tdlb2->hw_rsrc_query_results.num_credits;\n+\t} else {\n+\t\thandle->info.hw_rsrc_max.nb_events_limit =\n+\t\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n+\t}\n \thandle->info.hw_rsrc_max.num_queues =\n \t\tdlb2->hw_rsrc_query_results.num_ldb_queues +\n \t\tdlb2->hw_rsrc_query_results.num_dir_ports;\ndiff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb2/dlb2_user.h\nindex f4bda7822..b7d125dec 100644\n--- a/drivers/event/dlb2/dlb2_user.h\n+++ b/drivers/event/dlb2/dlb2_user.h\n@@ -195,9 +195,12 @@ struct dlb2_create_sched_domain_args {\n *\tcontiguous range of history list entries.\n * - num_ldb_credits: Amount of available load-balanced QE storage.\n * - num_dir_credits: Amount of available directed QE storage.\n+ * - response.status: Detailed error code. In certain cases, such as if the\n+ *\tioctl request arg is invalid, the driver won't set status.\n */\n struct dlb2_get_num_resources_args {\n \t/* Output parameters */\n+\tstruct dlb2_cmd_response response;\n \t__u32 num_sched_domains;\n \t__u32 num_ldb_queues;\n \t__u32 num_ldb_ports;\n@@ -206,8 +209,15 @@ struct dlb2_get_num_resources_args {\n \t__u32 num_atomic_inflights;\n \t__u32 num_hist_list_entries;\n \t__u32 max_contiguous_hist_list_entries;\n-\t__u32 num_ldb_credits;\n-\t__u32 num_dir_credits;\n+\tunion {\n+\t\tstruct {\n+\t\t\t__u32 num_ldb_credits;\n+\t\t\t__u32 num_dir_credits;\n+\t\t};\n+\t\tstruct {\n+\t\t\t__u32 num_credits;\n+\t\t};\n+\t};\n };\n \n /*\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 7ba6521ef..eda983d85 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -58,54 +58,6 @@ void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n \tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n }\n \n-int dlb2_hw_get_num_resources(struct dlb2_hw *hw,\n-\t\t\t struct dlb2_get_num_resources_args *arg,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n-{\n-\tstruct dlb2_function_resources *rsrcs;\n-\tstruct dlb2_bitmap *map;\n-\tint i;\n-\n-\tif (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS)\n-\t\treturn -EINVAL;\n-\n-\tif (vdev_req)\n-\t\trsrcs = &hw->vdev[vdev_id];\n-\telse\n-\t\trsrcs = &hw->pf;\n-\n-\targ->num_sched_domains = rsrcs->num_avail_domains;\n-\n-\targ->num_ldb_queues = rsrcs->num_avail_ldb_queues;\n-\n-\targ->num_ldb_ports = 0;\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n-\t\targ->num_ldb_ports += rsrcs->num_avail_ldb_ports[i];\n-\n-\targ->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0];\n-\targ->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1];\n-\targ->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2];\n-\targ->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3];\n-\n-\targ->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;\n-\n-\targ->num_atomic_inflights = rsrcs->num_avail_aqed_entries;\n-\n-\tmap = rsrcs->avail_hist_list_entries;\n-\n-\targ->num_hist_list_entries = dlb2_bitmap_count(map);\n-\n-\targ->max_contiguous_hist_list_entries =\n-\t\tdlb2_bitmap_longest_set_range(map);\n-\n-\targ->num_ldb_credits = rsrcs->num_avail_qed_entries;\n-\n-\targ->num_dir_credits = rsrcs->num_avail_dqed_entries;\n-\n-\treturn 0;\n-}\n-\n void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n {\n \tunion dlb2_chp_cfg_chp_csr_ctrl r0;\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 175b0799e..14b97dbf9 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -257,3 +257,69 @@ void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw, enum dlb2_hw_ver ver)\n \tDLB2_CSR_WR(hw, DLB2_CM_CFG_PM_PMCSR_DISABLE(ver), pmcsr_dis);\n }\n \n+/**\n+ * dlb2_hw_get_num_resources() - query the PCI function's available resources\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @arg: pointer to resource counts.\n+ * @vdev_req: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_req is true, this contains the vdev's ID.\n+ *\n+ * This function returns the number of available resources for the PF or for a\n+ * VF.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, -EINVAL if vdev_req is true and vdev_id is\n+ * invalid.\n+ */\n+int dlb2_hw_get_num_resources(struct dlb2_hw *hw,\n+\t\t\t struct dlb2_get_num_resources_args *arg,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_function_resources *rsrcs;\n+\tstruct dlb2_bitmap *map;\n+\tint i;\n+\n+\tif (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS)\n+\t\treturn -EINVAL;\n+\n+\tif (vdev_req)\n+\t\trsrcs = &hw->vdev[vdev_id];\n+\telse\n+\t\trsrcs = &hw->pf;\n+\n+\targ->num_sched_domains = rsrcs->num_avail_domains;\n+\n+\targ->num_ldb_queues = rsrcs->num_avail_ldb_queues;\n+\n+\targ->num_ldb_ports = 0;\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\targ->num_ldb_ports += rsrcs->num_avail_ldb_ports[i];\n+\n+\targ->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0];\n+\targ->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1];\n+\targ->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2];\n+\targ->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3];\n+\n+\targ->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;\n+\n+\targ->num_atomic_inflights = rsrcs->num_avail_aqed_entries;\n+\n+\tmap = rsrcs->avail_hist_list_entries;\n+\n+\targ->num_hist_list_entries = dlb2_bitmap_count(map);\n+\n+\targ->max_contiguous_hist_list_entries =\n+\t\tdlb2_bitmap_longest_set_range(map);\n+\n+\tif (hw->ver == DLB2_HW_V2) {\n+\t\targ->num_ldb_credits = rsrcs->num_avail_qed_entries;\n+\t\targ->num_dir_credits = rsrcs->num_avail_dqed_entries;\n+\t} else {\n+\t\targ->num_credits = rsrcs->num_avail_entries;\n+\t}\n+\treturn 0;\n+}\n", "prefixes": [ "v5", "05/26" ] }