Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92462/?format=api
{ "id": 92462, "url": "http://patches.dpdk.org/api/patches/92462/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1619764130-57208-7-git-send-email-humin29@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1619764130-57208-7-git-send-email-humin29@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1619764130-57208-7-git-send-email-humin29@huawei.com", "date": "2021-04-30T06:28:50", "name": "[v3,6/6] net/hns3: fix vector Rx burst can't exceed 32", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ec546e32543b541672ec33d2d884d8584c0ad1d5", "submitter": { "id": 1944, "url": "http://patches.dpdk.org/api/people/1944/?format=api", "name": "humin (Q)", "email": "humin29@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1619764130-57208-7-git-send-email-humin29@huawei.com/mbox/", "series": [ { "id": 16768, "url": "http://patches.dpdk.org/api/series/16768/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16768", "date": "2021-04-30T06:28:46", "name": "optimization and bugfix for hns3 PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/16768/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92462/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92462/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1C5BCA0546;\n\tFri, 30 Apr 2021 08:29:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1B1F44113F;\n\tFri, 30 Apr 2021 08:28:57 +0200 (CEST)", "from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35])\n by mails.dpdk.org (Postfix) with ESMTP id 36FA441133\n for <dev@dpdk.org>; Fri, 30 Apr 2021 08:28:51 +0200 (CEST)", "from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58])\n by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4FWj7H4bNRzBskG\n for <dev@dpdk.org>; Fri, 30 Apr 2021 14:26:19 +0800 (CST)", "from localhost.localdomain (10.69.192.56) by\n DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id\n 14.3.498.0; Fri, 30 Apr 2021 14:28:45 +0800" ], "From": "\"Min Hu (Connor)\" <humin29@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>", "Date": "Fri, 30 Apr 2021 14:28:50 +0800", "Message-ID": "<1619764130-57208-7-git-send-email-humin29@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1619764130-57208-1-git-send-email-humin29@huawei.com>", "References": "<1619408092-54050-1-git-send-email-humin29@huawei.com>\n <1619764130-57208-1-git-send-email-humin29@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.69.192.56]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH v3 6/6] net/hns3: fix vector Rx burst can't\n exceed 32", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Chengwen Feng <fengchengwen@huawei.com>\n\nCurrently, driver uses the macro HNS3_DEFAULT_RX_BURST whose value is\n32 to limit the vector Rx burst size, as a result, the burst size\ncan't exceed 32.\n\nThis patch fixes this problem by support big burst size.\nAlso adjust HNS3_DEFAULT_RX_BURST to 64 as it performs better than 32.\n\nFixes: a3d4f4d291d7 (\"net/hns3: support NEON Rx\")\nFixes: 952ebacce4f2 (\"net/hns3: support SVE Rx\")\nCc: stable@dpdk.org\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\n---\n drivers/net/hns3/hns3_rxtx.h | 2 +-\n drivers/net/hns3/hns3_rxtx_vec.c | 36 ++++++++++++++++++++++++++++--------\n drivers/net/hns3/hns3_rxtx_vec.h | 3 +++\n drivers/net/hns3/hns3_rxtx_vec_sve.c | 32 ++++++++++++++++++++++++++------\n 4 files changed, 58 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h\nindex 1e2e994..ba24e00 100644\n--- a/drivers/net/hns3/hns3_rxtx.h\n+++ b/drivers/net/hns3/hns3_rxtx.h\n@@ -20,7 +20,7 @@\n #define HNS3_DEFAULT_TX_RS_THRESH\t32\n #define HNS3_TX_FAST_FREE_AHEAD\t\t64\n \n-#define HNS3_DEFAULT_RX_BURST\t\t32\n+#define HNS3_DEFAULT_RX_BURST\t\t64\n #if (HNS3_DEFAULT_RX_BURST > 64)\n #error \"PMD HNS3: HNS3_DEFAULT_RX_BURST must <= 64\\n\"\n #endif\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec.c b/drivers/net/hns3/hns3_rxtx_vec.c\nindex dc1e1ae..cc8b970 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec.c\n+++ b/drivers/net/hns3/hns3_rxtx_vec.c\n@@ -108,14 +108,13 @@ hns3_recv_pkts_vec(void *__restrict rx_queue,\n {\n \tstruct hns3_rx_queue *rxq = rx_queue;\n \tstruct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use];\n-\tuint64_t bd_err_mask; /* bit mask indicate whick pkts is error */\n+\tuint64_t pkt_err_mask; /* bit mask indicate whick pkts is error */\n \tuint16_t nb_rx;\n \n-\tnb_pkts = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);\n-\tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_DEFAULT_DESCS_PER_LOOP);\n-\n \trte_prefetch_non_temporal(rxdp);\n \n+\tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_DEFAULT_DESCS_PER_LOOP);\n+\n \tif (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)\n \t\thns3_rxq_rearm_mbuf(rxq);\n \n@@ -128,10 +127,31 @@ hns3_recv_pkts_vec(void *__restrict rx_queue,\n \trte_prefetch0(rxq->sw_ring[rxq->next_to_use + 2].mbuf);\n \trte_prefetch0(rxq->sw_ring[rxq->next_to_use + 3].mbuf);\n \n-\tbd_err_mask = 0;\n-\tnb_rx = hns3_recv_burst_vec(rxq, rx_pkts, nb_pkts, &bd_err_mask);\n-\tif (unlikely(bd_err_mask))\n-\t\tnb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, bd_err_mask);\n+\tif (likely(nb_pkts <= HNS3_DEFAULT_RX_BURST)) {\n+\t\tpkt_err_mask = 0;\n+\t\tnb_rx = hns3_recv_burst_vec(rxq, rx_pkts, nb_pkts,\n+\t\t\t\t\t &pkt_err_mask);\n+\t\tnb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, pkt_err_mask);\n+\t\treturn nb_rx;\n+\t}\n+\n+\tnb_rx = 0;\n+\twhile (nb_pkts > 0) {\n+\t\tuint16_t ret, n;\n+\n+\t\tn = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);\n+\t\tpkt_err_mask = 0;\n+\t\tret = hns3_recv_burst_vec(rxq, &rx_pkts[nb_rx], n,\n+\t\t\t\t\t &pkt_err_mask);\n+\t\tnb_pkts -= ret;\n+\t\tnb_rx += hns3_rx_reassemble_pkts(&rx_pkts[nb_rx], ret,\n+\t\t\t\t\t\t pkt_err_mask);\n+\t\tif (ret < n)\n+\t\t\tbreak;\n+\n+\t\tif (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)\n+\t\t\thns3_rxq_rearm_mbuf(rxq);\n+\t}\n \n \treturn nb_rx;\n }\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec.h b/drivers/net/hns3/hns3_rxtx_vec.h\nindex 2baf085..67c75e4 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec.h\n+++ b/drivers/net/hns3/hns3_rxtx_vec.h\n@@ -71,6 +71,9 @@ hns3_rx_reassemble_pkts(struct rte_mbuf **rx_pkts,\n \tuint16_t count, i;\n \tuint64_t mask;\n \n+\tif (likely(pkt_err_mask == 0))\n+\t\treturn nb_pkts;\n+\n \tcount = 0;\n \tfor (i = 0; i < nb_pkts; i++) {\n \t\tmask = ((uint64_t)1u) << i;\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c\nindex ef6c875..bf7f704 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec_sve.c\n+++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c\n@@ -292,12 +292,11 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue,\n {\n \tstruct hns3_rx_queue *rxq = rx_queue;\n \tstruct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use];\n-\tuint64_t bd_err_mask; /* bit mask indicate whick pkts is error */\n+\tuint64_t pkt_err_mask; /* bit mask indicate whick pkts is error */\n \tuint16_t nb_rx;\n \n \trte_prefetch_non_temporal(rxdp);\n \n-\tnb_pkts = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);\n \tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_SVE_DEFAULT_DESCS_PER_LOOP);\n \n \tif (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)\n@@ -309,10 +308,31 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue,\n \n \thns3_rx_prefetch_mbuf_sve(&rxq->sw_ring[rxq->next_to_use]);\n \n-\tbd_err_mask = 0;\n-\tnb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts, &bd_err_mask);\n-\tif (unlikely(bd_err_mask))\n-\t\tnb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, bd_err_mask);\n+\tif (likely(nb_pkts <= HNS3_DEFAULT_RX_BURST)) {\n+\t\tpkt_err_mask = 0;\n+\t\tnb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts,\n+\t\t\t\t\t\t&pkt_err_mask);\n+\t\tnb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, pkt_err_mask);\n+\t\treturn nb_rx;\n+\t}\n+\n+\tnb_rx = 0;\n+\twhile (nb_pkts > 0) {\n+\t\tuint16_t ret, n;\n+\n+\t\tn = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);\n+\t\tpkt_err_mask = 0;\n+\t\tret = hns3_recv_burst_vec_sve(rxq, &rx_pkts[nb_rx], n,\n+\t\t\t\t\t &pkt_err_mask);\n+\t\tnb_pkts -= ret;\n+\t\tnb_rx += hns3_rx_reassemble_pkts(&rx_pkts[nb_rx], ret,\n+\t\t\t\t\t\t pkt_err_mask);\n+\t\tif (ret < n)\n+\t\t\tbreak;\n+\n+\t\tif (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)\n+\t\t\thns3_rxq_rearm_mbuf_sve(rxq);\n+\t}\n \n \treturn nb_rx;\n }\n", "prefixes": [ "v3", "6/6" ] }