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GET /api/patches/92215/?format=api
{ "id": 92215, "url": "http://patches.dpdk.org/api/patches/92215/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-30-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210426174441.2302-30-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210426174441.2302-30-pbhagavatula@marvell.com", "date": "2021-04-26T17:44:36", "name": "[v2,29/33] event/cnxk: add timer arm timeout burst", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a00161f900da7292a433d8c2b8c40d1e50536f00", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-30-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16682, "url": "http://patches.dpdk.org/api/series/16682/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16682", "date": "2021-04-26T17:44:07", "name": "Marvell CNXK Event device Driver", "version": 2, "mbox": "http://patches.dpdk.org/series/16682/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92215/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92215/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3107AA0548;\n\tMon, 26 Apr 2021 19:48:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B55A24127F;\n\tMon, 26 Apr 2021 19:46:40 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 481874127C\n for <dev@dpdk.org>; Mon, 26 Apr 2021 19:46:38 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13QHis3K030120 for <dev@dpdk.org>; Mon, 26 Apr 2021 10:46:37 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 385tvvhdm7-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 26 Apr 2021 10:46:37 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 26 Apr 2021 10:46:35 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 26 Apr 2021 10:46:35 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 4D3595B6C96;\n Mon, 26 Apr 2021 10:46:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=9cvOfsN92kvA4zOaafGOXiB0v7eoP5PJu1CVuQZuVyE=;\n b=fnI7mlP1fW/2TdWD2vh8ijKYErBkRfmvBnJj50SOCbzJ3/NMXhoJapHhJvtBi/dzPMiy\n H9prvqffN1PHrEUsdSz2gz7wJEHmiva0xSKIC+jX2Pp6xxgcnIMT8XK1Nv0zW451qzUG\n wIWaY+T2f6cQcwElcG16nQtJl8ul3inIym6hPbmjhUMYGdhD4Ed2o3tUnDdQqmcJAMJj\n PQwTNMIEq3T7HuPi0a/N9yo/p37XLQUp/nyq4Me4cub/nLuW+n6+4wErR83IMyu5OZXp\n 3XKV9IudVbLkml9WiudYsN7YBpJTtEYcyP2dCHjextpFHzglpF7n3/uL4MD7vqkNIga5 3g==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 26 Apr 2021 23:14:36 +0530", "Message-ID": "<20210426174441.2302-30-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210426174441.2302-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>\n <20210426174441.2302-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ONCqZNzKRP2Qz7_usGku_SP_ybVjcPPV", "X-Proofpoint-ORIG-GUID": "ONCqZNzKRP2Qz7_usGku_SP_ybVjcPPV", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-26_09:2021-04-26,\n 2021-04-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 29/33] event/cnxk: add timer arm timeout burst", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd event timer arm timeout burst function.\nAll the timers requested to be armed have the same timeout.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/event/cnxk/cnxk_tim_evdev.c | 7 ++\n drivers/event/cnxk/cnxk_tim_evdev.h | 12 +++\n drivers/event/cnxk/cnxk_tim_worker.c | 53 ++++++++++\n drivers/event/cnxk/cnxk_tim_worker.h | 141 +++++++++++++++++++++++++++\n 4 files changed, 213 insertions(+)", "diff": "diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex a3be66f9a..e6f31b19f 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -88,7 +88,14 @@ cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)\n #undef FP\n \t};\n \n+\tconst rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2] = {\n+#define FP(_name, _f1, flags) [_f1] = cnxk_tim_arm_tmo_tick_burst_##_name,\n+\t\tTIM_ARM_TMO_FASTPATH_MODES\n+#undef FP\n+\t};\n+\n \tcnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag];\n+\tcnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb];\n }\n \n static void\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex 7cbcdb701..04ba3dc8c 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -217,6 +217,10 @@ cnxk_tim_cntfrq(void)\n \tFP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \\\n \tFP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP)\n \n+#define TIM_ARM_TMO_FASTPATH_MODES \\\n+\tFP(dfb, 0, CNXK_TIM_ENA_DFB) \\\n+\tFP(fb, 1, CNXK_TIM_ENA_FB)\n+\n #define FP(_name, _f2, _f1, flags) \\\n \tuint16_t cnxk_tim_arm_burst_##_name( \\\n \t\tconst struct rte_event_timer_adapter *adptr, \\\n@@ -224,6 +228,14 @@ cnxk_tim_cntfrq(void)\n TIM_ARM_FASTPATH_MODES\n #undef FP\n \n+#define FP(_name, _f1, flags) \\\n+\tuint16_t cnxk_tim_arm_tmo_tick_burst_##_name( \\\n+\t\tconst struct rte_event_timer_adapter *adptr, \\\n+\t\tstruct rte_event_timer **tim, const uint64_t timeout_tick, \\\n+\t\tconst uint16_t nb_timers);\n+TIM_ARM_TMO_FASTPATH_MODES\n+#undef FP\n+\n int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\t uint32_t *caps,\n \t\t const struct rte_event_timer_adapter_ops **ops);\ndiff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c\nindex eec39b9c2..2f1676ec1 100644\n--- a/drivers/event/cnxk/cnxk_tim_worker.c\n+++ b/drivers/event/cnxk/cnxk_tim_worker.c\n@@ -99,3 +99,56 @@ cnxk_tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr,\n \t}\n TIM_ARM_FASTPATH_MODES\n #undef FP\n+\n+static __rte_always_inline uint16_t\n+cnxk_tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr,\n+\t\t\t struct rte_event_timer **tim,\n+\t\t\t const uint64_t timeout_tick,\n+\t\t\t const uint16_t nb_timers, const uint8_t flags)\n+{\n+\tstruct cnxk_tim_ent entry[CNXK_TIM_MAX_BURST] __rte_cache_aligned;\n+\tstruct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;\n+\tuint16_t set_timers = 0;\n+\tuint16_t arr_idx = 0;\n+\tuint16_t idx;\n+\tint ret;\n+\n+\tif (unlikely(!timeout_tick || timeout_tick > tim_ring->nb_bkts)) {\n+\t\tconst enum rte_event_timer_state state =\n+\t\t\ttimeout_tick ? RTE_EVENT_TIMER_ERROR_TOOLATE :\n+\t\t\t\t\t RTE_EVENT_TIMER_ERROR_TOOEARLY;\n+\t\tfor (idx = 0; idx < nb_timers; idx++)\n+\t\t\ttim[idx]->state = state;\n+\n+\t\trte_errno = EINVAL;\n+\t\treturn 0;\n+\t}\n+\n+\tcnxk_tim_sync_start_cyc(tim_ring);\n+\twhile (arr_idx < nb_timers) {\n+\t\tfor (idx = 0; idx < CNXK_TIM_MAX_BURST && (arr_idx < nb_timers);\n+\t\t idx++, arr_idx++) {\n+\t\t\tcnxk_tim_format_event(tim[arr_idx], &entry[idx]);\n+\t\t}\n+\t\tret = cnxk_tim_add_entry_brst(tim_ring, timeout_tick,\n+\t\t\t\t\t &tim[set_timers], entry, idx,\n+\t\t\t\t\t flags);\n+\t\tset_timers += ret;\n+\t\tif (ret != idx)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn set_timers;\n+}\n+\n+#define FP(_name, _f1, _flags) \\\n+\tuint16_t __rte_noinline cnxk_tim_arm_tmo_tick_burst_##_name( \\\n+\t\tconst struct rte_event_timer_adapter *adptr, \\\n+\t\tstruct rte_event_timer **tim, const uint64_t timeout_tick, \\\n+\t\tconst uint16_t nb_timers) \\\n+\t{ \\\n+\t\treturn cnxk_tim_timer_arm_tmo_brst(adptr, tim, timeout_tick, \\\n+\t\t\t\t\t\t nb_timers, _flags); \\\n+\t}\n+TIM_ARM_TMO_FASTPATH_MODES\n+#undef FP\ndiff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h\nindex efdcf8969..7a4cfd1a6 100644\n--- a/drivers/event/cnxk/cnxk_tim_worker.h\n+++ b/drivers/event/cnxk/cnxk_tim_worker.h\n@@ -420,4 +420,145 @@ cnxk_tim_add_entry_mp(struct cnxk_tim_ring *const tim_ring,\n \treturn 0;\n }\n \n+static inline uint16_t\n+cnxk_tim_cpy_wrk(uint16_t index, uint16_t cpy_lmt, struct cnxk_tim_ent *chunk,\n+\t\t struct rte_event_timer **const tim,\n+\t\t const struct cnxk_tim_ent *const ents,\n+\t\t const struct cnxk_tim_bkt *const bkt)\n+{\n+\tfor (; index < cpy_lmt; index++) {\n+\t\t*chunk = *(ents + index);\n+\t\ttim[index]->impl_opaque[0] = (uintptr_t)chunk++;\n+\t\ttim[index]->impl_opaque[1] = (uintptr_t)bkt;\n+\t\ttim[index]->state = RTE_EVENT_TIMER_ARMED;\n+\t}\n+\n+\treturn index;\n+}\n+\n+/* Burst mode functions */\n+static inline int\n+cnxk_tim_add_entry_brst(struct cnxk_tim_ring *const tim_ring,\n+\t\t\tconst uint16_t rel_bkt,\n+\t\t\tstruct rte_event_timer **const tim,\n+\t\t\tconst struct cnxk_tim_ent *ents,\n+\t\t\tconst uint16_t nb_timers, const uint8_t flags)\n+{\n+\tstruct cnxk_tim_ent *chunk = NULL;\n+\tstruct cnxk_tim_bkt *mirr_bkt;\n+\tstruct cnxk_tim_bkt *bkt;\n+\tuint16_t chunk_remainder;\n+\tuint16_t index = 0;\n+\tuint64_t lock_sema;\n+\tint16_t rem, crem;\n+\tuint8_t lock_cnt;\n+\n+__retry:\n+\tcnxk_tim_get_target_bucket(tim_ring, rel_bkt, &bkt, &mirr_bkt);\n+\n+\t/* Only one thread beyond this. */\n+\tlock_sema = cnxk_tim_bkt_inc_lock(bkt);\n+\tlock_cnt = (uint8_t)((lock_sema >> TIM_BUCKET_W1_S_LOCK) &\n+\t\t\t TIM_BUCKET_W1_M_LOCK);\n+\n+\tif (lock_cnt) {\n+\t\tcnxk_tim_bkt_dec_lock(bkt);\n+#ifdef RTE_ARCH_ARM64\n+\t\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t\t \"\t\tldxrb %w[lock_cnt], [%[lock]]\t\\n\"\n+\t\t\t \"\t\ttst %w[lock_cnt], 255\t\t\\n\"\n+\t\t\t \"\t\tbeq dne%=\t\t\t\\n\"\n+\t\t\t \"\t\tsevl\t\t\t\t\\n\"\n+\t\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n+\t\t\t \"\t\tldxrb %w[lock_cnt], [%[lock]]\t\\n\"\n+\t\t\t \"\t\ttst %w[lock_cnt], 255\t\t\\n\"\n+\t\t\t \"\t\tbne rty%=\t\t\t\\n\"\n+\t\t\t \"dne%=:\t\t\t\t\t\\n\"\n+\t\t\t : [lock_cnt] \"=&r\"(lock_cnt)\n+\t\t\t : [lock] \"r\"(&bkt->lock)\n+\t\t\t : \"memory\");\n+#else\n+\t\twhile (__atomic_load_n(&bkt->lock, __ATOMIC_RELAXED))\n+\t\t\t;\n+#endif\n+\t\tgoto __retry;\n+\t}\n+\n+\t/* Bucket related checks. */\n+\tif (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) {\n+\t\tif (cnxk_tim_bkt_get_nent(lock_sema) != 0) {\n+\t\t\tuint64_t hbt_state;\n+#ifdef RTE_ARCH_ARM64\n+\t\t\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t\t\t \"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n+\t\t\t\t \"\t\ttbz %[hbt], 33, dne%=\t\\n\"\n+\t\t\t\t \"\t\tsevl\t\t\t\\n\"\n+\t\t\t\t \"rty%=:\twfe\t\t\t\\n\"\n+\t\t\t\t \"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n+\t\t\t\t \"\t\ttbnz %[hbt], 33, rty%=\t\\n\"\n+\t\t\t\t \"dne%=:\t\t\t\t\\n\"\n+\t\t\t\t : [hbt] \"=&r\"(hbt_state)\n+\t\t\t\t : [w1] \"r\"((&bkt->w1))\n+\t\t\t\t : \"memory\");\n+#else\n+\t\t\tdo {\n+\t\t\t\thbt_state = __atomic_load_n(&bkt->w1,\n+\t\t\t\t\t\t\t __ATOMIC_RELAXED);\n+\t\t\t} while (hbt_state & BIT_ULL(33));\n+#endif\n+\n+\t\t\tif (!(hbt_state & BIT_ULL(34))) {\n+\t\t\t\tcnxk_tim_bkt_dec_lock(bkt);\n+\t\t\t\tgoto __retry;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tchunk_remainder = cnxk_tim_bkt_fetch_rem(lock_sema);\n+\trem = chunk_remainder - nb_timers;\n+\tif (rem < 0) {\n+\t\tcrem = tim_ring->nb_chunk_slots - chunk_remainder;\n+\t\tif (chunk_remainder && crem) {\n+\t\t\tchunk = ((struct cnxk_tim_ent *)\n+\t\t\t\t\t mirr_bkt->current_chunk) +\n+\t\t\t\tcrem;\n+\n+\t\t\tindex = cnxk_tim_cpy_wrk(index, chunk_remainder, chunk,\n+\t\t\t\t\t\t tim, ents, bkt);\n+\t\t\tcnxk_tim_bkt_sub_rem(bkt, chunk_remainder);\n+\t\t\tcnxk_tim_bkt_add_nent(bkt, chunk_remainder);\n+\t\t}\n+\n+\t\tif (flags & CNXK_TIM_ENA_FB)\n+\t\t\tchunk = cnxk_tim_refill_chunk(bkt, mirr_bkt, tim_ring);\n+\t\tif (flags & CNXK_TIM_ENA_DFB)\n+\t\t\tchunk = cnxk_tim_insert_chunk(bkt, mirr_bkt, tim_ring);\n+\n+\t\tif (unlikely(chunk == NULL)) {\n+\t\t\tcnxk_tim_bkt_dec_lock(bkt);\n+\t\t\trte_errno = ENOMEM;\n+\t\t\ttim[index]->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\treturn crem;\n+\t\t}\n+\t\t*(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0;\n+\t\tmirr_bkt->current_chunk = (uintptr_t)chunk;\n+\t\tcnxk_tim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt);\n+\n+\t\trem = nb_timers - chunk_remainder;\n+\t\tcnxk_tim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - rem);\n+\t\tcnxk_tim_bkt_add_nent(bkt, rem);\n+\t} else {\n+\t\tchunk = (struct cnxk_tim_ent *)mirr_bkt->current_chunk;\n+\t\tchunk += (tim_ring->nb_chunk_slots - chunk_remainder);\n+\n+\t\tcnxk_tim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt);\n+\t\tcnxk_tim_bkt_sub_rem(bkt, nb_timers);\n+\t\tcnxk_tim_bkt_add_nent(bkt, nb_timers);\n+\t}\n+\n+\tcnxk_tim_bkt_dec_lock(bkt);\n+\n+\treturn nb_timers;\n+}\n+\n #endif /* __CNXK_TIM_WORKER_H__ */\n", "prefixes": [ "v2", "29/33" ] }