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GET /api/patches/92106/?format=api
{ "id": 92106, "url": "http://patches.dpdk.org/api/patches/92106/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210424103700.8098-7-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210424103700.8098-7-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210424103700.8098-7-hemant.agrawal@nxp.com", "date": "2021-04-24T10:36:58", "name": "[v4,6/8] baseband/la12xx: add enqueue and dequeue support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5b8783212ab3be514051b5c371aa50268a0e7821", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210424103700.8098-7-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 16642, "url": "http://patches.dpdk.org/api/series/16642/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16642", "date": "2021-04-24T10:36:52", "name": "baseband: add NXP LA12xx driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16642/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92106/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92106/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E5ECDA09E4;\n\tSat, 24 Apr 2021 12:39:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 772B04112E;\n\tSat, 24 Apr 2021 12:38:48 +0200 (CEST)", "from EUR01-DB5-obe.outbound.protection.outlook.com\n (mail-eopbgr150078.outbound.protection.outlook.com [40.107.15.78])\n by mails.dpdk.org (Postfix) with ESMTP id 1203A41118\n for <dev@dpdk.org>; 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dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=nxp.com;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com,\n\tnicolas.chautru@intel.com", "Cc": "david.marchand@redhat.com, Hemant Agrawal <hemant.agrawal@nxp.com>,\n Nipun Gupta <nipun.gupta@nxp.com>", "Date": "Sat, 24 Apr 2021 16:06:58 +0530", "Message-Id": "<20210424103700.8098-7-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210424103700.8098-1-hemant.agrawal@nxp.com>", "References": "<20210413051715.26430-2-hemant.agrawal@nxp.com>\n <20210424103700.8098-1-hemant.agrawal@nxp.com>", "Content-Type": "text/plain", "X-Originating-IP": "[92.120.0.67]", "X-ClientProxiedBy": "HK2PR04CA0088.apcprd04.prod.outlook.com\n (2603:1096:202:15::32) To AM6PR04MB4456.eurprd04.prod.outlook.com\n (2603:10a6:20b:22::25)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "63110e5b-0abf-4b34-6bab-08d9070d2209", "X-MS-TrafficTypeDiagnostic": "AM6PR0402MB3895:", "X-MS-Exchange-Transport-Forked": "True", "X-Microsoft-Antispam-PRVS": "\n <AM6PR0402MB389568B199E1AB64EBB5E11C89449@AM6PR0402MB3895.eurprd04.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1060;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n mt7Gjay80YpiLMPuHCMRaTIwcq+w22Jo07wsziDSb0M4jukjMHXVtmn6DYsPyGXDThpinD/4moBNln8ToF7xwJnJKASqW8lajUF4Cmyhwz5O3UqGM1JYsuNlPPq9rFs7uLxCrq++bNhyLOQTELsIgzZkAmTEba9ttyJ8t9FsmIuxBJ4kTuxQcXQXB62ZIh55ul/4Kcp1Rr2x+hwB3cZuNyRePEB0ozS1ZXefYch+m0Dmp0RSS9bTgRY3UsGWB0eA0eKpuoEUwGx+WrYnmBFlRjgg4RKyAXKRLWKprP8XgiwOvEA8IK3q42wlawDJsN5OBRXITf1rRBr9jHR4ry9/B3aOCesy+OqZHfu2f/e3wx8qT51hBmAHZQK9j6CrsCC4pGg3Xx4K2d7esMIctP74srzwUUSbm420K/JfwBtl1IJkwsOcSYPsm9EMU9zKiNdKK5QcogngXqsvkK7DaZ7/GULAXg556oFP5D0bpgLa6Egd8XjFc/ZA1piAS1fl6+hKS3234ylveRW36j0wHRWJAZcF+YTXtBsZEQLrs5MZ1xthwQBfutWwPPiAfQBS/n5MPkTj+vv7BT9BgW3qoXc+LJhLDt1BkBQmqqI1vWlmxIMMLbTjhuLB5aCWgYTiiGSXAhiOE2PO3ZgpBDASwexnIU4mVdOz1RGqNIK/KmWe5ZQ=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:AM6PR04MB4456.eurprd04.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(4636009)(39860400002)(396003)(136003)(376002)(366004)(346002)(8936002)(5660300002)(316002)(1076003)(54906003)(8676002)(6512007)(86362001)(478600001)(30864003)(38100700002)(2906002)(956004)(2616005)(38350700002)(36756003)(6666004)(186003)(83380400001)(26005)(4326008)(16526019)(6506007)(52116002)(6486002)(44832011)(66476007)(66556008)(66946007);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData": "\n R2yUhxHcUOkUn2Kf8yySk+zstGudU9eJoEUfjMWj4nSzvY8KfMs/vTDyk6ZQyp0T/fntXXDoDqB1CyakhrbVjQm5s+C+UcH4iJoUaCYXoeGkh61rh3Z/ipdZpfrs0VUD7UYda+kEbzmgR0Bf1MIcCRNzZ7wrFwtw0LypOejyips5fhe3LmQN8YSm8SaBLbcNOF5Lchy2UdyXX37OfJ2iKPrOITwGI4JA6A1VbscPOTCAXDRouDzyXi1OvCuwbu9Yg6lORCNsJOovl9gNcuheI4GXf0W+JMNP7X5etHC4Wr8aqTIaS0jBFvqdkvRnq0XkSAi9Qdog3N30ZZMDkNakOLhNire8uQkR14jZOZPzqJW3hSJBgEMRWIsPPJkAlCGnMZR/FsVHjFzOP2AeADkQ19yfDwGXVj/zLGrsWRsXJq1/w35Vz20X/5tNf0CP5nqv6S4JzoziyS3vhbgfJutCKjoxKPmyP3NYD3RBpwvfcyH8hPo4llRJ0pfKxu8mKm5HBLzuveY3qSr3hd9ksmY0o5QDJZa9G7m3EcrbUj3kJXCSd9qdkf1Uvbt8w4MiuClQfrI1LqdNC+G6LcOjtuR6627GdEk3xDknFfW5S2SI9JJPcpRh1wagqG9yqxLnBnVxWLAhGIGpngp34luBJ3l/CAQw2QXK8TI3G456g31T9hGAgEZEpEUACHUPk6DMgTgL5Xs+UVz3UcZmBFjOi7gFQtEaWPiZr+Wb0fhC0gq6tWDfJgPcRZhoojYbrIlh2qiwemLy3V/k+32rPFUgZEjTSvfzfsa5V0XTpEjqr1nX4RlPpUCZUquLsomK4N5hsJDGmuOIH/EMUOOMoBrFfK5gbwr35BKD/N/Ihg4VpjIQ9yQ6gHvWPbZDLGmR0KupESoQRyvqLYQxfP+xIdag+OkQzpsqvQLZaid0+JWPJR1U9f87qiTQbVASqhNzgvkEFyD7oCsFyOBQMpjX+OrgBui+c+2scfbBkTSxFTTlxtQpZY91cPszJJwXKFUmxg8UV6eyofiG5f4lUD2ONDUhFptnG2gJKEXCtP0lLI0l8pQz3YAus1ODPQPhyCIcp7vkCwm64eb4pMPI9BnX7KFV0zd017ePjhigXMBSH4g5iY7z4x7s7vgeh96R8hjJADfCIHs7nEZWQSQ4X+MyR0HHujONLvGbCnibKy5s4EDXg1JunlmCb6r5EBs+bBR2nehmKUx+fzFowSVkoRrHdyKXym5dkR1dcsXzbWiYx9uRtdxmZdCjAmNSuq9Y3iIS4IA1wMkU7x0i4+0ZsiHT1tOgGzLpB59U1muqD5mPW54qOiLvrB/+dbduzbpdM6pOtXWIbHej", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 63110e5b-0abf-4b34-6bab-08d9070d2209", "X-MS-Exchange-CrossTenant-AuthSource": "AM6PR04MB4456.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Apr 2021 10:38:43.9786 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n tYxXyXURu5jMRX3tZD1KjHxoxkY3sszLXlM+YFfkBgSWtf2GGXemd28Lr57U1zj1MJhnYeEOIWBNDOoSeV17XA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM6PR0402MB3895", "Subject": "[dpdk-dev] [PATCH v4 6/8] baseband/la12xx: add enqueue and dequeue\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for enqueue and dequeue the LDPC enc/dec\nfrom the modem device.\n\nSigned-off-by: Nipun Gupta <nipun.gupta@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n doc/guides/bbdevs/features/la12xx.ini | 14 +\n doc/guides/bbdevs/la12xx.rst | 46 +++\n drivers/baseband/la12xx/bbdev_la12xx.c | 334 ++++++++++++++++++++-\n drivers/baseband/la12xx/bbdev_la12xx_ipc.h | 37 +++\n 4 files changed, 425 insertions(+), 6 deletions(-)\n create mode 100644 doc/guides/bbdevs/features/la12xx.ini", "diff": "diff --git a/doc/guides/bbdevs/features/la12xx.ini b/doc/guides/bbdevs/features/la12xx.ini\nnew file mode 100644\nindex 0000000000..d184914b10\n--- /dev/null\n+++ b/doc/guides/bbdevs/features/la12xx.ini\n@@ -0,0 +1,14 @@\n+;\n+; Supported features of the 'la12xx' bbdev driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Turbo Decoder (4G) = N\n+Turbo Encoder (4G) = N\n+LDPC Decoder (5G) = Y\n+LDPC Encoder (5G) = Y\n+LLR/HARQ Compression = N\n+HW Accelerated = Y\n+BBDEV API = Y\n+Network Order Data = Y\n\\ No newline at end of file\ndiff --git a/doc/guides/bbdevs/la12xx.rst b/doc/guides/bbdevs/la12xx.rst\nindex 3c9ac5c047..c39be0e51f 100644\n--- a/doc/guides/bbdevs/la12xx.rst\n+++ b/doc/guides/bbdevs/la12xx.rst\n@@ -16,6 +16,8 @@ Features\n \n LA12xx PMD supports the following features:\n \n+- LDPC Encode in the DL\n+- LDPC Decode in the UL\n - Maximum of 8 UL queues\n - Maximum of 8 DL queues\n - PCIe Gen-3 x8 Interface\n@@ -79,3 +81,47 @@ For enabling logs, use the following EAL parameter:\n \n Using ``bb.la12xx`` as log matching criteria, all Baseband PMD logs can be\n enabled which are lower than logging ``level``.\n+\n+Test Application\n+----------------\n+\n+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing\n+the functionality of LA12xx for FEC encode and decode, depending on the device\n+capabilities. The test application is located under app->test-bbdev folder and has the\n+following options:\n+\n+.. code-block:: console\n+\n+ \"-p\", \"--testapp-path\": specifies path to the bbdev test app.\n+ \"-e\", \"--eal-params\"\t: EAL arguments which are passed to the test app.\n+ \"-t\", \"--timeout\"\t: Timeout in seconds (default=300).\n+ \"-c\", \"--test-cases\"\t: Defines test cases to run. Run all if not specified.\n+ \"-v\", \"--test-vector\"\t: Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).\n+ \"-n\", \"--num-ops\"\t: Number of operations to process on device (default=32).\n+ \"-b\", \"--burst-size\"\t: Operations enqueue/dequeue burst size (default=32).\n+ \"-s\", \"--snr\"\t\t: SNR in dB used when generating LLRs for bler tests.\n+ \"-s\", \"--iter_max\"\t: Number of iterations for LDPC decoder.\n+ \"-l\", \"--num-lcores\"\t: Number of lcores to run (default=16).\n+ \"-i\", \"--init-device\" : Initialise PF device with default values.\n+\n+\n+To execute the test application tool using simple decode or encode data,\n+type one of the following:\n+\n+.. code-block:: console\n+\n+ ./test-bbdev.py -e=\"--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8\" -c validation -n 64 -b 1 -v ./ldpc_dec_default.data\n+ ./test-bbdev.py -e=\"--vdev=baseband_la12xx,socket_id=0,max_nb_queues=8\" -c validation -n 64 -b 1 -v ./ldpc_enc_default.data\n+\n+The test application ``test-bbdev.py``, supports the ability to configure the PF device with\n+a default set of values, if the \"-i\" or \"- -init-device\" option is included. The default values\n+are defined in test_bbdev_perf.c.\n+\n+\n+Test Vectors\n+~~~~~~~~~~~~\n+\n+In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides\n+a range of additional tests under the test_vectors folder, which may be useful. The results\n+of these tests will depend on the LA12xx FEC capabilities which may cause some\n+testcases to be skipped, but no failure should be reported.\ndiff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c\nindex 1fdeca279e..50e3284622 100644\n--- a/drivers/baseband/la12xx/bbdev_la12xx.c\n+++ b/drivers/baseband/la12xx/bbdev_la12xx.c\n@@ -54,7 +54,8 @@ static const struct rte_bbdev_op_cap bbdev_capabilities[] = {\n \t\t.cap.ldpc_enc = {\n \t\t\t.capability_flags =\n \t\t\t\t\tRTE_BBDEV_LDPC_CRC_24A_ATTACH |\n-\t\t\t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH,\n+\t\t\t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH |\n+\t\t\t\t\tRTE_BBDEV_LDPC_ENC_NETWORK_ORDER,\n \t\t\t.num_buffers_src =\n \t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n \t\t\t.num_buffers_dst =\n@@ -68,7 +69,8 @@ static const struct rte_bbdev_op_cap bbdev_capabilities[] = {\n \t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK |\n \t\t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION |\n \t\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK |\n-\t\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_DROP,\n+\t\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_DROP |\n+\t\t\t\t\tRTE_BBDEV_LDPC_DEC_NETWORK_ORDER,\n \t\t\t.num_buffers_src =\n \t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n \t\t\t.num_buffers_hard_out =\n@@ -121,6 +123,10 @@ la12xx_queue_release(struct rte_bbdev *dev, uint16_t q_id)\n \t\t((uint64_t) ((unsigned long) (A) \\\n \t\t- ((uint64_t)ipc_priv->hugepg_start.host_vaddr)))\n \n+#define MODEM_P2V(A) \\\n+\t((uint64_t) ((unsigned long) (A) \\\n+\t\t+ (unsigned long)(ipc_priv->peb_start.host_vaddr)))\n+\n static int ipc_queue_configure(uint32_t channel_id,\n \t\tipc_t instance, struct bbdev_la12xx_q_priv *q_priv)\n {\n@@ -335,6 +341,318 @@ static const struct rte_bbdev_ops pmd_ops = {\n \t.queue_release = la12xx_queue_release,\n \t.start = la12xx_start\n };\n+\n+static inline int\n+is_bd_ring_full(uint32_t ci, uint32_t ci_flag,\n+\t\tuint32_t pi, uint32_t pi_flag)\n+{\n+\tif (pi == ci) {\n+\t\tif (pi_flag != ci_flag)\n+\t\t\treturn 1; /* Ring is Full */\n+\t}\n+\treturn 0;\n+}\n+\n+static inline int\n+prepare_ldpc_enc_op(struct rte_bbdev_enc_op *bbdev_enc_op,\n+\t\t struct bbdev_la12xx_q_priv *q_priv __rte_unused,\n+\t\t struct rte_bbdev_op_data *in_op_data __rte_unused,\n+\t\t struct rte_bbdev_op_data *out_op_data)\n+{\n+\tstruct rte_bbdev_op_ldpc_enc *ldpc_enc = &bbdev_enc_op->ldpc_enc;\n+\tuint32_t total_out_bits;\n+\n+\ttotal_out_bits = (ldpc_enc->tb_params.cab *\n+\t\tldpc_enc->tb_params.ea) + (ldpc_enc->tb_params.c -\n+\t\tldpc_enc->tb_params.cab) * ldpc_enc->tb_params.eb;\n+\n+\tldpc_enc->output.length = (total_out_bits + 7)/8;\n+\n+\trte_pktmbuf_append(out_op_data->data, ldpc_enc->output.length);\n+\n+\treturn 0;\n+}\n+\n+static inline int\n+prepare_ldpc_dec_op(struct rte_bbdev_dec_op *bbdev_dec_op,\n+\t\t struct bbdev_ipc_dequeue_op *bbdev_ipc_op,\n+\t\t struct bbdev_la12xx_q_priv *q_priv __rte_unused,\n+\t\t struct rte_bbdev_op_data *out_op_data __rte_unused)\n+{\n+\tstruct rte_bbdev_op_ldpc_dec *ldpc_dec = &bbdev_dec_op->ldpc_dec;\n+\tuint32_t total_out_bits;\n+\tuint32_t num_code_blocks = 0;\n+\tuint16_t sys_cols;\n+\n+\tsys_cols = (ldpc_dec->basegraph == 1) ? 22 : 10;\n+\tif (ldpc_dec->tb_params.c == 1) {\n+\t\ttotal_out_bits = ((sys_cols * ldpc_dec->z_c) -\n+\t\t\t\tldpc_dec->n_filler);\n+\t\t/* 5G-NR protocol uses 16 bit CRC when output packet\n+\t\t * size <= 3824 (bits). Otherwise 24 bit CRC is used.\n+\t\t * Adjust the output bits accordingly\n+\t\t */\n+\t\tif (total_out_bits - 16 <= 3824)\n+\t\t\ttotal_out_bits -= 16;\n+\t\telse\n+\t\t\ttotal_out_bits -= 24;\n+\t\tldpc_dec->hard_output.length = (total_out_bits / 8);\n+\t} else {\n+\t\ttotal_out_bits = (((sys_cols * ldpc_dec->z_c) -\n+\t\t\t\tldpc_dec->n_filler - 24) *\n+\t\t\t\tldpc_dec->tb_params.c);\n+\t\tldpc_dec->hard_output.length = (total_out_bits / 8) - 3;\n+\t}\n+\n+\tnum_code_blocks = ldpc_dec->tb_params.c;\n+\n+\tbbdev_ipc_op->num_code_blocks = rte_cpu_to_be_32(num_code_blocks);\n+\n+\treturn 0;\n+}\n+\n+static int\n+enqueue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *bbdev_op)\n+{\n+\tstruct bbdev_la12xx_private *priv = q_priv->bbdev_priv;\n+\tipc_userspace_t *ipc_priv = priv->ipc_priv;\n+\tipc_instance_t *ipc_instance = ipc_priv->instance;\n+\tstruct bbdev_ipc_dequeue_op *bbdev_ipc_op;\n+\tstruct rte_bbdev_op_ldpc_enc *ldpc_enc;\n+\tstruct rte_bbdev_op_ldpc_dec *ldpc_dec;\n+\tuint32_t q_id = q_priv->q_id;\n+\tuint32_t ci, ci_flag, pi, pi_flag;\n+\tipc_ch_t *ch = &(ipc_instance->ch_list[q_id]);\n+\tipc_br_md_t *md = &(ch->md);\n+\tsize_t virt;\n+\tchar *huge_start_addr =\n+\t\t(char *)q_priv->bbdev_priv->ipc_priv->hugepg_start.host_vaddr;\n+\tstruct rte_bbdev_op_data *in_op_data, *out_op_data;\n+\tchar *data_ptr;\n+\tuint32_t l1_pcie_addr;\n+\tint ret;\n+\n+\tci = IPC_GET_CI_INDEX(q_priv->host_ci);\n+\tci_flag = IPC_GET_CI_FLAG(q_priv->host_ci);\n+\n+\tpi = IPC_GET_PI_INDEX(q_priv->host_pi);\n+\tpi_flag = IPC_GET_PI_FLAG(q_priv->host_pi);\n+\n+\trte_bbdev_dp_log(DEBUG, \"before bd_ring_full: pi: %u, ci: %u,\"\n+\t\t\"pi_flag: %u, ci_flag: %u, ring size: %u\",\n+\t\tpi, ci, pi_flag, ci_flag, q_priv->queue_size);\n+\n+\tif (is_bd_ring_full(ci, ci_flag, pi, pi_flag)) {\n+\t\trte_bbdev_dp_log(DEBUG, \"bd ring full for queue id: %d\", q_id);\n+\t\treturn IPC_CH_FULL;\n+\t}\n+\n+\tvirt = MODEM_P2V(q_priv->host_params->bd_m_modem_ptr[pi]);\n+\tbbdev_ipc_op = (struct bbdev_ipc_dequeue_op *)virt;\n+\tq_priv->bbdev_op[pi] = bbdev_op;\n+\n+\tswitch (q_priv->op_type) {\n+\tcase RTE_BBDEV_OP_LDPC_ENC:\n+\t\tldpc_enc = &(((struct rte_bbdev_enc_op *)bbdev_op)->ldpc_enc);\n+\t\tin_op_data = &ldpc_enc->input;\n+\t\tout_op_data = &ldpc_enc->output;\n+\n+\t\tret = prepare_ldpc_enc_op(bbdev_op, q_priv,\n+\t\t\t\t\t in_op_data, out_op_data);\n+\t\tif (ret) {\n+\t\t\trte_bbdev_log(ERR, \"process_ldpc_enc_op fail, ret: %d\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase RTE_BBDEV_OP_LDPC_DEC:\n+\t\tldpc_dec = &(((struct rte_bbdev_dec_op *)bbdev_op)->ldpc_dec);\n+\t\tin_op_data = &ldpc_dec->input;\n+\n+\t\tout_op_data = &ldpc_dec->hard_output;\n+\n+\t\tret = prepare_ldpc_dec_op(bbdev_op, bbdev_ipc_op,\n+\t\t\t\t\t q_priv, out_op_data);\n+\t\tif (ret) {\n+\t\t\trte_bbdev_log(ERR, \"process_ldpc_dec_op fail, ret: %d\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\trte_bbdev_log(ERR, \"unsupported bbdev_ipc op type\");\n+\t\treturn -1;\n+\t}\n+\n+\tif (in_op_data->data) {\n+\t\tdata_ptr = rte_pktmbuf_mtod(in_op_data->data, char *);\n+\t\tl1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR +\n+\t\t\t data_ptr - huge_start_addr;\n+\t\tbbdev_ipc_op->in_addr = l1_pcie_addr;\n+\t\tbbdev_ipc_op->in_len = in_op_data->length;\n+\t}\n+\n+\tif (out_op_data->data) {\n+\t\tdata_ptr = rte_pktmbuf_mtod(out_op_data->data, char *);\n+\t\tl1_pcie_addr = (uint32_t)GUL_USER_HUGE_PAGE_ADDR +\n+\t\t\t\tdata_ptr - huge_start_addr;\n+\t\tbbdev_ipc_op->out_addr = rte_cpu_to_be_32(l1_pcie_addr);\n+\t\tbbdev_ipc_op->out_len = rte_cpu_to_be_32(out_op_data->length);\n+\t}\n+\n+\t/* Move Producer Index forward */\n+\tpi++;\n+\t/* Flip the PI flag, if wrapping */\n+\tif (unlikely(q_priv->queue_size == pi)) {\n+\t\tpi = 0;\n+\t\tpi_flag = pi_flag ? 0 : 1;\n+\t}\n+\n+\tif (pi_flag)\n+\t\tIPC_SET_PI_FLAG(pi);\n+\telse\n+\t\tIPC_RESET_PI_FLAG(pi);\n+\tq_priv->host_pi = pi;\n+\n+\t/* Wait for Data Copy & pi_flag update to complete before updating pi */\n+\trte_mb();\n+\t/* now update pi */\n+\tmd->pi = rte_cpu_to_be_32(pi);\n+\n+\trte_bbdev_dp_log(DEBUG, \"enter: pi: %u, ci: %u,\"\n+\t\t\t\"pi_flag: %u, ci_flag: %u, ring size: %u\",\n+\t\t\tpi, ci, pi_flag, ci_flag, q_priv->queue_size);\n+\n+\treturn 0;\n+}\n+\n+/* Enqueue decode burst */\n+static uint16_t\n+enqueue_dec_ops(struct rte_bbdev_queue_data *q_data,\n+\t\tstruct rte_bbdev_dec_op **ops, uint16_t nb_ops)\n+{\n+\tstruct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;\n+\tint nb_enqueued, ret;\n+\n+\tfor (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) {\n+\t\tret = enqueue_single_op(q_priv, ops[nb_enqueued]);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t}\n+\n+\tq_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued;\n+\tq_data->queue_stats.enqueued_count += nb_enqueued;\n+\n+\treturn nb_enqueued;\n+}\n+\n+/* Enqueue encode burst */\n+static uint16_t\n+enqueue_enc_ops(struct rte_bbdev_queue_data *q_data,\n+\t\tstruct rte_bbdev_enc_op **ops, uint16_t nb_ops)\n+{\n+\tstruct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;\n+\tint nb_enqueued, ret;\n+\n+\tfor (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) {\n+\t\tret = enqueue_single_op(q_priv, ops[nb_enqueued]);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t}\n+\n+\tq_data->queue_stats.enqueue_err_count += nb_ops - nb_enqueued;\n+\tq_data->queue_stats.enqueued_count += nb_enqueued;\n+\n+\treturn nb_enqueued;\n+}\n+\n+/* Dequeue encode burst */\n+static void *\n+dequeue_single_op(struct bbdev_la12xx_q_priv *q_priv, void *dst)\n+{\n+\tvoid *op;\n+\tuint32_t ci, ci_flag;\n+\tuint32_t temp_ci;\n+\n+\ttemp_ci = q_priv->host_params->ci;\n+\tif (temp_ci == q_priv->host_ci)\n+\t\treturn NULL;\n+\n+\tci = IPC_GET_CI_INDEX(q_priv->host_ci);\n+\tci_flag = IPC_GET_CI_FLAG(q_priv->host_ci);\n+\n+\trte_bbdev_dp_log(DEBUG,\n+\t\t\"ci: %u, ci_flag: %u, ring size: %u\",\n+\t\tci, ci_flag, q_priv->queue_size);\n+\n+\top = q_priv->bbdev_op[ci];\n+\n+\trte_memcpy(dst, q_priv->msg_ch_vaddr[ci],\n+\t\tsizeof(struct bbdev_ipc_enqueue_op));\n+\n+\t/* Move Consumer Index forward */\n+\tci++;\n+\t/* Flip the CI flag, if wrapping */\n+\tif (q_priv->queue_size == ci) {\n+\t\tci = 0;\n+\t\tci_flag = ci_flag ? 0 : 1;\n+\t}\n+\tif (ci_flag)\n+\t\tIPC_SET_CI_FLAG(ci);\n+\telse\n+\t\tIPC_RESET_CI_FLAG(ci);\n+\n+\tq_priv->host_ci = ci;\n+\n+\trte_bbdev_dp_log(DEBUG,\n+\t\t\"exit: ci: %u, ci_flag: %u, ring size: %u\",\n+\t\tci, ci_flag, q_priv->queue_size);\n+\n+\treturn op;\n+}\n+\n+/* Dequeue decode burst */\n+static uint16_t\n+dequeue_dec_ops(struct rte_bbdev_queue_data *q_data,\n+\t\tstruct rte_bbdev_dec_op **ops, uint16_t nb_ops)\n+{\n+\tstruct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;\n+\tstruct bbdev_ipc_enqueue_op bbdev_ipc_op;\n+\tint nb_dequeued;\n+\n+\tfor (nb_dequeued = 0; nb_dequeued < nb_ops; nb_dequeued++) {\n+\t\tops[nb_dequeued] = dequeue_single_op(q_priv, &bbdev_ipc_op);\n+\t\tif (!ops[nb_dequeued])\n+\t\t\tbreak;\n+\t\tops[nb_dequeued]->status = bbdev_ipc_op.status;\n+\t}\n+\tq_data->queue_stats.dequeued_count += nb_dequeued;\n+\n+\treturn nb_dequeued;\n+}\n+\n+/* Dequeue encode burst */\n+static uint16_t\n+dequeue_enc_ops(struct rte_bbdev_queue_data *q_data,\n+\t\tstruct rte_bbdev_enc_op **ops, uint16_t nb_ops)\n+{\n+\tstruct bbdev_la12xx_q_priv *q_priv = q_data->queue_private;\n+\tstruct bbdev_ipc_enqueue_op bbdev_ipc_op;\n+\tint nb_enqueued;\n+\n+\tfor (nb_enqueued = 0; nb_enqueued < nb_ops; nb_enqueued++) {\n+\t\tops[nb_enqueued] = dequeue_single_op(q_priv, &bbdev_ipc_op);\n+\t\tif (!ops[nb_enqueued])\n+\t\t\tbreak;\n+\t\tops[nb_enqueued]->status = bbdev_ipc_op.status;\n+\t}\n+\tq_data->queue_stats.enqueued_count += nb_enqueued;\n+\n+\treturn nb_enqueued;\n+}\n+\n static struct hugepage_info *\n get_hugepage_info(void)\n {\n@@ -708,10 +1026,14 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev,\n \tbbdev->intr_handle = NULL;\n \n \t/* register rx/tx burst functions for data path */\n-\tbbdev->dequeue_enc_ops = NULL;\n-\tbbdev->dequeue_dec_ops = NULL;\n-\tbbdev->enqueue_enc_ops = NULL;\n-\tbbdev->enqueue_dec_ops = NULL;\n+\tbbdev->dequeue_enc_ops = dequeue_enc_ops;\n+\tbbdev->dequeue_dec_ops = dequeue_dec_ops;\n+\tbbdev->enqueue_enc_ops = enqueue_enc_ops;\n+\tbbdev->enqueue_dec_ops = enqueue_dec_ops;\n+\tbbdev->dequeue_ldpc_enc_ops = dequeue_enc_ops;\n+\tbbdev->dequeue_ldpc_dec_ops = dequeue_dec_ops;\n+\tbbdev->enqueue_ldpc_enc_ops = enqueue_enc_ops;\n+\tbbdev->enqueue_ldpc_dec_ops = enqueue_dec_ops;\n \n \treturn 0;\n }\ndiff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h\nindex 5f613fb087..b6a7f677d0 100644\n--- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h\n+++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h\n@@ -73,6 +73,25 @@ typedef struct {\n \t_IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *)\n #define IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int *)\n \n+#define GUL_USER_HUGE_PAGE_OFFSET\t(0)\n+#define GUL_PCI1_ADDR_BASE\t(0x00000000ULL)\n+\n+#define GUL_USER_HUGE_PAGE_ADDR\t(GUL_PCI1_ADDR_BASE + GUL_USER_HUGE_PAGE_OFFSET)\n+\n+/* IPC PI/CI index & flag manipulation helpers */\n+#define IPC_PI_CI_FLAG_MASK\t0x80000000 /* (1<<31) */\n+#define IPC_PI_CI_INDEX_MASK\t0x7FFFFFFF /* ~(1<<31) */\n+\n+#define IPC_SET_PI_FLAG(x)\t(x |= IPC_PI_CI_FLAG_MASK)\n+#define IPC_RESET_PI_FLAG(x)\t(x &= IPC_PI_CI_INDEX_MASK)\n+#define IPC_GET_PI_FLAG(x)\t(x >> 31)\n+#define IPC_GET_PI_INDEX(x)\t(x & IPC_PI_CI_INDEX_MASK)\n+\n+#define IPC_SET_CI_FLAG(x)\t(x |= IPC_PI_CI_FLAG_MASK)\n+#define IPC_RESET_CI_FLAG(x)\t(x &= IPC_PI_CI_INDEX_MASK)\n+#define IPC_GET_CI_FLAG(x)\t(x >> 31)\n+#define IPC_GET_CI_INDEX(x)\t(x & IPC_PI_CI_INDEX_MASK)\n+\n /** buffer ring common metadata */\n typedef struct ipc_bd_ring_md {\n \tvolatile uint32_t pi;\t\t/**< Producer index and flag (MSB)\n@@ -180,6 +199,24 @@ struct bbdev_ipc_enqueue_op {\n \tuint32_t rsvd;\n };\n \n+/** Structure specifying dequeue operation (dequeue at LA1224) */\n+struct bbdev_ipc_dequeue_op {\n+\t/** Input buffer memory address */\n+\tuint32_t in_addr;\n+\t/** Input buffer memory length */\n+\tuint32_t in_len;\n+\t/** Output buffer memory address */\n+\tuint32_t out_addr;\n+\t/** Output buffer memory length */\n+\tuint32_t out_len;\n+\t/* Number of code blocks. Only set when HARQ is used */\n+\tuint32_t num_code_blocks;\n+\t/** Dequeue Operation flags */\n+\tuint32_t op_flags;\n+\t/** Shared metadata between L1 and L2 */\n+\tuint32_t shared_metadata;\n+};\n+\n /* This shared memory would be on the host side which have copy of some\n * of the parameters which are also part of Shared BD ring. Read access\n * of these parameters from the host side would not be over PCI.\n", "prefixes": [ "v4", "6/8" ] }