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GET /api/patches/92105/?format=api
{ "id": 92105, "url": "http://patches.dpdk.org/api/patches/92105/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210424103700.8098-6-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210424103700.8098-6-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210424103700.8098-6-hemant.agrawal@nxp.com", "date": "2021-04-24T10:36:57", "name": "[v4,5/8] baseband/la12xx: add queue and modem config support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "27029b72493887313aa60592d35ca5ede89b7800", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210424103700.8098-6-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 16642, "url": "http://patches.dpdk.org/api/series/16642/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16642", "date": "2021-04-24T10:36:52", "name": "baseband: add NXP LA12xx driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16642/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92105/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92105/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2BA3AA09E4;\n\tSat, 24 Apr 2021 12:39:02 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4ADB1410FA;\n\tSat, 24 Apr 2021 12:38:47 +0200 (CEST)", "from EUR01-DB5-obe.outbound.protection.outlook.com\n (mail-eopbgr150059.outbound.protection.outlook.com [40.107.15.59])\n by mails.dpdk.org (Postfix) with ESMTP id AA4834112B\n for <dev@dpdk.org>; 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dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=nxp.com;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com,\n\tnicolas.chautru@intel.com", "Cc": "david.marchand@redhat.com, Hemant Agrawal <hemant.agrawal@nxp.com>,\n Nipun Gupta <nipun.gupta@nxp.com>", "Date": "Sat, 24 Apr 2021 16:06:57 +0530", "Message-Id": "<20210424103700.8098-6-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210424103700.8098-1-hemant.agrawal@nxp.com>", "References": "<20210413051715.26430-2-hemant.agrawal@nxp.com>\n <20210424103700.8098-1-hemant.agrawal@nxp.com>", "Content-Type": "text/plain", "X-Originating-IP": "[92.120.0.67]", "X-ClientProxiedBy": "HK2PR04CA0088.apcprd04.prod.outlook.com\n (2603:1096:202:15::32) To AM6PR04MB4456.eurprd04.prod.outlook.com\n (2603:10a6:20b:22::25)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "4f0f2cc2-2e8d-434d-6c1a-08d9070d202a", "X-MS-TrafficTypeDiagnostic": "AM6PR0402MB3895:", "X-MS-Exchange-Transport-Forked": "True", "X-Microsoft-Antispam-PRVS": "\n <AM6PR0402MB389528BD99664EFC18CF59F989449@AM6PR0402MB3895.eurprd04.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:431;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ESdlpQQmoDtD7j6YUCbsr13vTBMzv1QqyIrQ4GYA/jGcpR6PKpvWx/f9UVQxX/QORHPWJX4XtPZqD1zwNPq1Ri/RmvoQDVwNuL1f5RvOlcBnhvb2hcx5RtGR2blMzrTBlcrGJT2y6z/0J6BNszOL7c5+Cmlqyb0PcUG2CTwJth5oG7VZbPxlDaOXqHgT4eX4BEb1+doftA1dOCcLowgqfPFxVtAgp2hZIkw5sd1HU9U0W2a8UbxpUavTrkD9LVWCs2m2g27iBFO0L9ibTin2NY5PW5oqw29fXDEXxk8vd5GaK/TrXFf1Sxz1vbiUo890ahWJm9UjF7YE4Yt2F91lJOFakLluFs5UfVcvy8sCmyx8CpSslRdWFJOrBFi2unMmKv4lOu1jYukSmJn/HfkA6zSpd9kbUoh0k7Mr1W/i5xlJpIZGi63gkd4GWgX4+GE5rTDQ6/pW5v+6U9UzECzcHKj5mc0JtuEpwTWIr2t/An2DYofeYQ15A+cT3iOqFP3q+PcxI6USRJRAj/UDMrHFeP+W3E+lzMa1hlQ/lDzWeph4yGruk9Ifsy2sKzGJiCdsHbRCJ+7cBsyAUcXDRS/OhSAec4QdVY7PP9EGg9AY68cMQ3ssHS3A2a0eB7Y76e2KJfZUNgcK1bPO8y+oRL1xGFY4KxlnmwS+NmygmJoMvdTWG4iH5O/pvyv8NmCXtSo2vrZxCGqUrKXD0ju4YL6H8sqQTsl1Tw3nRs7YrEGvcszruWFpHqZMx/eAwVNtuT0s", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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SPDX-License-Identifier: BSD-3-Clause\n+ Copyright 2021 NXP\n+\n+NXP LA12xx Poll Mode Driver\n+=======================================\n+\n+The BBDEV LA12xx poll mode driver (PMD) supports an implementation for\n+offloading High Phy processing functions like LDPC Encode / Decode 5GNR wireless\n+acceleration function, using PCI based LA12xx Software defined radio.\n+\n+More information can be found at `NXP Official Website\n+<https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-access-la1200-programmable-baseband-processor:LA1200>`_.\n+\n+Features\n+--------\n+\n+LA12xx PMD supports the following features:\n+\n+- Maximum of 8 UL queues\n+- Maximum of 8 DL queues\n+- PCIe Gen-3 x8 Interface\n+- MSI-X\n+\n+Installation\n+------------\n+\n+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.\n+\n+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.\n+\n+Initialization\n+--------------\n+\n+The device can be listed on the host console with:\n+\n+\n+Use the following lspci command to get the multiple LA12xx processor ids. The\n+device ID of the LA12xx baseband processor is \"1c30\".\n+\n+.. code-block:: console\n+\n+ sudo lspci -nn\n+\n+...\n+0001:01:00.0 Power PC [0b20]: Freescale Semiconductor Inc Device [1957:1c30] (\n+rev 10)\n+...\n+0002:01:00.0 Power PC [0b20]: Freescale Semiconductor Inc Device [1957:1c30] (\n+rev 10)\n+\n+\n+Prerequisites\n+-------------\n+\n+Currently supported by DPDK:\n+\n+- NXP LA1224 BSP **1.0+**.\n+- NXP LA1224 PCIe Modem card connected to ARM host.\n+\n+- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.\n+\n+* Use dev arg option ``modem=0`` to identify the modem instance for a given\n+ device. This is required only if more than 1 modem cards are attached to host.\n+ this is optional and the default value is 0.\n+ e.g. ``--vdev=baseband_la12xx,modem=0``\n+\n+* Use dev arg option ``max_nb_queues=x`` to specify the maximum number of queues\n+ to be used for communication with offload device i.e. modem. default is 16.\n+ e.g. ``--vdev=baseband_la12xx,max_nb_queues=4``\n+\n+Enabling logs\n+-------------\n+\n+For enabling logs, use the following EAL parameter:\n+\n+.. code-block:: console\n+\n+ ./your_bbdev_application <EAL args> --log-level=la12xx:<level>\n+\n+Using ``bb.la12xx`` as log matching criteria, all Baseband PMD logs can be\n+enabled which are lower than logging ``level``.\ndiff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst\nindex b3224dc332..4e0b62debb 100644\n--- a/doc/guides/rel_notes/release_21_05.rst\n+++ b/doc/guides/rel_notes/release_21_05.rst\n@@ -236,6 +236,11 @@ New Features\n the hash function used in NICs to spread the traffic among the queues.\n It can be used to get predictable mapping of the flows.\n \n+* **Added NXP LA12xx baseband PMD.**\n+\n+ * Added a new baseband PMD driver for NXP LA12xx Software defined radio.\n+ * See the :doc:`../bbdevs/la12xx` for more details.\n+\n * **Updated testpmd.**\n \n * Added a command line option to configure forced speed for Ethernet port.\ndiff --git a/drivers/baseband/la12xx/bbdev_la12xx.c b/drivers/baseband/la12xx/bbdev_la12xx.c\nindex f26f3f2a08..1fdeca279e 100644\n--- a/drivers/baseband/la12xx/bbdev_la12xx.c\n+++ b/drivers/baseband/la12xx/bbdev_la12xx.c\n@@ -3,6 +3,11 @@\n */\n \n #include <string.h>\n+#include <unistd.h>\n+#include <fcntl.h>\n+#include <sys/ioctl.h>\n+#include <sys/mman.h>\n+#include <dirent.h>\n \n #include <rte_common.h>\n #include <rte_bus_vdev.h>\n@@ -31,11 +36,549 @@ struct bbdev_la12xx_params {\n #define LA12XX_VDEV_MODEM_ID_ARG\t\"modem\"\n #define LA12XX_MAX_MODEM 4\n \n+#define LA12XX_MAX_CORES\t4\n+#define LA12XX_LDPC_ENC_CORE\t0\n+#define LA12XX_LDPC_DEC_CORE\t1\n+\n+#define LA12XX_MAX_LDPC_ENC_QUEUES\t4\n+#define LA12XX_MAX_LDPC_DEC_QUEUES\t4\n+\n static const char * const bbdev_la12xx_valid_params[] = {\n \tLA12XX_MAX_NB_QUEUES_ARG,\n \tLA12XX_VDEV_MODEM_ID_ARG,\n };\n \n+static const struct rte_bbdev_op_cap bbdev_capabilities[] = {\n+\t{\n+\t\t.type = RTE_BBDEV_OP_LDPC_ENC,\n+\t\t.cap.ldpc_enc = {\n+\t\t\t.capability_flags =\n+\t\t\t\t\tRTE_BBDEV_LDPC_CRC_24A_ATTACH |\n+\t\t\t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH,\n+\t\t\t.num_buffers_src =\n+\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t\t.num_buffers_dst =\n+\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t}\n+\t},\n+\t{\n+\t\t.type = RTE_BBDEV_OP_LDPC_DEC,\n+\t\t.cap.ldpc_dec = {\n+\t\t\t.capability_flags =\n+\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK |\n+\t\t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION |\n+\t\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK |\n+\t\t\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_DROP,\n+\t\t\t.num_buffers_src =\n+\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t\t.num_buffers_hard_out =\n+\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n+\t\t}\n+\t},\n+\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static struct rte_bbdev_queue_conf default_queue_conf = {\n+\t.queue_size = MAX_CHANNEL_DEPTH,\n+};\n+\n+/* Get device info */\n+static void\n+la12xx_info_get(struct rte_bbdev *dev __rte_unused,\n+\t\tstruct rte_bbdev_driver_info *dev_info)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tdev_info->driver_name = RTE_STR(DRIVER_NAME);\n+\tdev_info->max_num_queues = LA12XX_MAX_QUEUES;\n+\tdev_info->queue_size_lim = MAX_CHANNEL_DEPTH;\n+\tdev_info->hardware_accelerated = true;\n+\tdev_info->max_dl_queue_priority = 0;\n+\tdev_info->max_ul_queue_priority = 0;\n+\tdev_info->default_queue_conf = default_queue_conf;\n+\tdev_info->capabilities = bbdev_capabilities;\n+\tdev_info->cpu_flag_reqs = NULL;\n+\tdev_info->min_alignment = 64;\n+\n+\trte_bbdev_log_debug(\"got device info from %u\", dev->data->dev_id);\n+}\n+\n+/* Release queue */\n+static int\n+la12xx_queue_release(struct rte_bbdev *dev, uint16_t q_id)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(q_id);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* TODO: Implement */\n+\n+\treturn 0;\n+}\n+\n+#define HUGEPG_OFFSET(A) \\\n+\t\t((uint64_t) ((unsigned long) (A) \\\n+\t\t- ((uint64_t)ipc_priv->hugepg_start.host_vaddr)))\n+\n+static int ipc_queue_configure(uint32_t channel_id,\n+\t\tipc_t instance, struct bbdev_la12xx_q_priv *q_priv)\n+{\n+\tipc_userspace_t *ipc_priv = (ipc_userspace_t *)instance;\n+\tipc_instance_t *ipc_instance = ipc_priv->instance;\n+\tipc_ch_t *ch;\n+\tvoid *vaddr;\n+\tuint32_t i = 0;\n+\tuint32_t msg_size = sizeof(struct bbdev_ipc_enqueue_op);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\trte_bbdev_log_debug(\"%x %p\", ipc_instance->initialized,\n+\t\tipc_priv->instance);\n+\tch = &(ipc_instance->ch_list[channel_id]);\n+\n+\trte_bbdev_log_debug(\"channel: %u, depth: %u, msg size: %u\",\n+\t\tchannel_id, q_priv->queue_size, msg_size);\n+\n+\t/* Start init of channel */\n+\tch->md.ring_size = rte_cpu_to_be_32(q_priv->queue_size);\n+\tch->md.pi = 0;\n+\tch->md.ci = 0;\n+\tch->md.msg_size = msg_size;\n+\tfor (i = 0; i < q_priv->queue_size; i++) {\n+\t\tvaddr = rte_malloc(NULL, msg_size, RTE_CACHE_LINE_SIZE);\n+\t\tif (!vaddr)\n+\t\t\treturn IPC_HOST_BUF_ALLOC_FAIL;\n+\t\t/* Only offset now */\n+\t\tch->bd_h[i].modem_ptr =\n+\t\t\trte_cpu_to_be_32(HUGEPG_OFFSET(vaddr));\n+\t\tch->bd_h[i].host_virt_l = lower_32_bits(vaddr);\n+\t\tch->bd_h[i].host_virt_h = upper_32_bits(vaddr);\n+\t\tq_priv->msg_ch_vaddr[i] = vaddr;\n+\t\t/* Not sure use of this len may be for CRC*/\n+\t\tch->bd_h[i].len = 0;\n+\t}\n+\tch->host_ipc_params =\n+\t\trte_cpu_to_be_32(HUGEPG_OFFSET(q_priv->host_params));\n+\n+\trte_bbdev_log_debug(\"Channel configured\");\n+\treturn IPC_SUCCESS;\n+}\n+\n+static int\n+la12xx_e200_queue_setup(struct rte_bbdev *dev,\n+\t\tstruct bbdev_la12xx_q_priv *q_priv)\n+{\n+\tstruct bbdev_la12xx_private *priv = dev->data->dev_private;\n+\tipc_userspace_t *ipc_priv = priv->ipc_priv;\n+\tstruct gul_hif *mhif;\n+\tipc_metadata_t *ipc_md;\n+\tipc_ch_t *ch;\n+\tint instance_id = 0, i;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tswitch (q_priv->op_type) {\n+\tcase RTE_BBDEV_OP_LDPC_ENC:\n+\t\tq_priv->la12xx_core_id = LA12XX_LDPC_ENC_CORE;\n+\t\tbreak;\n+\tcase RTE_BBDEV_OP_LDPC_DEC:\n+\t\tq_priv->la12xx_core_id = LA12XX_LDPC_DEC_CORE;\n+\t\tbreak;\n+\tdefault:\n+\t\trte_bbdev_log(ERR, \"Unsupported op type\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tmhif = (struct gul_hif *)ipc_priv->mhif_start.host_vaddr;\n+\t/* offset is from start of PEB */\n+\tipc_md = (ipc_metadata_t *)((uint64_t)ipc_priv->peb_start.host_vaddr +\n+\t\tmhif->ipc_regs.ipc_mdata_offset);\n+\tch = &ipc_md->instance_list[instance_id].ch_list[q_priv->q_id];\n+\n+\tif (q_priv->q_id < priv->num_valid_queues) {\n+\t\tipc_br_md_t *md = &(ch->md);\n+\n+\t\tq_priv->feca_blk_id = rte_cpu_to_be_32(ch->feca_blk_id);\n+\t\tq_priv->feca_blk_id_be32 = ch->feca_blk_id;\n+\t\tq_priv->host_pi = rte_be_to_cpu_32(md->pi);\n+\t\tq_priv->host_ci = rte_be_to_cpu_32(md->ci);\n+\t\tq_priv->host_params = (host_ipc_params_t *)\n+\t\t\t(rte_be_to_cpu_32(ch->host_ipc_params) +\n+\t\t\t((uint64_t)ipc_priv->hugepg_start.host_vaddr));\n+\n+\t\tfor (i = 0; i < q_priv->queue_size; i++) {\n+\t\t\tuint32_t h, l;\n+\n+\t\t\th = ch->bd_h[i].host_virt_h;\n+\t\t\tl = ch->bd_h[i].host_virt_l;\n+\t\t\tq_priv->msg_ch_vaddr[i] = (void *)join_32_bits(h, l);\n+\t\t}\n+\n+\t\trte_bbdev_log(WARNING,\n+\t\t\t\"Queue [%d] already configured, not configuring again\",\n+\t\t\tq_priv->q_id);\n+\t\treturn 0;\n+\t}\n+\n+\trte_bbdev_log_debug(\"setting up queue %d\", q_priv->q_id);\n+\n+\t/* Call ipc_configure_channel */\n+\tret = ipc_queue_configure(q_priv->q_id, ipc_priv, q_priv);\n+\tif (ret) {\n+\t\trte_bbdev_log(ERR, \"Unable to setup queue (%d) (err=%d)\",\n+\t\t q_priv->q_id, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Set queue properties for LA12xx device */\n+\tswitch (q_priv->op_type) {\n+\tcase RTE_BBDEV_OP_LDPC_ENC:\n+\t\tif (priv->num_ldpc_enc_queues >= LA12XX_MAX_LDPC_ENC_QUEUES) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"num_ldpc_enc_queues reached max value\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tch->la12xx_core_id =\n+\t\t\trte_cpu_to_be_32(LA12XX_LDPC_ENC_CORE);\n+\t\tch->feca_blk_id = rte_cpu_to_be_32(priv->num_ldpc_enc_queues++);\n+\t\tbreak;\n+\tcase RTE_BBDEV_OP_LDPC_DEC:\n+\t\tif (priv->num_ldpc_dec_queues >= LA12XX_MAX_LDPC_DEC_QUEUES) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"num_ldpc_dec_queues reached max value\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tch->la12xx_core_id =\n+\t\t\trte_cpu_to_be_32(LA12XX_LDPC_DEC_CORE);\n+\t\tch->feca_blk_id = rte_cpu_to_be_32(priv->num_ldpc_dec_queues++);\n+\t\tbreak;\n+\tdefault:\n+\t\trte_bbdev_log(ERR, \"Not supported op type\\n\");\n+\t\treturn -1;\n+\t}\n+\tch->op_type = rte_cpu_to_be_32(q_priv->op_type);\n+\tch->depth = rte_cpu_to_be_32(q_priv->queue_size);\n+\n+\t/* Store queue config here */\n+\tq_priv->feca_blk_id = rte_cpu_to_be_32(ch->feca_blk_id);\n+\tq_priv->feca_blk_id_be32 = ch->feca_blk_id;\n+\n+\treturn 0;\n+}\n+\n+/* Setup a queue */\n+static int\n+la12xx_queue_setup(struct rte_bbdev *dev, uint16_t q_id,\n+\t\tconst struct rte_bbdev_queue_conf *queue_conf)\n+{\n+\tstruct bbdev_la12xx_private *priv = dev->data->dev_private;\n+\tstruct rte_bbdev_queue_data *q_data;\n+\tstruct bbdev_la12xx_q_priv *q_priv;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Move to setup_queues callback */\n+\tq_data = &dev->data->queues[q_id];\n+\tq_data->queue_private = rte_zmalloc(NULL,\n+\t\tsizeof(struct bbdev_la12xx_q_priv), 0);\n+\tif (!q_data->queue_private) {\n+\t\trte_bbdev_log(ERR, \"Memory allocation failed for qpriv\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tq_priv = q_data->queue_private;\n+\tq_priv->q_id = q_id;\n+\tq_priv->bbdev_priv = dev->data->dev_private;\n+\tq_priv->queue_size = queue_conf->queue_size;\n+\tq_priv->op_type = queue_conf->op_type;\n+\n+\tret = la12xx_e200_queue_setup(dev, q_priv);\n+\tif (ret) {\n+\t\trte_bbdev_log(ERR, \"e200_queue_setup failed for qid: %d\",\n+\t\t\t\t q_id);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Store queue config here */\n+\tpriv->num_valid_queues++;\n+\n+\treturn 0;\n+}\n+\n+static int\n+la12xx_start(struct rte_bbdev *dev)\n+{\n+\tstruct bbdev_la12xx_private *priv = dev->data->dev_private;\n+\tipc_userspace_t *ipc_priv = priv->ipc_priv;\n+\tint ready = 0;\n+\tstruct gul_hif *hif_start;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\thif_start = (struct gul_hif *)ipc_priv->mhif_start.host_vaddr;\n+\n+\t/* Set Host Read bit */\n+\tSET_HIF_HOST_RDY(hif_start, HIF_HOST_READY_IPC_APP);\n+\n+\t/* Now wait for modem ready bit */\n+\twhile (!ready)\n+\t\tready = CHK_HIF_MOD_RDY(hif_start, HIF_MOD_READY_IPC_APP);\n+\n+\treturn 0;\n+}\n+\n+static const struct rte_bbdev_ops pmd_ops = {\n+\t.info_get = la12xx_info_get,\n+\t.queue_setup = la12xx_queue_setup,\n+\t.queue_release = la12xx_queue_release,\n+\t.start = la12xx_start\n+};\n+static struct hugepage_info *\n+get_hugepage_info(void)\n+{\n+\tstruct hugepage_info *hp_info;\n+\tstruct rte_memseg *mseg;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* TODO - find a better way */\n+\thp_info = rte_malloc(NULL, sizeof(struct hugepage_info), 0);\n+\tif (!hp_info) {\n+\t\trte_bbdev_log(ERR, \"Unable to allocate on local heap\");\n+\t\treturn NULL;\n+\t}\n+\n+\tmseg = rte_mem_virt2memseg(hp_info, NULL);\n+\thp_info->vaddr = mseg->addr;\n+\thp_info->paddr = rte_mem_virt2phy(mseg->addr);\n+\thp_info->len = mseg->len;\n+\n+\treturn hp_info;\n+}\n+\n+static int open_ipc_dev(int modem_id)\n+{\n+\tchar dev_initials[16], dev_path[PATH_MAX];\n+\tstruct dirent *entry;\n+\tint dev_ipc = 0;\n+\tDIR *dir;\n+\n+\tdir = opendir(\"/dev/\");\n+\tif (!dir) {\n+\t\trte_bbdev_log(ERR, \"Unable to open /dev/\");\n+\t\treturn -1;\n+\t}\n+\n+\tsprintf(dev_initials, \"gulipcgul%d\", modem_id);\n+\n+\twhile ((entry = readdir(dir)) != NULL) {\n+\t\tif (!strncmp(dev_initials, entry->d_name,\n+\t\t sizeof(dev_initials) - 1))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (!entry) {\n+\t\trte_bbdev_log(ERR, \"Error: No gulipcgul%d device\", modem_id);\n+\t\treturn -1;\n+\t}\n+\n+\tsprintf(dev_path, \"/dev/%s\", entry->d_name);\n+\tdev_ipc = open(dev_path, O_RDWR);\n+\tif (dev_ipc < 0) {\n+\t\trte_bbdev_log(ERR, \"Error: Cannot open %s\", dev_path);\n+\t\treturn -errno;\n+\t}\n+\n+\treturn dev_ipc;\n+}\n+\n+static int\n+setup_la12xx_dev(struct rte_bbdev *dev)\n+{\n+\tstruct bbdev_la12xx_private *priv = dev->data->dev_private;\n+\tipc_userspace_t *ipc_priv = priv->ipc_priv;\n+\tstruct hugepage_info *hp = NULL;\n+\tipc_channel_us_t *ipc_priv_ch = NULL;\n+\tint dev_ipc = 0, dev_mem = 0, i;\n+\tipc_metadata_t *ipc_md;\n+\tstruct gul_hif *mhif;\n+\tuint32_t phy_align = 0;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (!ipc_priv) {\n+\t\t/* TODO - get a better way */\n+\t\t/* Get the hugepage info against it */\n+\t\thp = get_hugepage_info();\n+\t\tif (!hp) {\n+\t\t\trte_bbdev_log(ERR, \"Unable to get hugepage info\");\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto err;\n+\t\t}\n+\n+\t\trte_bbdev_log_debug(\"%lx %p %lx\",\n+\t\t\t\thp->paddr, hp->vaddr, hp->len);\n+\n+\t\tipc_priv = rte_zmalloc(0, sizeof(ipc_userspace_t), 0);\n+\t\tif (ipc_priv == NULL) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"Unable to allocate memory for ipc priv\");\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto err;\n+\t\t}\n+\n+\t\tfor (i = 0; i < IPC_MAX_CHANNEL_COUNT; i++) {\n+\t\t\tipc_priv_ch = rte_zmalloc(0,\n+\t\t\t\tsizeof(ipc_channel_us_t), 0);\n+\t\t\tif (ipc_priv_ch == NULL) {\n+\t\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"Unable to allocate memory for channels\");\n+\t\t\t\tret = -ENOMEM;\n+\t\t\t}\n+\t\t\tipc_priv->channels[i] = ipc_priv_ch;\n+\t\t}\n+\n+\t\tdev_mem = open(\"/dev/mem\", O_RDWR);\n+\t\tif (dev_mem < 0) {\n+\t\t\trte_bbdev_log(ERR, \"Error: Cannot open /dev/mem\");\n+\t\t\tret = -errno;\n+\t\t\tgoto err;\n+\t\t}\n+\n+\t\tipc_priv->instance_id = 0;\n+\t\tipc_priv->dev_mem = dev_mem;\n+\n+\t\trte_bbdev_log_debug(\"hugepg input %lx %p %lx\",\n+\t\t\thp->paddr, hp->vaddr, hp->len);\n+\n+\t\tipc_priv->sys_map.hugepg_start.host_phys = hp->paddr;\n+\t\tipc_priv->sys_map.hugepg_start.size = hp->len;\n+\n+\t\tipc_priv->hugepg_start.host_phys = hp->paddr;\n+\t\tipc_priv->hugepg_start.host_vaddr = hp->vaddr;\n+\t\tipc_priv->hugepg_start.size = hp->len;\n+\n+\t\trte_free(hp);\n+\t}\n+\n+\tdev_ipc = open_ipc_dev(priv->modem_id);\n+\tif (dev_ipc < 0) {\n+\t\trte_bbdev_log(ERR, \"Error: open_ipc_dev failed\");\n+\t\tgoto err;\n+\t}\n+\tipc_priv->dev_ipc = dev_ipc;\n+\n+\tret = ioctl(ipc_priv->dev_ipc, IOCTL_GUL_IPC_GET_SYS_MAP,\n+\t\t &ipc_priv->sys_map);\n+\tif (ret) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\"IOCTL_GUL_IPC_GET_SYS_MAP ioctl failed\");\n+\t\tgoto err;\n+\t}\n+\n+\tphy_align = (ipc_priv->sys_map.mhif_start.host_phys % 0x1000);\n+\tipc_priv->mhif_start.host_vaddr =\n+\t\tmmap(0, ipc_priv->sys_map.mhif_start.size + phy_align,\n+\t\t (PROT_READ | PROT_WRITE), MAP_SHARED, ipc_priv->dev_mem,\n+\t\t (ipc_priv->sys_map.mhif_start.host_phys - phy_align));\n+\tif (ipc_priv->mhif_start.host_vaddr == MAP_FAILED) {\n+\t\trte_bbdev_log(ERR, \"MAP failed:\");\n+\t\tret = -errno;\n+\t\tgoto err;\n+\t}\n+\n+\tipc_priv->mhif_start.host_vaddr = (void *) ((uint64_t)\n+\t\t(ipc_priv->mhif_start.host_vaddr) + phy_align);\n+\n+\tphy_align = (ipc_priv->sys_map.peb_start.host_phys % 0x1000);\n+\tipc_priv->peb_start.host_vaddr =\n+\t\tmmap(0, ipc_priv->sys_map.peb_start.size + phy_align,\n+\t\t (PROT_READ | PROT_WRITE), MAP_SHARED, ipc_priv->dev_mem,\n+\t\t (ipc_priv->sys_map.peb_start.host_phys - phy_align));\n+\tif (ipc_priv->peb_start.host_vaddr == MAP_FAILED) {\n+\t\trte_bbdev_log(ERR, \"MAP failed:\");\n+\t\tret = -errno;\n+\t\tgoto err;\n+\t}\n+\n+\tipc_priv->peb_start.host_vaddr = (void *)((uint64_t)\n+\t\t(ipc_priv->peb_start.host_vaddr) + phy_align);\n+\n+\tphy_align = (ipc_priv->sys_map.modem_ccsrbar.host_phys % 0x1000);\n+\tipc_priv->modem_ccsrbar.host_vaddr =\n+\t\tmmap(0, ipc_priv->sys_map.modem_ccsrbar.size + phy_align,\n+\t\t (PROT_READ | PROT_WRITE), MAP_SHARED, ipc_priv->dev_mem,\n+\t\t (ipc_priv->sys_map.modem_ccsrbar.host_phys - phy_align));\n+\tif (ipc_priv->modem_ccsrbar.host_vaddr == MAP_FAILED) {\n+\t\trte_bbdev_log(ERR, \"MAP failed:\");\n+\t\tret = -errno;\n+\t\tgoto err;\n+\t}\n+\n+\tipc_priv->modem_ccsrbar.host_vaddr = (void *)((uint64_t)\n+\t\t(ipc_priv->modem_ccsrbar.host_vaddr) + phy_align);\n+\n+\tipc_priv->hugepg_start.modem_phys =\n+\t\tipc_priv->sys_map.hugepg_start.modem_phys;\n+\n+\tipc_priv->mhif_start.host_phys =\n+\t\tipc_priv->sys_map.mhif_start.host_phys;\n+\tipc_priv->mhif_start.size = ipc_priv->sys_map.mhif_start.size;\n+\tipc_priv->peb_start.host_phys = ipc_priv->sys_map.peb_start.host_phys;\n+\tipc_priv->peb_start.size = ipc_priv->sys_map.peb_start.size;\n+\n+\trte_bbdev_log(INFO, \"peb %lx %p %x\",\n+\t\t\tipc_priv->peb_start.host_phys,\n+\t\t\tipc_priv->peb_start.host_vaddr,\n+\t\t\tipc_priv->peb_start.size);\n+\trte_bbdev_log(INFO, \"hugepg %lx %p %x\",\n+\t\t\tipc_priv->hugepg_start.host_phys,\n+\t\t\tipc_priv->hugepg_start.host_vaddr,\n+\t\t\tipc_priv->hugepg_start.size);\n+\trte_bbdev_log(INFO, \"mhif %lx %p %x\",\n+\t\t\tipc_priv->mhif_start.host_phys,\n+\t\t\tipc_priv->mhif_start.host_vaddr,\n+\t\t\tipc_priv->mhif_start.size);\n+\tmhif = (struct gul_hif *)ipc_priv->mhif_start.host_vaddr;\n+\n+\t/* offset is from start of PEB */\n+\tipc_md = (ipc_metadata_t *)((uint64_t)ipc_priv->peb_start.host_vaddr +\n+\t\t\tmhif->ipc_regs.ipc_mdata_offset);\n+\n+\tif (sizeof(ipc_metadata_t) != mhif->ipc_regs.ipc_mdata_size) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\"ipc_metadata_t =%lx, mhif->ipc_regs.ipc_mdata_size=%x\",\n+\t\t\tsizeof(ipc_metadata_t), mhif->ipc_regs.ipc_mdata_size);\n+\t\trte_bbdev_log(ERR, \"--> mhif->ipc_regs.ipc_mdata_offset= %x\",\n+\t\t\tmhif->ipc_regs.ipc_mdata_offset);\n+\t\trte_bbdev_log(ERR, \"gul_hif size=%lx\", sizeof(struct gul_hif));\n+\t\treturn IPC_MD_SZ_MISS_MATCH;\n+\t}\n+\n+\tipc_priv->instance = (ipc_instance_t *)\n+\t\t(&ipc_md->instance_list[ipc_priv->instance_id]);\n+\n+\trte_bbdev_log_debug(\"finish host init\");\n+\n+\tpriv->ipc_priv = ipc_priv;\n+\n+\treturn 0;\n+\n+err:\n+\trte_free(hp);\n+\trte_free(ipc_priv);\n+\trte_free(ipc_priv_ch);\n+\tif (dev_mem)\n+\t\tclose(dev_mem);\n+\tif (dev_ipc)\n+\t\tclose(dev_ipc);\n+\n+\treturn ret;\n+}\n+\n static inline int\n parse_u16_arg(const char *key, const char *value, void *extra_args)\n {\n@@ -123,6 +666,7 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev,\n \tstruct rte_bbdev *bbdev;\n \tconst char *name = rte_vdev_device_name(vdev);\n \tstruct bbdev_la12xx_private *priv;\n+\tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -152,7 +696,13 @@ la12xx_bbdev_create(struct rte_vdev_device *vdev,\n \n \trte_bbdev_log(INFO, \"Setting Up %s: DevId=%d, ModemId=%d\",\n \t\t\t\tname, bbdev->data->dev_id, priv->modem_id);\n-\tbbdev->dev_ops = NULL;\n+\tret = setup_la12xx_dev(bbdev);\n+\tif (ret) {\n+\t\trte_bbdev_log(ERR, \"IPC Setup failed for %s\", name);\n+\t\trte_free(bbdev->data->dev_private);\n+\t\treturn ret;\n+\t}\n+\tbbdev->dev_ops = &pmd_ops;\n \tbbdev->device = &vdev->device;\n \tbbdev->data->socket_id = 0;\n \tbbdev->intr_handle = NULL;\ndiff --git a/drivers/baseband/la12xx/bbdev_la12xx.h b/drivers/baseband/la12xx/bbdev_la12xx.h\nindex 5228502331..49c37fe2fe 100644\n--- a/drivers/baseband/la12xx/bbdev_la12xx.h\n+++ b/drivers/baseband/la12xx/bbdev_la12xx.h\n@@ -5,16 +5,10 @@\n #ifndef __BBDEV_LA12XX_H__\n #define __BBDEV_LA12XX_H__\n \n-#define BBDEV_IPC_ENC_OP_TYPE\t1\n-#define BBDEV_IPC_DEC_OP_TYPE\t2\n-\n-#define MAX_LDPC_ENC_FECA_QUEUES\t4\n-#define MAX_LDPC_DEC_FECA_QUEUES\t4\n-\n #define MAX_CHANNEL_DEPTH 16\n /* private data structure */\n struct bbdev_la12xx_private {\n-\tvoid *ipc_priv;\n+\tipc_userspace_t *ipc_priv;\n \tuint8_t num_valid_queues;\n \tuint8_t max_nb_queues;\n \tuint8_t num_ldpc_enc_queues;\n@@ -52,5 +46,6 @@ struct bbdev_la12xx_q_priv {\n \n #define lower_32_bits(x) ((uint32_t)((uint64_t)x))\n #define upper_32_bits(x) ((uint32_t)(((uint64_t)(x) >> 16) >> 16))\n-\n+#define join_32_bits(upper, lower) \\\n+\t((size_t)(((uint64_t)(upper) << 32) | (uint32_t)(lower)))\n #endif\ndiff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h\nindex 9aa5562981..5f613fb087 100644\n--- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h\n+++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h\n@@ -4,9 +4,182 @@\n #ifndef __BBDEV_LA12XX_IPC_H__\n #define __BBDEV_LA12XX_IPC_H__\n \n+#define LA12XX_MAX_QUEUES 20\n+#define HOST_RX_QUEUEID_OFFSET LA12XX_MAX_QUEUES\n+\n+/** No. of max channel per instance */\n+#define IPC_MAX_CHANNEL_COUNT\t(64)\n+\n /** No. of max channel per instance */\n #define IPC_MAX_DEPTH\t(16)\n \n+/** No. of max IPC instance per modem */\n+#define IPC_MAX_INSTANCE_COUNT\t(1)\n+\n+/** Error codes */\n+#define IPC_SUCCESS\t\t(0) /** IPC operation success */\n+#define IPC_INPUT_INVALID\t(-1) /** Invalid input to API */\n+#define IPC_CH_INVALID\t\t(-2) /** Channel no is invalid */\n+#define IPC_INSTANCE_INVALID\t(-3) /** Instance no is invalid */\n+#define IPC_MEM_INVALID\t\t(-4) /** Insufficient memory */\n+#define IPC_CH_FULL\t\t(-5) /** Channel is full */\n+#define IPC_CH_EMPTY\t\t(-6) /** Channel is empty */\n+#define IPC_BL_EMPTY\t\t(-7) /** Free buffer list is empty */\n+#define IPC_BL_FULL\t\t(-8) /** Free buffer list is full */\n+#define IPC_HOST_BUF_ALLOC_FAIL\t(-9) /** DPDK malloc fail */\n+#define IPC_MD_SZ_MISS_MATCH\t(-10) /** META DATA size in mhif miss matched*/\n+#define IPC_MALLOC_FAIL\t\t(-11) /** system malloc fail */\n+#define IPC_IOCTL_FAIL\t\t(-12) /** IOCTL call failed */\n+#define IPC_MMAP_FAIL\t\t(-14) /** MMAP fail */\n+#define IPC_OPEN_FAIL\t\t(-15) /** OPEN fail */\n+#define IPC_EVENTFD_FAIL\t(-16) /** eventfd initialization failed */\n+#define IPC_NOT_IMPLEMENTED\t(-17) /** IPC feature is not implemented yet*/\n+\n+#define SET_HIF_HOST_RDY(hif, RDY_MASK) (hif->host_ready |= RDY_MASK)\n+#define CHK_HIF_MOD_RDY(hif, RDY_MASK) (hif->mod_ready & RDY_MASK)\n+\n+/* Host Ready bits */\n+#define HIF_HOST_READY_HOST_REGIONS\t(1 << 0)\n+#define HIF_HOST_READY_IPC_LIB\t\t(1 << 12)\n+#define HIF_HOST_READY_IPC_APP\t\t(1 << 13)\n+#define HIF_HOST_READY_FECA\t\t(1 << 14)\n+\n+/* Modem Ready bits */\n+#define HIF_MOD_READY_IPC_LIB\t\t(1 << 5)\n+#define HIF_MOD_READY_IPC_APP\t\t(1 << 6)\n+#define HIF_MOD_READY_FECA\t\t(1 << 7)\n+\n+typedef void *ipc_t;\n+\n+struct ipc_msg {\n+\tint chid;\n+\tvoid *addr;\n+\tuint32_t len;\n+\tuint8_t flags;\n+};\n+\n+typedef struct {\n+\tuint64_t host_phys;\n+\tuint32_t modem_phys;\n+\tvoid *host_vaddr;\n+\tuint32_t size;\n+} mem_range_t;\n+\n+#define GUL_IPC_MAGIC\t'R'\n+\n+#define IOCTL_GUL_IPC_GET_SYS_MAP _IOW(GUL_IPC_MAGIC, 1, struct ipc_msg *)\n+#define IOCTL_GUL_IPC_CHANNEL_REGISTER _IOWR(GUL_IPC_MAGIC, 4, struct ipc_msg *)\n+#define IOCTL_GUL_IPC_CHANNEL_DEREGISTER \\\n+\t_IOWR(GUL_IPC_MAGIC, 5, struct ipc_msg *)\n+#define IOCTL_GUL_IPC_CHANNEL_RAISE_INTERRUPT _IOW(GUL_IPC_MAGIC, 6, int *)\n+\n+/** buffer ring common metadata */\n+typedef struct ipc_bd_ring_md {\n+\tvolatile uint32_t pi;\t\t/**< Producer index and flag (MSB)\n+\t\t\t\t\t * which flip for each Ring wrapping\n+\t\t\t\t\t */\n+\tvolatile uint32_t ci;\t\t/**< Consumer index and flag (MSB)\n+\t\t\t\t\t * which flip for each Ring wrapping\n+\t\t\t\t\t */\n+\tuint32_t ring_size;\t/**< depth (Used to roll-over pi/ci) */\n+\tuint32_t msg_size;\t/**< Size of the each buffer */\n+} __rte_packed ipc_br_md_t;\n+\n+/** IPC buffer descriptor */\n+typedef struct ipc_buffer_desc {\n+\tunion {\n+\t\tuint64_t host_virt;\t/**< msg's host virtual address */\n+\t\tstruct {\n+\t\t\tuint32_t host_virt_l;\n+\t\t\tuint32_t host_virt_h;\n+\t\t};\n+\t};\n+\tuint32_t modem_ptr;\t/**< msg's modem physical address */\n+\tuint32_t len;\t\t/**< msg len */\n+} __rte_packed ipc_bd_t;\n+\n+typedef struct ipc_channel {\n+\tuint32_t ch_id;\t\t/**< Channel id */\n+\tipc_br_md_t md;\t\t\t/**< Metadata for BD ring */\n+\tipc_bd_t bd_h[IPC_MAX_DEPTH];\t/**< Buffer Descriptor on Host */\n+\tipc_bd_t bd_m[IPC_MAX_DEPTH];\t/**< Buffer Descriptor on Modem */\n+\tuint32_t op_type;\t\t/**< Type of the BBDEV operation\n+\t\t\t\t\t * supported on this channel\n+\t\t\t\t\t */\n+\tuint32_t depth;\t\t\t/**< Channel depth */\n+\tuint32_t feca_blk_id;\t/**< FECA Transport Block ID for processing */\n+\tuint32_t la12xx_core_id;/**< LA12xx core ID on which this will be\n+\t\t\t\t * scheduled\n+\t\t\t\t */\n+\tuint32_t feca_input_circ_size;\t/**< FECA transport block input\n+\t\t\t\t\t * circular buffer size\n+\t\t\t\t\t */\n+\tuint32_t host_ipc_params;\t/**< Address for host IPC parameters */\n+} __rte_packed ipc_ch_t;\n+\n+typedef struct ipc_instance {\n+\tuint32_t instance_id;\t\t/**< instance id, use to init this\n+\t\t\t\t\t * instance by ipc_init API\n+\t\t\t\t\t */\n+\tuint32_t initialized;\t\t/**< Set in ipc_init */\n+\tipc_ch_t ch_list[IPC_MAX_CHANNEL_COUNT];\n+\t\t/**< Channel descriptors in this instance */\n+} __rte_packed ipc_instance_t;\n+\n+typedef struct ipc_metadata {\n+\tuint32_t ipc_host_signature; /**< IPC host signature, Set by host/L2 */\n+\tuint32_t ipc_geul_signature; /**< IPC geul signature, Set by modem */\n+\tipc_instance_t instance_list[IPC_MAX_INSTANCE_COUNT];\n+} __rte_packed ipc_metadata_t;\n+\n+typedef struct ipc_channel_us_priv {\n+\tint32_t\t\teventfd;\n+\tuint32_t\tchannel_id;\n+\t/* In flight packets status for buffer list. */\n+\tuint8_t\t\tbufs_inflight[IPC_MAX_DEPTH];\n+} ipc_channel_us_t;\n+\n+typedef struct {\n+\tuint64_t host_phys;\n+\tuint32_t modem_phys;\n+\tuint32_t size;\n+} mem_strt_addr_t;\n+\n+typedef struct {\n+\tmem_strt_addr_t modem_ccsrbar;\n+\tmem_strt_addr_t peb_start; /* PEB meta data */\n+\tmem_strt_addr_t mhif_start; /* MHIF meta daat */\n+\tmem_strt_addr_t hugepg_start; /* Modem to access hugepage */\n+} sys_map_t;\n+\n+typedef struct ipc_priv_t {\n+\tint instance_id;\n+\tint dev_ipc;\n+\tint dev_mem;\n+\tsys_map_t sys_map;\n+\tmem_range_t modem_ccsrbar;\n+\tmem_range_t peb_start;\n+\tmem_range_t mhif_start;\n+\tmem_range_t hugepg_start;\n+\tipc_channel_us_t *channels[IPC_MAX_CHANNEL_COUNT];\n+\tipc_instance_t\t*instance;\n+\tipc_instance_t\t*instance_bk;\n+} ipc_userspace_t;\n+\n+/** Structure specifying enqueue operation (enqueue at LA1224) */\n+struct bbdev_ipc_enqueue_op {\n+\t/** Status of operation that was performed */\n+\tint32_t status;\n+\t/** CRC Status of SD operation that was performed */\n+\tint32_t crc_stat_addr;\n+\t/** HARQ Output buffer memory length for Shared Decode.\n+\t * Filled by LA12xx.\n+\t */\n+\tuint32_t out_len;\n+\t/** Reserved (for 8 byte alignment) */\n+\tuint32_t rsvd;\n+};\n+\n /* This shared memory would be on the host side which have copy of some\n * of the parameters which are also part of Shared BD ring. Read access\n * of these parameters from the host side would not be over PCI.\n@@ -14,7 +187,21 @@\n typedef struct host_ipc_params {\n \tvolatile uint32_t pi;\n \tvolatile uint32_t ci;\n-\tvolatile uint32_t modem_ptr[IPC_MAX_DEPTH];\n+\tvolatile uint32_t bd_m_modem_ptr[IPC_MAX_DEPTH];\n } __rte_packed host_ipc_params_t;\n \n+struct hif_ipc_regs {\n+\tuint32_t ipc_mdata_offset;\n+\tuint32_t ipc_mdata_size;\n+} __rte_packed;\n+\n+struct gul_hif {\n+\tuint32_t ver;\n+\tuint32_t hif_ver;\n+\tuint32_t status;\n+\tvolatile uint32_t host_ready;\n+\tvolatile uint32_t mod_ready;\n+\tstruct hif_ipc_regs ipc_regs;\n+} __rte_packed;\n+\n #endif\n", "prefixes": [ "v4", "5/8" ] }