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GET /api/patches/92097/?format=api
{ "id": 92097, "url": "http://patches.dpdk.org/api/patches/92097/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210424060337.2824837-3-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210424060337.2824837-3-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210424060337.2824837-3-qi.z.zhang@intel.com", "date": "2021-04-24T06:03:35", "name": "[2/4] common/iavf: add enumeration for the rxdid format", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5188f985a754363b05fe04948f340c0e5f7250f6", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210424060337.2824837-3-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 16641, "url": "http://patches.dpdk.org/api/series/16641/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16641", "date": "2021-04-24T06:03:33", "name": "common/iavf: update virtchnl", "version": 1, "mbox": "http://patches.dpdk.org/series/16641/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92097/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92097/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E7974A0547;\n\tSat, 24 Apr 2021 08:00:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E5C2A4111E;\n\tSat, 24 Apr 2021 08:00:01 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 4C62A41112\n for <dev@dpdk.org>; Sat, 24 Apr 2021 08:00:00 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Apr 2021 22:59:59 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 23 Apr 2021 22:59:58 -0700" ], "IronPort-SDR": [ "\n rqEr+Z1T+vjdRuY73iZk89AOjZGlDsR3UOZ+CX2sGpahQ8ChwPsVV4JXZN08jTJCa/AZBFEPdU\n zaSYgtsZ9LxA==", "\n J+eEhKr5B3TzimJI5K8G+6X3U5yLDzyxAlhul41a/t2HjYnTK2DFXI4hEhMk9UQhORQJD/XPZF\n E/YnucT29bdQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9963\"; a=\"257470324\"", "E=Sophos;i=\"5.82,247,1613462400\"; d=\"scan'208\";a=\"257470324\"", "E=Sophos;i=\"5.82,247,1613462400\"; d=\"scan'208\";a=\"421999419\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "beilei.xing@intel.com", "Cc": "haiyue.wang@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Sat, 24 Apr 2021 14:03:35 +0800", "Message-Id": "<20210424060337.2824837-3-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210424060337.2824837-1-qi.z.zhang@intel.com>", "References": "<20210424060337.2824837-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 2/4] common/iavf: add enumeration for the rxdid\n format", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Support for allowing VFs to negotiate the descriptor format was added\npreviously.\n\nThis support requires that the VF specify which descriptor format to use\nwhen requesting Rx queues. The VF is supposed to request the set of\nsupported formats via the new VIRTCHNL_OP_GET_SUPPORTED_RXDIDS, and then\nset one of the supported formats in the rxdid field of the\nvirtchnl_rxq_info structure.\n\nThe virtchnl.h header does not provide an enumeration of the format\nvalues. The existing implementations in the PF directly use the values\nfrom the DDP package.\n\nMake the formats explicit by defining an enumeration of the RXDIDs.\nProvide an enumeration for the values as well as the bit positions as\nreturned by the supported_rxdids data from the\nVIRTCHNL_OP_GET_SUPPORTED_RXDIDS.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/common/iavf/virtchnl.h | 55 +++++++++++++++++++++++++++++++++-\n 1 file changed, 54 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h\nindex c68128f773..d794f11c01 100644\n--- a/drivers/common/iavf/virtchnl.h\n+++ b/drivers/common/iavf/virtchnl.h\n@@ -432,6 +432,54 @@ struct virtchnl_txq_info {\n \n VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_txq_info);\n \n+/* RX descriptor IDs (range from 0 to 63) */\n+enum virtchnl_rx_desc_ids {\n+\tVIRTCHNL_RXDID_0_16B_BASE\t\t= 0,\n+\t/* 32B_BASE and FLEX_SPLITQ share desc ids as default descriptors\n+\t * because they can be differentiated based on queue model; e.g. single\n+\t * queue model can only use 32B_BASE and split queue model can only use\n+\t * FLEX_SPLITQ. Having these as 1 allows them to be used as default\n+\t * descriptors without negotiation.\n+\t */\n+\tVIRTCHNL_RXDID_1_32B_BASE\t\t= 1,\n+\tVIRTCHNL_RXDID_1_FLEX_SPLITQ\t\t= 1,\n+\tVIRTCHNL_RXDID_2_FLEX_SQ_NIC\t\t= 2,\n+\tVIRTCHNL_RXDID_3_FLEX_SQ_SW\t\t= 3,\n+\tVIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB\t= 4,\n+\tVIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL\t= 5,\n+\tVIRTCHNL_RXDID_6_FLEX_SQ_NIC_2\t\t= 6,\n+\tVIRTCHNL_RXDID_7_HW_RSVD\t\t= 7,\n+\t/* 9 through 15 are reserved */\n+\tVIRTCHNL_RXDID_16_COMMS_GENERIC\t\t= 16,\n+\tVIRTCHNL_RXDID_17_COMMS_AUX_VLAN\t= 17,\n+\tVIRTCHNL_RXDID_18_COMMS_AUX_IPV4\t= 18,\n+\tVIRTCHNL_RXDID_19_COMMS_AUX_IPV6\t= 19,\n+\tVIRTCHNL_RXDID_20_COMMS_AUX_FLOW\t= 20,\n+\tVIRTCHNL_RXDID_21_COMMS_AUX_TCP\t\t= 21,\n+\t/* 22 through 63 are reserved */\n+};\n+\n+/* RX descriptor ID bitmasks */\n+enum virtchnl_rx_desc_id_bitmasks {\n+\tVIRTCHNL_RXDID_0_16B_BASE_M\t\t= BIT(VIRTCHNL_RXDID_0_16B_BASE),\n+\tVIRTCHNL_RXDID_1_32B_BASE_M\t\t= BIT(VIRTCHNL_RXDID_1_32B_BASE),\n+\tVIRTCHNL_RXDID_1_FLEX_SPLITQ_M\t\t= BIT(VIRTCHNL_RXDID_1_FLEX_SPLITQ),\n+\tVIRTCHNL_RXDID_2_FLEX_SQ_NIC_M\t\t= BIT(VIRTCHNL_RXDID_2_FLEX_SQ_NIC),\n+\tVIRTCHNL_RXDID_3_FLEX_SQ_SW_M\t\t= BIT(VIRTCHNL_RXDID_3_FLEX_SQ_SW),\n+\tVIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB_M\t= BIT(VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB),\n+\tVIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL_M\t= BIT(VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL),\n+\tVIRTCHNL_RXDID_6_FLEX_SQ_NIC_2_M\t= BIT(VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2),\n+\tVIRTCHNL_RXDID_7_HW_RSVD_M\t\t= BIT(VIRTCHNL_RXDID_7_HW_RSVD),\n+\t/* 9 through 15 are reserved */\n+\tVIRTCHNL_RXDID_16_COMMS_GENERIC_M\t= BIT(VIRTCHNL_RXDID_16_COMMS_GENERIC),\n+\tVIRTCHNL_RXDID_17_COMMS_AUX_VLAN_M\t= BIT(VIRTCHNL_RXDID_17_COMMS_AUX_VLAN),\n+\tVIRTCHNL_RXDID_18_COMMS_AUX_IPV4_M\t= BIT(VIRTCHNL_RXDID_18_COMMS_AUX_IPV4),\n+\tVIRTCHNL_RXDID_19_COMMS_AUX_IPV6_M\t= BIT(VIRTCHNL_RXDID_19_COMMS_AUX_IPV6),\n+\tVIRTCHNL_RXDID_20_COMMS_AUX_FLOW_M\t= BIT(VIRTCHNL_RXDID_20_COMMS_AUX_FLOW),\n+\tVIRTCHNL_RXDID_21_COMMS_AUX_TCP_M\t= BIT(VIRTCHNL_RXDID_21_COMMS_AUX_TCP),\n+\t/* 22 through 63 are reserved */\n+};\n+\n /* VIRTCHNL_OP_CONFIG_RX_QUEUE\n * VF sends this message to set up parameters for one RX queue.\n * External data buffer contains one instance of virtchnl_rxq_info.\n@@ -454,7 +502,11 @@ struct virtchnl_rxq_info {\n \tu32 databuffer_size;\n \tu32 max_pkt_size;\n \tu8 crc_disable;\n-\t/* only used when VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC is supported */\n+\t/* see enum virtchnl_rx_desc_ids;\n+\t * only used when VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC is supported. Note\n+\t * that when the offload is not supported, the descriptor format aligns\n+\t * with VIRTCHNL_RXDID_1_32B_BASE.\n+\t */\n \tu8 rxdid;\n \tu8 pad1[2];\n \tu64 dma_ring_addr;\n@@ -1294,6 +1346,7 @@ struct virtchnl_dcf_vlan_offload {\n VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_dcf_vlan_offload);\n \n struct virtchnl_supported_rxdids {\n+\t/* see enum virtchnl_rx_desc_id_bitmasks */\n \tu64 supported_rxdids;\n };\n \n", "prefixes": [ "2/4" ] }