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GET /api/patches/91871/?format=api
{ "id": 91871, "url": "http://patches.dpdk.org/api/patches/91871/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1618916122-181792-15-git-send-email-jiaweiw@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618916122-181792-15-git-send-email-jiaweiw@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618916122-181792-15-git-send-email-jiaweiw@nvidia.com", "date": "2021-04-20T10:55:21", "name": "[v6,14/15] net/mlx5: allow multiple flow tables on the same level", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fc4a27fabd826baa6563b3e3510b6a1c2bb9f93a", "submitter": { "id": 1939, "url": "http://patches.dpdk.org/api/people/1939/?format=api", "name": "Jiawei Wang", "email": "jiaweiw@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1618916122-181792-15-git-send-email-jiaweiw@nvidia.com/mbox/", "series": [ { "id": 16520, "url": "http://patches.dpdk.org/api/series/16520/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16520", "date": "2021-04-20T10:55:12", "name": "Add ASO meter support in MLX5 PMD", "version": 6, "mbox": "http://patches.dpdk.org/series/16520/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/91871/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/91871/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4FBC1A0548;\n\tTue, 20 Apr 2021 12:56:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 82A0141781;\n\tTue, 20 Apr 2021 12:55:43 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id AE2FA4174E\n for <dev@dpdk.org>; Tue, 20 Apr 2021 12:55:30 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n jiaweiw@nvidia.com) with SMTP; 20 Apr 2021 13:55:26 +0300", "from nvidia.com (gen-l-vrt-281.mtl.labs.mlnx [10.237.44.1])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13KAtMS2009943;\n Tue, 20 Apr 2021 13:55:26 +0300" ], "From": "Jiawei Wang <jiaweiw@nvidia.com>", "To": "matan@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n ferruh.yigit@intel.com, thomas@monjalon.net,\n Shahaf Shuler <shahafs@nvidia.com>", "Cc": "dev@dpdk.org, rasland@nvidia.com, asafp@nvidia.com,\n Li Zhang <lizh@nvidia.com>", "Date": "Tue, 20 Apr 2021 13:55:21 +0300", "Message-Id": "<1618916122-181792-15-git-send-email-jiaweiw@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1618916122-181792-1-git-send-email-jiaweiw@nvidia.com>", "References": "<20210331073632.1443011-1-lizh@nvidia.com>\n <1618916122-181792-1-git-send-email-jiaweiw@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v6 14/15] net/mlx5: allow multiple flow tables on\n the same level", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Li Zhang <lizh@nvidia.com>\n\nThe driver devices support creation of multiple flow tables.\nJump action can be used in order to move the packet steering\nto different flow table.\nTable 0 is always the root table for packet steering.\n\nJumping between tables may cause endless loops in steering mechanism,\nthat's why each table has level attribute,\nthe driver sub-system may not allow jumping to table with\nequal or lower level than the current table.\n\nCurrently, in the driver, the table ID and level are always identical.\n\nAllow multiple flow table creation with the same level attribute.\n\nThis patch adds the table id in flow table data entry, while\nallocates the flow table, if the table level is same but the\ndifferent table id, the new table will be allocated with new\ntable object id. It supports 4M multiple flow tables on the\nsame level.\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 9 +++--\n drivers/net/mlx5/mlx5.h | 10 +++--\n drivers/net/mlx5/mlx5_flow.c | 17 ++++++---\n drivers/net/mlx5/mlx5_flow.h | 12 ++++--\n drivers/net/mlx5/mlx5_flow_dv.c | 84 +++++++++++++++++++++++------------------\n 5 files changed, 79 insertions(+), 53 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex e5ffb8f..7e13b38 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1271,9 +1271,12 @@ struct mlx5_dev_ctx_shared *\n \t * because DV expect to see them even if they cannot be created by\n \t * RDMA-CORE.\n \t */\n-\tif (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||\n-\t !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||\n-\t !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {\n+\tif (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,\n+\t\tNULL, 0, 1, 0, &error) ||\n+\t !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,\n+\t\tNULL, 0, 1, 0, &error) ||\n+\t !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,\n+\t\tNULL, 0, 1, 0, &error)) {\n \t\terr = ENOMEM;\n \t\tgoto error;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex b2eb851..55ff17a 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -779,10 +779,12 @@ struct mlx5_aso_mtr_pools_mng {\n union mlx5_flow_tbl_key {\n \tstruct {\n \t\t/* Table ID should be at the lowest address. */\n-\t\tuint32_t table_id;\t/**< ID of the table. */\n-\t\tuint16_t dummy;\t\t/**< Dummy table for DV API. */\n-\t\tuint8_t domain;\t\t/**< 1 - FDB, 0 - NIC TX/RX. */\n-\t\tuint8_t direction;\t/**< 1 - egress, 0 - ingress. */\n+\t\tuint32_t level;\t/**< Level of the table. */\n+\t\tuint32_t id:22;\t/**< ID of the table. */\n+\t\tuint32_t dummy:1;\t/**< Dummy table for DV API. */\n+\t\tuint32_t is_fdb:1;\t/**< 1 - FDB, 0 - NIC TX/RX. */\n+\t\tuint32_t is_egress:1;\t/**< 1 - egress, 0 - ingress. */\n+\t\tuint32_t reserved:7;\t/**< must be zero for comparison. */\n \t};\n \tuint64_t v64;\t\t\t/**< full 64bits value of key */\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex cf93ab0..bed8f31 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -4342,6 +4342,9 @@ struct mlx5_hlist_entry *\n \t\tdev_flow->handle->mark = 1;\n \tif (sub_flow)\n \t\t*sub_flow = dev_flow;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tdev_flow->dv.table_id = flow_split_info->table_id;\n+#endif\n \treturn flow_drv_translate(dev, dev_flow, attr, items, actions, error);\n }\n \n@@ -5497,8 +5500,7 @@ struct mlx5_hlist_entry *\n \t\t\t\t\t\tstruct mlx5_flow_tbl_data_entry,\n \t\t\t\t\t\ttbl);\n \t\t\tsfx_attr.group = sfx_attr.transfer ?\n-\t\t\t\t\t\t(sfx_tbl_data->table_id - 1) :\n-\t\t\t\t\t\tsfx_tbl_data->table_id;\n+\t\t\t(sfx_tbl_data->level - 1) : sfx_tbl_data->level;\n \t\t} else {\n \t\t\tMLX5_ASSERT(attr->transfer);\n \t\t\tsfx_attr.group = jump_table;\n@@ -5698,7 +5700,8 @@ struct mlx5_hlist_entry *\n \t\t.skip_scale = 0,\n \t\t.flow_idx = 0,\n \t\t.prefix_mark = 0,\n-\t\t.prefix_layers = 0\n+\t\t.prefix_layers = 0,\n+\t\t.table_id = 0\n \t};\n \tint ret;\n \n@@ -7784,10 +7787,12 @@ int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains)\n \tunion tunnel_offload_mark mbits = { .val = mark };\n \tunion mlx5_flow_tbl_key table_key = {\n \t\t{\n-\t\t\t.table_id = tunnel_id_to_flow_tbl(mbits.table_id),\n+\t\t\t.level = tunnel_id_to_flow_tbl(mbits.table_id),\n+\t\t\t.id = 0,\n+\t\t\t.reserved = 0,\n \t\t\t.dummy = 0,\n-\t\t\t.domain = !!mbits.transfer,\n-\t\t\t.direction = 0,\n+\t\t\t.is_fdb = !!mbits.transfer,\n+\t\t\t.is_egress = 0,\n \t\t}\n \t};\n \the = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL);\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 81cf1b5..1a74b17 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -564,8 +564,9 @@ struct mlx5_flow_tbl_data_entry {\n \tuint32_t is_egress:1; /**< Egress table. */\n \tuint32_t is_transfer:1; /**< Transfer table. */\n \tuint32_t dummy:1; /**< DR table. */\n-\tuint32_t reserve:27; /**< Reserved to future using. */\n-\tuint32_t table_id; /**< Table ID. */\n+\tuint32_t id:22; /**< Table ID. */\n+\tuint32_t reserve:5; /**< Reserved to future using. */\n+\tuint32_t level; /**< Table level. */\n };\n \n /* Sub rdma-core actions list. */\n@@ -699,6 +700,7 @@ struct mlx5_flow_handle {\n /** Device flow structure only for DV flow creation. */\n struct mlx5_flow_dv_workspace {\n \tuint32_t group; /**< The group index. */\n+\tuint32_t table_id; /**< Flow table identifier. */\n \tuint8_t transfer; /**< 1 if the flow is E-Switch flow. */\n \tint actions_n; /**< number of actions. */\n \tvoid *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */\n@@ -1059,6 +1061,7 @@ struct mlx5_flow_split_info {\n \tuint32_t flow_idx; /**< This memory pool index to the flow. */\n \tuint32_t prefix_mark; /**< Prefix subflow mark flag. */\n \tuint64_t prefix_layers; /**< Prefix subflow layers. */\n+\tuint32_t table_id; /**< Flow table identifier. */\n };\n \n typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,\n@@ -1410,9 +1413,10 @@ int flow_dv_tbl_match_cb(struct mlx5_hlist *list,\n void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,\n \t\t\t struct mlx5_hlist_entry *entry);\n struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n-\t\tuint32_t table_id, uint8_t egress, uint8_t transfer,\n+\t\tuint32_t table_level, uint8_t egress, uint8_t transfer,\n \t\tbool external, const struct mlx5_flow_tunnel *tunnel,\n-\t\tuint32_t group_id, uint8_t dummy, struct rte_flow_error *error);\n+\t\tuint32_t group_id, uint8_t dummy,\n+\t\tuint32_t table_id, struct rte_flow_error *error);\n \n struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,\n \t\t\t\t\t uint64_t key, void *cb_ctx);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex a649339..ffd9f63 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -9373,20 +9373,21 @@ struct mlx5_hlist_entry *\n \ttbl_data->group_id = tt_prm->group_id;\n \ttbl_data->external = !!tt_prm->external;\n \ttbl_data->tunnel_offload = is_tunnel_offload_active(dev);\n-\ttbl_data->is_egress = !!key.direction;\n-\ttbl_data->is_transfer = !!key.domain;\n+\ttbl_data->is_egress = !!key.is_egress;\n+\ttbl_data->is_transfer = !!key.is_fdb;\n \ttbl_data->dummy = !!key.dummy;\n-\ttbl_data->table_id = key.table_id;\n+\ttbl_data->level = key.level;\n+\ttbl_data->id = key.id;\n \ttbl = &tbl_data->tbl;\n \tif (key.dummy)\n \t\treturn &tbl_data->entry;\n-\tif (key.domain)\n+\tif (key.is_fdb)\n \t\tdomain = sh->fdb_domain;\n-\telse if (key.direction)\n+\telse if (key.is_egress)\n \t\tdomain = sh->tx_domain;\n \telse\n \t\tdomain = sh->rx_domain;\n-\tret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);\n+\tret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);\n \tif (ret) {\n \t\trte_flow_error_set(error, ENOMEM,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -9394,7 +9395,7 @@ struct mlx5_hlist_entry *\n \t\tmlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);\n \t\treturn NULL;\n \t}\n-\tif (key.table_id) {\n+\tif (key.level != 0) {\n \t\tret = mlx5_flow_os_create_flow_action_dest_flow_tbl\n \t\t\t\t\t(tbl->obj, &tbl_data->jump.action);\n \t\tif (ret) {\n@@ -9407,9 +9408,9 @@ struct mlx5_hlist_entry *\n \t\t\treturn NULL;\n \t\t}\n \t}\n-\tMKSTR(matcher_name, \"%s_%s_%u_matcher_cache\",\n-\t key.domain ? \"FDB\" : \"NIC\", key.direction ? \"egress\" : \"ingress\",\n-\t key.table_id);\n+\tMKSTR(matcher_name, \"%s_%s_%u_%u_matcher_cache\",\n+\t key.is_fdb ? \"FDB\" : \"NIC\", key.is_egress ? \"egress\" : \"ingress\",\n+\t key.level, key.id);\n \tmlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,\n \t\t\t flow_dv_matcher_create_cb,\n \t\t\t flow_dv_matcher_match_cb,\n@@ -9426,10 +9427,11 @@ struct mlx5_hlist_entry *\n \t\tcontainer_of(entry, struct mlx5_flow_tbl_data_entry, entry);\n \tunion mlx5_flow_tbl_key key = { .v64 = key64 };\n \n-\treturn tbl_data->table_id != key.table_id ||\n+\treturn tbl_data->level != key.level ||\n+\t tbl_data->id != key.id ||\n \t tbl_data->dummy != key.dummy ||\n-\t tbl_data->is_transfer != key.domain ||\n-\t tbl_data->is_egress != key.direction;\n+\t tbl_data->is_transfer != !!key.is_fdb ||\n+\t tbl_data->is_egress != !!key.is_egress;\n }\n \n /**\n@@ -9437,14 +9439,16 @@ struct mlx5_hlist_entry *\n *\n * @param[in, out] dev\n * Pointer to rte_eth_dev structure.\n- * @param[in] table_id\n- * Table id to use.\n+ * @param[in] table_level\n+ * Table level to use.\n * @param[in] egress\n * Direction of the table.\n * @param[in] transfer\n * E-Switch or NIC flow.\n * @param[in] dummy\n * Dummy entry for dv API.\n+ * @param[in] table_id\n+ * Table id to use.\n * @param[out] error\n * pointer to error structure.\n *\n@@ -9453,20 +9457,23 @@ struct mlx5_hlist_entry *\n */\n struct mlx5_flow_tbl_resource *\n flow_dv_tbl_resource_get(struct rte_eth_dev *dev,\n-\t\t\t uint32_t table_id, uint8_t egress,\n+\t\t\t uint32_t table_level, uint8_t egress,\n \t\t\t uint8_t transfer,\n \t\t\t bool external,\n \t\t\t const struct mlx5_flow_tunnel *tunnel,\n \t\t\t uint32_t group_id, uint8_t dummy,\n+\t\t\t uint32_t table_id,\n \t\t\t struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tunion mlx5_flow_tbl_key table_key = {\n \t\t{\n-\t\t\t.table_id = table_id,\n-\t\t\t.dummy = dummy,\n-\t\t\t.domain = !!transfer,\n-\t\t\t.direction = !!egress,\n+\t\t\t.level = table_level,\n+\t\t\t.id = table_id,\n+\t\t\t.reserved = 0,\n+\t\t\t.dummy = !!dummy,\n+\t\t\t.is_fdb = !!transfer,\n+\t\t\t.is_egress = !!egress,\n \t\t}\n \t};\n \tstruct mlx5_flow_tbl_tunnel_prm tt_prm = {\n@@ -9489,8 +9496,10 @@ struct mlx5_flow_tbl_resource *\n \t\t\t\t \"cannot get table\");\n \t\treturn NULL;\n \t}\n-\tDRV_LOG(DEBUG, \"Table_id %u tunnel %u group %u registered.\",\n-\t\ttable_id, tunnel ? tunnel->tunnel_id : 0, group_id);\n+\tDRV_LOG(DEBUG, \"table_level %u table_id %u \"\n+\t\t\"tunnel %u group %u registered.\",\n+\t\ttable_level, table_id,\n+\t\ttunnel ? tunnel->tunnel_id : 0, group_id);\n \ttbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);\n \treturn &tbl_data->tbl;\n }\n@@ -9517,7 +9526,7 @@ struct mlx5_flow_tbl_resource *\n \t\t\t\t\ttbl_data->tunnel->tunnel_id : 0,\n \t\t\t.group = tbl_data->group_id\n \t\t};\n-\t\tuint32_t table_id = tbl_data->table_id;\n+\t\tuint32_t table_level = tbl_data->level;\n \n \t\ttunnel_grp_hash = tbl_data->tunnel ?\n \t\t\t\t\ttbl_data->tunnel->groups :\n@@ -9526,8 +9535,9 @@ struct mlx5_flow_tbl_resource *\n \t\tif (he)\n \t\t\tmlx5_hlist_unregister(tunnel_grp_hash, he);\n \t\tDRV_LOG(DEBUG,\n-\t\t\t\"Table_id %u tunnel %u group %u released.\",\n-\t\t\ttable_id,\n+\t\t\t\"table_level %u id %u tunnel %u group %u released.\",\n+\t\t\ttable_level,\n+\t\t\ttbl_data->id,\n \t\t\ttbl_data->tunnel ?\n \t\t\ttbl_data->tunnel->tunnel_id : 0,\n \t\t\ttbl_data->group_id);\n@@ -9655,10 +9665,10 @@ struct mlx5_cache_entry *\n \t * tunnel offload API requires this registration for cases when\n \t * tunnel match rule was inserted before tunnel set rule.\n \t */\n-\ttbl = flow_dv_tbl_resource_get(dev, key->table_id,\n-\t\t\t\t key->direction, key->domain,\n+\ttbl = flow_dv_tbl_resource_get(dev, key->level,\n+\t\t\t\t key->is_egress, key->is_fdb,\n \t\t\t\t dev_flow->external, tunnel,\n-\t\t\t\t group_id, 0, error);\n+\t\t\t\t group_id, 0, key->id, error);\n \tif (!tbl)\n \t\treturn -rte_errno;\t/* No need to refill the error info */\n \ttbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);\n@@ -10137,7 +10147,7 @@ struct mlx5_cache_entry *\n \t\tis_egress = 1;\n \ttbl = flow_dv_tbl_resource_get(dev, next_ft_id,\n \t\t\t\t\tis_egress, is_transfer,\n-\t\t\t\t\ttrue, NULL, 0, 0, error);\n+\t\t\t\t\ttrue, NULL, 0, 0, 0, error);\n \tif (!tbl) {\n \t\trte_flow_error_set(error, ENOMEM,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -11490,7 +11500,7 @@ struct mlx5_cache_entry *\n \t\t\t\t\t\t attr->transfer,\n \t\t\t\t\t\t !!dev_flow->external,\n \t\t\t\t\t\t tunnel, jump_group, 0,\n-\t\t\t\t\t\t error);\n+\t\t\t\t\t\t 0, error);\n \t\t\tif (!tbl)\n \t\t\t\treturn rte_flow_error_set\n \t\t\t\t\t\t(error, errno,\n@@ -12032,9 +12042,10 @@ struct mlx5_cache_entry *\n \tmatcher.priority = mlx5_get_matcher_priority(dev, attr,\n \t\t\t\t\tmatcher.priority);\n \t/* reserved field no needs to be set to 0 here. */\n-\ttbl_key.domain = attr->transfer;\n-\ttbl_key.direction = attr->egress;\n-\ttbl_key.table_id = dev_flow->dv.group;\n+\ttbl_key.is_fdb = attr->transfer;\n+\ttbl_key.is_egress = attr->egress;\n+\ttbl_key.level = dev_flow->dv.group;\n+\ttbl_key.id = dev_flow->dv.table_id;\n \tif (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,\n \t\t\t\t tunnel, attr->group, error))\n \t\treturn -rte_errno;\n@@ -13641,7 +13652,7 @@ struct mlx5_cache_entry *\n \t/* Create the meter table with METER level. */\n \tdtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,\n \t\t\t\t\t egress, transfer, false, NULL, 0,\n-\t\t\t\t\t 0, &error);\n+\t\t\t\t\t 0, 0, &error);\n \tif (!dtb->tbl) {\n \t\tDRV_LOG(ERR, \"Failed to create meter policer table.\");\n \t\treturn -1;\n@@ -13650,7 +13661,7 @@ struct mlx5_cache_entry *\n \tdtb->sfx_tbl = flow_dv_tbl_resource_get(dev,\n \t\t\t\t\t MLX5_FLOW_TABLE_LEVEL_SUFFIX,\n \t\t\t\t\t egress, transfer, false, NULL, 0,\n-\t\t\t\t\t 0, &error);\n+\t\t\t\t\t 0, 0, &error);\n \tif (!dtb->sfx_tbl) {\n \t\tDRV_LOG(ERR, \"Failed to create meter suffix table.\");\n \t\treturn -1;\n@@ -14173,7 +14184,8 @@ struct mlx5_cache_entry *\n \tvoid *flow = NULL;\n \tint ret = -1;\n \n-\ttbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);\n+\ttbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,\n+\t\t\t\t\t0, 0, 0, NULL);\n \tif (!tbl)\n \t\tgoto err;\n \tdcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);\n", "prefixes": [ "v6", "14/15" ] }