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{
    "id": 91860,
    "url": "http://patches.dpdk.org/api/patches/91860/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1618916122-181792-6-git-send-email-jiaweiw@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1618916122-181792-6-git-send-email-jiaweiw@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1618916122-181792-6-git-send-email-jiaweiw@nvidia.com",
    "date": "2021-04-20T10:55:12",
    "name": "[v6,05/15] net/mlx5: use mask for meter register setting",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "4909b4f327412ed7331af09bb325efb846d1e8ec",
    "submitter": {
        "id": 1939,
        "url": "http://patches.dpdk.org/api/people/1939/?format=api",
        "name": "Jiawei Wang",
        "email": "jiaweiw@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1618916122-181792-6-git-send-email-jiaweiw@nvidia.com/mbox/",
    "series": [
        {
            "id": 16520,
            "url": "http://patches.dpdk.org/api/series/16520/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16520",
            "date": "2021-04-20T10:55:12",
            "name": "Add ASO meter support in MLX5 PMD",
            "version": 6,
            "mbox": "http://patches.dpdk.org/series/16520/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/91860/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/91860/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 39781A0548;\n\tTue, 20 Apr 2021 12:55:27 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 189A241357;\n\tTue, 20 Apr 2021 12:55:27 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id C860C411C9\n for <dev@dpdk.org>; Tue, 20 Apr 2021 12:55:25 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n jiaweiw@nvidia.com) with SMTP; 20 Apr 2021 13:55:24 +0300",
            "from nvidia.com (gen-l-vrt-281.mtl.labs.mlnx [10.237.44.1])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13KAtMRr009943;\n Tue, 20 Apr 2021 13:55:23 +0300"
        ],
        "From": "Jiawei Wang <jiaweiw@nvidia.com>",
        "To": "matan@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n ferruh.yigit@intel.com, thomas@monjalon.net,\n Shahaf Shuler <shahafs@nvidia.com>",
        "Cc": "dev@dpdk.org, rasland@nvidia.com, asafp@nvidia.com,\n Shun Hao <shunh@nvidia.com>",
        "Date": "Tue, 20 Apr 2021 13:55:12 +0300",
        "Message-Id": "<1618916122-181792-6-git-send-email-jiaweiw@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1618916122-181792-1-git-send-email-jiaweiw@nvidia.com>",
        "References": "<20210331073632.1443011-1-lizh@nvidia.com>\n <1618916122-181792-1-git-send-email-jiaweiw@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH v6 05/15] net/mlx5: use mask for meter register\n setting",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Shun Hao <shunh@nvidia.com>\n\nASO (Advanced Steering Operation) meter feature may require\nto locate the flow context tag action after the ASO action.\nWhen color register is shared by meter_id/flow_id, it's like:\nBits[0-7] A meter color value set by the HW.\nBits[8-31] A flow id and meter id set by SW.\n\nCurrently the tag action for meter writes all the bits\nof the meter register, so it will potentially overwrite\nmeter color when ASO meter action is before the tag action.\n\nSet only 24-MSB-bits of meter register in the meter tag action.\n\nSigned-off-by: Shun Hao <shunh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c    | 28 ++++++++++++++++++----------\n drivers/net/mlx5/mlx5_flow.h    |  2 ++\n drivers/net/mlx5/mlx5_flow_dv.c |  2 ++\n 3 files changed, 22 insertions(+), 10 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 3bb04d5..1afddf7 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -4258,9 +4258,11 @@ struct mlx5_hlist_entry *\n \trte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action));\n \tactions_rx++;\n \tset_tag = (void *)actions_rx;\n-\tset_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL);\n+\t*set_tag = (struct mlx5_rte_flow_action_set_tag) {\n+\t\t.id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL),\n+\t\t.data = flow_id,\n+\t};\n \tMLX5_ASSERT(set_tag->id > REG_NON);\n-\tset_tag->data = flow_id;\n \ttag_action->conf = set_tag;\n \t/* Create Tx item list. */\n \trte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action));\n@@ -4496,6 +4498,14 @@ struct mlx5_hlist_entry *\n \tset_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre;\n \ttag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items;\n \ttag_item_mask = tag_item_spec + 1;\n+\t/* Both flow_id and meter_id share the same register. */\n+\t*set_tag = (struct mlx5_rte_flow_action_set_tag) {\n+\t\t.id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,\n+\t\t\t\t\t\t\t    0, error),\n+\t\t.offset = mtr_id_offset,\n+\t\t.length = mtr_reg_bits,\n+\t\t.data = fm->idx,\n+\t};\n \t/*\n \t * The color Reg bits used by flow_id are growing from\n \t * msb to lsb, so must do bit reverse for flow_id val in RegC.\n@@ -4503,13 +4513,9 @@ struct mlx5_hlist_entry *\n \tfor (shift = 0; shift < flow_id_bits; shift++)\n \t\tflow_id_reversed = (flow_id_reversed << 1) |\n \t\t\t      ((flow_id >> shift) & 0x1);\n-\t/* Both flow_id and meter_id share the same register. */\n-\tset_tag->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 0, error);\n-\tset_tag->data =\n-\t\t(fm->idx | (flow_id_reversed << (mtr_reg_bits - flow_id_bits)))\n-\t\t<< mtr_id_offset;\n+\tset_tag->data |= flow_id_reversed << (mtr_reg_bits - flow_id_bits);\n \ttag_item_spec->id = set_tag->id;\n-\ttag_item_spec->data = set_tag->data;\n+\ttag_item_spec->data = set_tag->data << mtr_id_offset;\n \ttag_item_mask->data = UINT32_MAX << mtr_id_offset;\n \ttag_action->type = (enum rte_flow_action_type)\n \t\t\t\tMLX5_RTE_FLOW_ACTION_TYPE_TAG;\n@@ -4904,10 +4910,12 @@ struct mlx5_hlist_entry *\n \t\tret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n-\t\tset_tag->id = ret;\n \t\tmlx5_ipool_malloc(priv->sh->ipool\n \t\t\t\t  [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id);\n-\t\tset_tag->data = tag_id;\n+\t\t*set_tag = (struct mlx5_rte_flow_action_set_tag) {\n+\t\t\t.id = ret,\n+\t\t\t.data = tag_id,\n+\t\t};\n \t\t/* Prepare the suffix subflow items. */\n \t\ttag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM);\n \t\ttag_spec->data = tag_id;\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 3145f8f..0806407 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -54,6 +54,8 @@ struct mlx5_rte_flow_item_tag {\n /* Modify selected register. */\n struct mlx5_rte_flow_action_set_tag {\n \tenum modify_reg id;\n+\tuint8_t offset;\n+\tuint8_t length;\n \tuint32_t data;\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex d4d4c1b..4b6b62c 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -965,6 +965,8 @@ struct field_modify_info modify_tcp[] = {\n \tactions[i] = (struct mlx5_modification_cmd) {\n \t\t.action_type = MLX5_MODIFICATION_TYPE_SET,\n \t\t.field = reg_to_field[conf->id],\n+\t\t.offset = conf->offset,\n+\t\t.length = conf->length,\n \t};\n \tactions[i].data0 = rte_cpu_to_be_32(actions[i].data0);\n \tactions[i].data1 = rte_cpu_to_be_32(conf->data);\n",
    "prefixes": [
        "v6",
        "05/15"
    ]
}