Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/91270/?format=api
{ "id": 91270, "url": "http://patches.dpdk.org/api/patches/91270/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210413143038.2621294-10-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210413143038.2621294-10-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210413143038.2621294-10-qi.z.zhang@intel.com", "date": "2021-04-13T14:30:33", "name": "[v3,09/14] net/ice/base: enable I2C read/write commands", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f54ccc46f4e404935b37177495bac48a0573f994", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210413143038.2621294-10-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 16337, "url": "http://patches.dpdk.org/api/series/16337/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16337", "date": "2021-04-13T14:30:24", "name": "ice: base code update batch 2", "version": 3, "mbox": "http://patches.dpdk.org/series/16337/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/91270/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/91270/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BFB91A0524;\n\tTue, 13 Apr 2021 16:27:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D132716107D;\n\tTue, 13 Apr 2021 16:27:13 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 902ED161073\n for <dev@dpdk.org>; Tue, 13 Apr 2021 16:27:11 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2021 07:27:11 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 13 Apr 2021 07:27:09 -0700" ], "IronPort-SDR": [ "\n cN0yvQmXwfYMw2iylTNsQnvVpz2gumy4M1h+6oyTO6pIlphy2oiCcP2m7GSV+2G8Ih9QJ+uMNq\n kaX/uGVcxukg==", "\n vlVs0xtEGGFQSi65b9mWnzG55PuVijfmRkWo+R8CzuhdVBzrJkGpe70ytuMK3vFt6KOtcfgSb9\n N1s9ZyrQH9Fw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9953\"; a=\"214904248\"", "E=Sophos;i=\"5.82,219,1613462400\"; d=\"scan'208\";a=\"214904248\"", "E=Sophos;i=\"5.82,219,1613462400\"; d=\"scan'208\";a=\"417875234\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, ferruh.yigit@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n Maciej Machnikowski <maciej.machnikowski@intel.com>", "Date": "Tue, 13 Apr 2021 22:30:33 +0800", "Message-Id": "<20210413143038.2621294-10-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210413143038.2621294-1-qi.z.zhang@intel.com>", "References": "<20210329141411.2395069-1-qi.z.zhang@intel.com>\n <20210413143038.2621294-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 09/14] net/ice/base: enable I2C read/write\n commands", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable I2C read/write AQ commands. They are now required for\ncontrolling the external physical connectors via external I2C\nport expander on E810-T adapters.\n\nSigned-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 29 +++++++++\n drivers/net/ice/base/ice_common.c | 94 +++++++++++++++++++++++++++\n drivers/net/ice/base/ice_common.h | 8 +++\n 3 files changed, 131 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 4b78da92b5..f9a741e99f 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1665,6 +1665,31 @@ struct ice_aqc_get_link_topo {\n \tu8 rsvd[9];\n };\n \n+/* Read/Write I2C (direct, 0x06E2/0x06E3) */\n+struct ice_aqc_i2c {\n+\tstruct ice_aqc_link_topo_addr topo_addr;\n+\t__le16 i2c_addr;\n+\tu8 i2c_params;\n+#define ICE_AQC_I2C_DATA_SIZE_S\t\t0\n+#define ICE_AQC_I2C_DATA_SIZE_M\t\t(0xF << ICE_AQC_I2C_DATA_SIZE_S)\n+#define ICE_AQC_I2C_ADDR_TYPE_M\t\tBIT(4)\n+#define ICE_AQC_I2C_ADDR_TYPE_7BIT\t0\n+#define ICE_AQC_I2C_ADDR_TYPE_10BIT\tICE_AQC_I2C_ADDR_TYPE_M\n+#define ICE_AQC_I2C_DATA_OFFSET_S\t5\n+#define ICE_AQC_I2C_DATA_OFFSET_M\t(0x3 << ICE_AQC_I2C_DATA_OFFSET_S)\n+#define ICE_AQC_I2C_USE_REPEATED_START\tBIT(7)\n+\tu8 rsvd;\n+\t__le16 i2c_bus_addr;\n+#define ICE_AQC_I2C_ADDR_7BIT_MASK\t0x7F\n+#define ICE_AQC_I2C_ADDR_10BIT_MASK\t0x3FF\n+\tu8 i2c_data[4]; /* Used only by write command, reserved in read. */\n+};\n+\n+/* Read I2C Response (direct, 0x06E2) */\n+struct ice_aqc_read_i2c_resp {\n+\tu8 i2c_data[16];\n+};\n+\n /* Set Port Identification LED (direct, 0x06E9) */\n struct ice_aqc_set_port_id_led {\n \tu8 lport_num;\n@@ -2838,6 +2863,8 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_get_phy_caps get_phy;\n \t\tstruct ice_aqc_set_phy_cfg set_phy;\n \t\tstruct ice_aqc_restart_an restart_an;\n+\t\tstruct ice_aqc_i2c read_write_i2c;\n+\t\tstruct ice_aqc_read_i2c_resp read_i2c_resp;\n \t\tstruct ice_aqc_sff_eeprom read_write_sff_param;\n \t\tstruct ice_aqc_set_port_id_led set_port_id_led;\n \t\tstruct ice_aqc_get_sw_cfg get_sw_conf;\n@@ -3074,6 +3101,8 @@ enum ice_adminq_opc {\n \tice_aqc_opc_set_event_mask\t\t\t= 0x0613,\n \tice_aqc_opc_set_mac_lb\t\t\t\t= 0x0620,\n \tice_aqc_opc_get_link_topo\t\t\t= 0x06E0,\n+\tice_aqc_opc_read_i2c\t\t\t\t= 0x06E2,\n+\tice_aqc_opc_write_i2c\t\t\t\t= 0x06E3,\n \tice_aqc_opc_set_port_id_led\t\t\t= 0x06E9,\n \tice_aqc_opc_get_port_options\t\t\t= 0x06EA,\n \tice_aqc_opc_set_port_option\t\t\t= 0x06EB,\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 356a8b4d09..befaa83a4b 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -4766,6 +4766,100 @@ enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)\n \t\treturn ICE_FW_MODE_NORMAL;\n }\n \n+/**\n+ * ice_aq_read_i2c\n+ * @hw: pointer to the hw struct\n+ * @topo_addr: topology address for a device to communicate with\n+ * @bus_addr: 7-bit I2C bus address\n+ * @addr: I2C memory address (I2C offset) with up to 16 bits\n+ * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size,\n+ *\t\t\t bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes)\n+ * @data: pointer to data (0 to 16 bytes) to be read from the I2C device\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Read I2C (0x06E2)\n+ */\n+enum ice_status\n+ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,\n+\t\tu16 bus_addr, __le16 addr, u8 params, u8 *data,\n+\t\tstruct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc = { 0 };\n+\tstruct ice_aqc_i2c *cmd;\n+\tenum ice_status status;\n+\tu8 data_size;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);\n+\tcmd = &desc.params.read_write_i2c;\n+\n+\tif (!data)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tdata_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;\n+\n+\tcmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);\n+\tcmd->topo_addr = topo_addr;\n+\tcmd->i2c_params = params;\n+\tcmd->i2c_addr = addr;\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+\tif (!status) {\n+\t\tstruct ice_aqc_read_i2c_resp *resp;\n+\t\tu8 i;\n+\n+\t\tresp = &desc.params.read_i2c_resp;\n+\t\tfor (i = 0; i < data_size; i++) {\n+\t\t\t*data = resp->i2c_data[i];\n+\t\t\tdata++;\n+\t\t}\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_write_i2c\n+ * @hw: pointer to the hw struct\n+ * @topo_addr: topology address for a device to communicate with\n+ * @bus_addr: 7-bit I2C bus address\n+ * @addr: I2C memory address (I2C offset) with up to 16 bits\n+ * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)\n+ * @data: pointer to data (0 to 4 bytes) to be written to the I2C device\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Write I2C (0x06E3)\n+ */\n+enum ice_status\n+ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,\n+\t\t u16 bus_addr, __le16 addr, u8 params, u8 *data,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc = { 0 };\n+\tstruct ice_aqc_i2c *cmd;\n+\tu8 i, data_size;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);\n+\tcmd = &desc.params.read_write_i2c;\n+\n+\tdata_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;\n+\n+\t/* data_size limited to 4 */\n+\tif (data_size > 4)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tcmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);\n+\tcmd->topo_addr = topo_addr;\n+\tcmd->i2c_params = params;\n+\tcmd->i2c_addr = addr;\n+\n+\tfor (i = 0; i < data_size; i++) {\n+\t\tcmd->i2c_data[i] = *data;\n+\t\tdata++;\n+\t}\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n /**\n * ice_fw_supports_link_override\n * @hw: pointer to the hardware structure\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex 5b720c3b09..f9e3ed1d67 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -225,5 +225,13 @@ ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,\n bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);\n enum ice_status\n ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);\n+enum ice_status\n+ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,\n+\t\tu16 bus_addr, __le16 addr, u8 params, u8 *data,\n+\t\tstruct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,\n+\t\t u16 bus_addr, __le16 addr, u8 params, u8 *data,\n+\t\t struct ice_sq_cd *cd);\n bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);\n #endif /* _ICE_COMMON_H_ */\n", "prefixes": [ "v3", "09/14" ] }