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GET /api/patches/90714/?format=api
{ "id": 90714, "url": "http://patches.dpdk.org/api/patches/90714/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406144144.19925-40-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406144144.19925-40-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406144144.19925-40-ndabilpuram@marvell.com", "date": "2021-04-06T14:41:31", "name": "[v5,39/52] common/cnxk: add nix tm debug support and misc utils", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b0f659a3b8d94727c47fea5c8fdcc789ef95ecae", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406144144.19925-40-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16131, "url": "http://patches.dpdk.org/api/series/16131/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16131", "date": "2021-04-06T14:40:52", "name": "Add Marvell CNXK common driver", "version": 5, "mbox": "http://patches.dpdk.org/series/16131/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90714/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90714/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BCDE1A0546;\n\tTue, 6 Apr 2021 16:48:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AD57D141157;\n\tTue, 6 Apr 2021 16:43:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 3DCF1141150\n for <dev@dpdk.org>; Tue, 6 Apr 2021 16:43:51 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136Ee6MH000962 for <dev@dpdk.org>; Tue, 6 Apr 2021 07:43:50 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 37r72p30mh-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 07:43:50 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 07:43:48 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 07:43:48 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 446D93F7040;\n Tue, 6 Apr 2021 07:43:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=YoTl9J5avQNA0rLP98+lmiXnYpbyKKQn5ez9F5CI9bY=;\n b=exnXlt/reOPhB/Y6PexFaw9LzEgb10HgMJvQZU3vTqQ8/K225t1t834OIfgdBl/nttmm\n nfU1WrKEVyEVRREuZA0esy4R5jTnDt+UYKryrLczlNPpiTVVh8hk4+qT8QBiKMJc7TFo\n ES8B75PEELsX6YWuLXWzGNpwOvygA+t+fJrJmT9hfU9V+O6xJS+nrelnqeJrxIU/rEDI\n rhcRAhb5Hv5ijpD5BXR+iTlu8gMMcjfgDsVujMhl0GlPH+o8g2TvcAAEyztMyKXb/2pj\n gXm1hcB7InDWVdsCLZpekmtXdVfVUqSC7dPqHCpq5RdNf24ajzYRS2QGuOI6bFCmyFqn SQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Tue, 6 Apr 2021 20:11:31 +0530", "Message-ID": "<20210406144144.19925-40-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406144144.19925-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406144144.19925-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Pky0ETBNLpq2_udLrZfSbHyu6nOaXTXC", "X-Proofpoint-ORIG-GUID": "Pky0ETBNLpq2_udLrZfSbHyu6nOaXTXC", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_03:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v5 39/52] common/cnxk: add nix tm debug support\n and misc utils", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support to dump TM HW registers and hierarchy on error.\nThis patch also adds support for misc utils such as API to\nquery TM HW resource availability, resource pre-allocation\nand static priority support on root node.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 9 +\n drivers/common/cnxk/roc_nix_debug.c | 330 +++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_tm.c | 1 +\n drivers/common/cnxk/roc_nix_tm_ops.c | 125 +++++++++++++\n drivers/common/cnxk/roc_nix_tm_utils.c | 18 ++\n drivers/common/cnxk/roc_utils.c | 108 +++++++++++\n drivers/common/cnxk/version.map | 6 +\n 7 files changed, 597 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex ad00efe..b39f461 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -291,6 +291,7 @@ void __roc_api roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n void __roc_api roc_nix_rq_dump(struct roc_nix_rq *rq);\n void __roc_api roc_nix_cq_dump(struct roc_nix_cq *cq);\n void __roc_api roc_nix_sq_dump(struct roc_nix_sq *sq);\n+void __roc_api roc_nix_tm_dump(struct roc_nix *roc_nix);\n void __roc_api roc_nix_dump(struct roc_nix *roc_nix);\n \n /* IRQ */\n@@ -394,6 +395,10 @@ int __roc_api roc_nix_tm_shaper_profile_update(\n int __roc_api roc_nix_tm_shaper_profile_delete(struct roc_nix *roc_nix,\n \t\t\t\t\t uint32_t id);\n \n+int __roc_api roc_nix_tm_prealloc_res(struct roc_nix *roc_nix, uint8_t lvl,\n+\t\t\t\t uint16_t discontig, uint16_t contig);\n+uint16_t __roc_api roc_nix_tm_leaf_cnt(struct roc_nix *roc_nix);\n+\n struct roc_nix_tm_node *__roc_api roc_nix_tm_node_get(struct roc_nix *roc_nix,\n \t\t\t\t\t\t uint32_t node_id);\n struct roc_nix_tm_node *__roc_api\n@@ -420,6 +425,10 @@ int __roc_api roc_nix_tm_hierarchy_enable(struct roc_nix *roc_nix,\n * TM utilities API.\n */\n int __roc_api roc_nix_tm_node_lvl(struct roc_nix *roc_nix, uint32_t node_id);\n+bool __roc_api roc_nix_tm_root_has_sp(struct roc_nix *roc_nix);\n+void __roc_api roc_nix_tm_rsrc_max(bool pf, uint16_t schq[ROC_TM_LVL_MAX]);\n+int __roc_api roc_nix_tm_rsrc_count(struct roc_nix *roc_nix,\n+\t\t\t\t uint16_t schq[ROC_TM_LVL_MAX]);\n int __roc_api roc_nix_tm_node_name_get(struct roc_nix *roc_nix,\n \t\t\t\t uint32_t node_id, char *buf,\n \t\t\t\t size_t buflen);\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex a0cf98e..6e56513 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -44,6 +44,33 @@ static const struct nix_lf_reg_info nix_lf_reg[] = {\n \tNIX_REG_INFO(NIX_LF_SEND_ERR_DBG),\n };\n \n+static void\n+nix_bitmap_dump(struct plt_bitmap *bmp)\n+{\n+\tuint32_t pos = 0, start_pos;\n+\tuint64_t slab = 0;\n+\tint i;\n+\n+\tplt_bitmap_scan_init(bmp);\n+\tplt_bitmap_scan(bmp, &pos, &slab);\n+\tstart_pos = pos;\n+\n+\tnix_dump_no_nl(\" \\t\\t[\");\n+\tdo {\n+\t\tif (!slab)\n+\t\t\tbreak;\n+\t\ti = 0;\n+\n+\t\tfor (i = 0; i < 64; i++)\n+\t\t\tif (slab & (1ULL << i))\n+\t\t\t\tnix_dump_no_nl(\"%d, \", i);\n+\n+\t\tif (!plt_bitmap_scan(bmp, &pos, &slab))\n+\t\t\tbreak;\n+\t} while (start_pos != pos);\n+\tnix_dump_no_nl(\" ]\");\n+}\n+\n int\n roc_nix_lf_get_reg_count(struct roc_nix *roc_nix)\n {\n@@ -761,6 +788,309 @@ roc_nix_sq_dump(struct roc_nix_sq *sq)\n \tnix_dump(\" fc = %p\", sq->fc);\n };\n \n+static uint8_t\n+nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link,\n+\t\t uint64_t *reg, char regstr[][NIX_REG_NAME_SZ])\n+{\n+\tuint8_t k = 0;\n+\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_SMQ:\n+\t\treg[k] = NIX_AF_SMQX_CFG(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_SMQ[%u]_CFG\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_MDQ[%u]_PARENT\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_MDQ[%u]_PIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_MDQ[%u]_CIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_MDQ[%u]_SHAPE\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_MDQ[%u]_SW_XOFF\",\n+\t\t\t schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treg[k] = NIX_AF_TL4X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL4[%u]_PARENT\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SDP_LINK_CFG\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL4[%u]_PIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL4[%u]_CIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL4[%u]_SHAPE\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL4[%u]_SW_XOFF\",\n+\t\t\t schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treg[k] = NIX_AF_TL3X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL3[%u]_PARENT\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n+\n+\t\treg[k] = NIX_AF_TL3X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL3[%u]_PIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL3[%u]_CIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL3[%u]_SHAPE\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL3[%u]_SW_XOFF\",\n+\t\t\t schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treg[k] = NIX_AF_TL2X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL2[%u]_PARENT\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n+\n+\t\treg[k] = NIX_AF_TL2X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL2[%u]_PIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL2[%u]_CIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL2[%u]_SHAPE\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL2[%u]_SW_XOFF\",\n+\t\t\t schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL1:\n+\n+\t\treg[k] = NIX_AF_TL1X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL1[%u]_CIR\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ, \"NIX_AF_TL1[%u]_SW_XOFF\",\n+\t\t\t schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_DROPPED_PACKETS\", schq);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (k > MAX_REGS_PER_MBOX_MSG) {\n+\t\tnix_dump(\"\\t!!!NIX TM Registers request overflow!!!\");\n+\t\treturn 0;\n+\t}\n+\treturn k;\n+}\n+\n+static void\n+nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)\n+{\n+\tchar regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];\n+\tuint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_txschq_config *req, *rsp;\n+\tconst char *lvlstr, *parent_lvlstr;\n+\tstruct nix_tm_node *node, *parent;\n+\tstruct nix_tm_node *root = NULL;\n+\tuint32_t schq, parent_schq;\n+\tbool found = false;\n+\tuint8_t j, k, rc;\n+\n+\tTAILQ_FOREACH(node, list, node) {\n+\t\tif (node->hw_lvl != hw_lvl)\n+\t\t\tcontinue;\n+\n+\t\tfound = true;\n+\t\tparent = node->parent;\n+\t\tif (hw_lvl == NIX_TXSCH_LVL_CNT) {\n+\t\t\tlvlstr = \"SQ\";\n+\t\t\tschq = node->id;\n+\t\t} else {\n+\t\t\tlvlstr = nix_tm_hwlvl2str(node->hw_lvl);\n+\t\t\tschq = node->hw_id;\n+\t\t}\n+\n+\t\tif (parent) {\n+\t\t\tparent_schq = parent->hw_id;\n+\t\t\tparent_lvlstr = nix_tm_hwlvl2str(parent->hw_lvl);\n+\t\t} else if (node->hw_lvl == NIX_TXSCH_LVL_TL1) {\n+\t\t\tparent_schq = nix->tx_link;\n+\t\t\tparent_lvlstr = \"LINK\";\n+\t\t} else {\n+\t\t\tparent_schq = node->parent_hw_id;\n+\t\t\tparent_lvlstr = nix_tm_hwlvl2str(node->hw_lvl + 1);\n+\t\t}\n+\n+\t\tnix_dump(\"\\t(%p%s) %s_%d->%s_%d\", node,\n+\t\t\t node->child_realloc ? \"[CR]\" : \"\", lvlstr, schq,\n+\t\t\t parent_lvlstr, parent_schq);\n+\n+\t\tif (!(node->flags & NIX_TM_NODE_HWRES))\n+\t\t\tcontinue;\n+\n+\t\t/* Need to dump TL1 when root is TL2 */\n+\t\tif (node->hw_lvl == nix->tm_root_lvl)\n+\t\t\troot = node;\n+\n+\t\t/* Dump registers only when HWRES is present */\n+\t\tk = nix_tm_reg_dump_prep(node->hw_lvl, schq, nix->tx_link, reg,\n+\t\t\t\t\t regstr);\n+\t\tif (!k)\n+\t\t\tcontinue;\n+\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->read = 1;\n+\t\treq->lvl = node->hw_lvl;\n+\t\treq->num_regs = k;\n+\t\tmbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n+\t\trc = mbox_process_msg(mbox, (void **)&rsp);\n+\t\tif (!rc) {\n+\t\t\tfor (j = 0; j < k; j++)\n+\t\t\t\tnix_dump(\"\\t\\t%s=0x%016\" PRIx64, regstr[j],\n+\t\t\t\t\t rsp->regval[j]);\n+\t\t} else {\n+\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n+\t\t}\n+\t}\n+\n+\tif (found)\n+\t\tnix_dump(\"\\n\");\n+\n+\t/* Dump TL1 node data when root level is TL2 */\n+\tif (root && root->hw_lvl == NIX_TXSCH_LVL_TL2) {\n+\t\tk = nix_tm_reg_dump_prep(NIX_TXSCH_LVL_TL1, root->parent_hw_id,\n+\t\t\t\t\t nix->tx_link, reg, regstr);\n+\t\tif (!k)\n+\t\t\treturn;\n+\n+\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->read = 1;\n+\t\treq->lvl = NIX_TXSCH_LVL_TL1;\n+\t\treq->num_regs = k;\n+\t\tmbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n+\t\trc = mbox_process_msg(mbox, (void **)&rsp);\n+\t\tif (!rc) {\n+\t\t\tfor (j = 0; j < k; j++)\n+\t\t\t\tnix_dump(\"\\t\\t%s=0x%016\" PRIx64, regstr[j],\n+\t\t\t\t\t rsp->regval[j]);\n+\t\t} else {\n+\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n+\t\t}\n+\t\tnix_dump(\"\\n\");\n+\t}\n+}\n+\n+void\n+roc_nix_tm_dump(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\tuint8_t hw_lvl, i;\n+\n+\tnix_dump(\"===TM hierarchy and registers dump of %s (pf:vf) (%d:%d)===\",\n+\t\t nix->pci_dev->name, dev_get_pf(dev->pf_func),\n+\t\t dev_get_vf(dev->pf_func));\n+\n+\t/* Dump all trees */\n+\tfor (i = 0; i < ROC_NIX_TM_TREE_MAX; i++) {\n+\t\tnix_dump(\"\\tTM %s:\", nix_tm_tree2str(i));\n+\t\tfor (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++)\n+\t\t\tnix_tm_dump_lvl(nix, &nix->trees[i], hw_lvl);\n+\t}\n+\n+\t/* Dump unused resources */\n+\tnix_dump(\"\\tTM unused resources:\");\n+\thw_lvl = NIX_TXSCH_LVL_SMQ;\n+\tfor (; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\tnix_dump(\"\\t\\ttxschq %7s num = %d\",\n+\t\t\t nix_tm_hwlvl2str(hw_lvl),\n+\t\t\t nix_tm_resource_avail(nix, hw_lvl, false));\n+\n+\t\tnix_bitmap_dump(nix->schq_bmp[hw_lvl]);\n+\t\tnix_dump(\"\\n\");\n+\n+\t\tnix_dump(\"\\t\\ttxschq_contig %7s num = %d\",\n+\t\t\t nix_tm_hwlvl2str(hw_lvl),\n+\t\t\t nix_tm_resource_avail(nix, hw_lvl, true));\n+\t\tnix_bitmap_dump(nix->schq_contig_bmp[hw_lvl]);\n+\t\tnix_dump(\"\\n\");\n+\t}\n+}\n+\n void\n roc_nix_dump(struct roc_nix *roc_nix)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 9b328c9..ad54e17 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -393,6 +393,7 @@ roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq)\n \n \treturn 0;\n exit:\n+\troc_nix_tm_dump(sq->roc_nix);\n \troc_nix_queues_ctx_dump(sq->roc_nix);\n \treturn -EFAULT;\n }\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex e4463d1..ed244d4 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -579,6 +579,58 @@ roc_nix_tm_node_suspend_resume(struct roc_nix *roc_nix, uint32_t node_id,\n }\n \n int\n+roc_nix_tm_prealloc_res(struct roc_nix *roc_nix, uint8_t lvl,\n+\t\t\tuint16_t discontig, uint16_t contig)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_txsch_alloc_req *req;\n+\tstruct nix_txsch_alloc_rsp *rsp;\n+\tuint8_t hw_lvl;\n+\tint rc = -ENOSPC;\n+\n+\thw_lvl = nix_tm_lvl2nix(nix, lvl);\n+\tif (hw_lvl == NIX_TXSCH_LVL_CNT)\n+\t\treturn -EINVAL;\n+\n+\t/* Preallocate contiguous */\n+\tif (nix->contig_rsvd[hw_lvl] < contig) {\n+\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->schq_contig[hw_lvl] = contig - nix->contig_rsvd[hw_lvl];\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tnix_tm_copy_rsp_to_nix(nix, rsp);\n+\t}\n+\n+\t/* Preallocate contiguous */\n+\tif (nix->discontig_rsvd[hw_lvl] < discontig) {\n+\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn -ENOSPC;\n+\t\treq->schq[hw_lvl] = discontig - nix->discontig_rsvd[hw_lvl];\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tnix_tm_copy_rsp_to_nix(nix, rsp);\n+\t}\n+\n+\t/* Save thresholds */\n+\tnix->contig_rsvd[hw_lvl] = contig;\n+\tnix->discontig_rsvd[hw_lvl] = discontig;\n+\t/* Release anything present above thresholds */\n+\tnix_tm_release_resources(nix, hw_lvl, true, true);\n+\tnix_tm_release_resources(nix, hw_lvl, false, true);\n+\treturn 0;\n+}\n+\n+int\n roc_nix_tm_node_shaper_update(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t\t uint32_t profile_id, bool force_update)\n {\n@@ -904,3 +956,76 @@ roc_nix_tm_fini(struct roc_nix *roc_nix)\n \tnix->tm_tree = 0;\n \tnix->tm_flags &= ~NIX_TM_HIERARCHY_ENA;\n }\n+\n+int\n+roc_nix_tm_rsrc_count(struct roc_nix *roc_nix, uint16_t schq[ROC_TM_LVL_MAX])\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct free_rsrcs_rsp *rsp;\n+\tuint8_t hw_lvl;\n+\tint rc, i;\n+\n+\t/* Get the current free resources */\n+\tmbox_alloc_msg_free_rsrc_cnt(mbox);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < ROC_TM_LVL_MAX; i++) {\n+\t\thw_lvl = nix_tm_lvl2nix(nix, i);\n+\t\tif (hw_lvl == NIX_TXSCH_LVL_CNT)\n+\t\t\tcontinue;\n+\n+\t\tschq[i] = (nix->is_nix1 ? rsp->schq_nix1[hw_lvl] :\n+\t\t\t\t\t\trsp->schq[hw_lvl]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+roc_nix_tm_rsrc_max(bool pf, uint16_t schq[ROC_TM_LVL_MAX])\n+{\n+\tuint8_t hw_lvl, i;\n+\tuint16_t max;\n+\n+\tfor (i = 0; i < ROC_TM_LVL_MAX; i++) {\n+\t\thw_lvl = pf ? nix_tm_lvl2nix_tl1_root(i) :\n+\t\t\t\t nix_tm_lvl2nix_tl2_root(i);\n+\n+\t\tswitch (hw_lvl) {\n+\t\tcase NIX_TXSCH_LVL_SMQ:\n+\t\t\tmax = (roc_model_is_cn9k() ?\n+\t\t\t\t\t NIX_CN9K_TXSCH_LVL_SMQ_MAX :\n+\t\t\t\t\t NIX_TXSCH_LVL_SMQ_MAX);\n+\t\t\tbreak;\n+\t\tcase NIX_TXSCH_LVL_TL4:\n+\t\t\tmax = NIX_TXSCH_LVL_TL4_MAX;\n+\t\t\tbreak;\n+\t\tcase NIX_TXSCH_LVL_TL3:\n+\t\t\tmax = NIX_TXSCH_LVL_TL3_MAX;\n+\t\t\tbreak;\n+\t\tcase NIX_TXSCH_LVL_TL2:\n+\t\t\tmax = pf ? NIX_TXSCH_LVL_TL2_MAX : 1;\n+\t\t\tbreak;\n+\t\tcase NIX_TXSCH_LVL_TL1:\n+\t\t\tmax = pf ? 1 : 0;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tmax = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tschq[i] = max;\n+\t}\n+}\n+\n+bool\n+roc_nix_tm_root_has_sp(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (nix->tm_flags & NIX_TM_TL1_NO_SP)\n+\t\treturn false;\n+\treturn true;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex b644716..1d7dd68 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -868,6 +868,24 @@ nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig, uint16_t *schq,\n \treturn cnt;\n }\n \n+uint16_t\n+roc_nix_tm_leaf_cnt(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_tm_node_list *list;\n+\tstruct nix_tm_node *node;\n+\tuint16_t leaf_cnt = 0;\n+\n+\t/* Count leafs only in user list */\n+\tlist = nix_tm_node_list(nix, ROC_NIX_TM_USER);\n+\tTAILQ_FOREACH(node, list, node) {\n+\t\tif (node->id < nix->nb_tx_queues)\n+\t\t\tleaf_cnt++;\n+\t}\n+\n+\treturn leaf_cnt;\n+}\n+\n int\n roc_nix_tm_node_lvl(struct roc_nix *roc_nix, uint32_t node_id)\n {\ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex c2693f8..986be3f 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -38,6 +38,69 @@ roc_error_msg_get(int errorcode)\n \tcase NIX_ERR_AQ_WRITE_FAILED:\n \t\terr_msg = \"AQ write failed\";\n \t\tbreak;\n+\tcase NIX_ERR_TM_LEAF_NODE_GET:\n+\t\terr_msg = \"TM leaf node get failed\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_LVL:\n+\t\terr_msg = \"TM node level invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_PRIO:\n+\t\terr_msg = \"TM node priority invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_PARENT:\n+\t\terr_msg = \"TM parent id invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_NODE_EXISTS:\n+\t\terr_msg = \"TM Node Exists\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_NODE:\n+\t\terr_msg = \"TM node id invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_SHAPER_PROFILE:\n+\t\terr_msg = \"TM shaper profile invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_WEIGHT_EXCEED:\n+\t\terr_msg = \"TM DWRR weight exceeded\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_CHILD_EXISTS:\n+\t\terr_msg = \"TM node children exists\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_PEAK_SZ:\n+\t\terr_msg = \"TM peak size invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_PEAK_RATE:\n+\t\terr_msg = \"TM peak rate invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_COMMIT_SZ:\n+\t\terr_msg = \"TM commit size invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_COMMIT_RATE:\n+\t\terr_msg = \"TM commit rate invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_SHAPER_PROFILE_IN_USE:\n+\t\terr_msg = \"TM shaper profile in use\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_SHAPER_PROFILE_EXISTS:\n+\t\terr_msg = \"TM shaper profile exists\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_INVALID_TREE:\n+\t\terr_msg = \"TM tree invalid\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_PARENT_PRIO_UPDATE:\n+\t\terr_msg = \"TM node parent and prio update failed\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_PRIO_EXCEEDED:\n+\t\terr_msg = \"TM node priority exceeded\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_PRIO_ORDER:\n+\t\terr_msg = \"TM node priority not in order\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_MULTIPLE_RR_GROUPS:\n+\t\terr_msg = \"TM multiple rr groups\";\n+\t\tbreak;\n+\tcase NIX_ERR_TM_SQ_UPDATE_FAIL:\n+\t\terr_msg = \"TM SQ update failed\";\n+\t\tbreak;\n \tcase NIX_ERR_NDC_SYNC:\n \t\terr_msg = \"NDC Sync failed\";\n \t\tbreak;\n@@ -74,9 +137,54 @@ roc_error_msg_get(int errorcode)\n \tcase NIX_AF_ERR_AF_LF_ALLOC:\n \t\terr_msg = \"NIX LF alloc failed\";\n \t\tbreak;\n+\tcase NIX_AF_ERR_TLX_INVALID:\n+\t\terr_msg = \"Invalid NIX TLX\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_TLX_ALLOC_FAIL:\n+\t\terr_msg = \"NIX TLX alloc failed\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_RSS_SIZE_INVALID:\n+\t\terr_msg = \"Invalid RSS size\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_RSS_GRPS_INVALID:\n+\t\terr_msg = \"Invalid RSS groups\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_FRS_INVALID:\n+\t\terr_msg = \"Invalid frame size\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_RX_LINK_INVALID:\n+\t\terr_msg = \"Invalid Rx link\";\n+\t\tbreak;\n+\tcase NIX_AF_INVAL_TXSCHQ_CFG:\n+\t\terr_msg = \"Invalid Tx scheduling config\";\n+\t\tbreak;\n+\tcase NIX_AF_SMQ_FLUSH_FAILED:\n+\t\terr_msg = \"SMQ flush failed\";\n+\t\tbreak;\n \tcase NIX_AF_ERR_LF_RESET:\n \t\terr_msg = \"NIX LF reset failed\";\n \t\tbreak;\n+\tcase NIX_AF_ERR_MARK_CFG_FAIL:\n+\t\terr_msg = \"Marking config failed\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_LSO_CFG_FAIL:\n+\t\terr_msg = \"LSO config failed\";\n+\t\tbreak;\n+\tcase NIX_AF_INVAL_NPA_PF_FUNC:\n+\t\terr_msg = \"Invalid NPA pf_func\";\n+\t\tbreak;\n+\tcase NIX_AF_INVAL_SSO_PF_FUNC:\n+\t\terr_msg = \"Invalid SSO pf_func\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_TX_VTAG_NOSPC:\n+\t\terr_msg = \"No space for Tx VTAG\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_RX_VTAG_INUSE:\n+\t\terr_msg = \"Rx VTAG is in use\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_PTP_CONFIG_FAIL:\n+\t\terr_msg = \"PTP config failed\";\n+\t\tbreak;\n \tcase UTIL_ERR_FS:\n \t\terr_msg = \"file operation failed\";\n \t\tbreak;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex a5eb17e..a3f3059 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -104,11 +104,13 @@ INTERNAL {\n \troc_nix_xstats_names_get;\n \troc_nix_switch_hdr_set;\n \troc_nix_eeprom_info_get;\n+\troc_nix_tm_dump;\n \troc_nix_tm_fini;\n \troc_nix_tm_free_resources;\n \troc_nix_tm_hierarchy_disable;\n \troc_nix_tm_hierarchy_enable;\n \troc_nix_tm_init;\n+\troc_nix_tm_leaf_cnt;\n \troc_nix_tm_node_add;\n \troc_nix_tm_node_delete;\n \troc_nix_tm_node_get;\n@@ -119,7 +121,11 @@ INTERNAL {\n \troc_nix_tm_node_pkt_mode_update;\n \troc_nix_tm_node_shaper_update;\n \troc_nix_tm_node_suspend_resume;\n+\troc_nix_tm_prealloc_res;\n \troc_nix_tm_rlimit_sq;\n+\troc_nix_tm_root_has_sp;\n+\troc_nix_tm_rsrc_count;\n+\troc_nix_tm_rsrc_max;\n \troc_nix_tm_shaper_profile_add;\n \troc_nix_tm_shaper_profile_delete;\n \troc_nix_tm_shaper_profile_get;\n", "prefixes": [ "v5", "39/52" ] }