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GET /api/patches/90695/?format=api
{ "id": 90695, "url": "http://patches.dpdk.org/api/patches/90695/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406144144.19925-21-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406144144.19925-21-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406144144.19925-21-ndabilpuram@marvell.com", "date": "2021-04-06T14:41:12", "name": "[v5,20/52] common/cnxk: add nix Tx queue management API", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "dbedcf323309771f4faad839ac0fc3ac72f3c475", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406144144.19925-21-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16131, "url": "http://patches.dpdk.org/api/series/16131/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16131", "date": "2021-04-06T14:40:52", "name": "Add Marvell CNXK common driver", "version": 5, "mbox": "http://patches.dpdk.org/series/16131/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90695/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90695/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7FCF4A0546;\n\tTue, 6 Apr 2021 16:45:20 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 07F411410D4;\n\tTue, 6 Apr 2021 16:42:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 51D2A1410C8\n for <dev@dpdk.org>; Tue, 6 Apr 2021 16:42:54 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136Ee6Ls000962 for <dev@dpdk.org>; Tue, 6 Apr 2021 07:42:53 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 37r72p30f9-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 07:42:53 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 07:42:52 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 07:42:52 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 95D023F7040;\n Tue, 6 Apr 2021 07:42:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=YwD9scN9bj7WyxS2S2Rq+YRajntXp9dMNT5nu8j/dWQ=;\n b=aLmN1lp79pmLbZoB/LvFTKChhg0Qz/K30JFOiD+aj8PBaM/RSOfRDdHirFl1Pc8MnF5z\n bH5W2bWTAIc1kHgTH7n8T8QmuHu91jRa3mNAXNaKwvukmmMrhKyxPUdoa2Flie2RbBgo\n XXDTctN2P3hVdtPVwuc7mvaI0tlL2Iiwk+25yEcx3LXb10iXCQVQ8NUxSd8PKYaWEFyU\n gXbqER0UahAamm9ugRIOTeNhpGIg6r+GkcJFF6ikpJc1wXPCZs/Q6n6rDfJY7KlJZ70h\n yekQxgeab8pWjoCo4KRHqmcm4BNNI9kzi6m1DYjnz74t3fEjpfpAaqE7qKU1nvC6SEsQ kg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Tue, 6 Apr 2021 20:11:12 +0530", "Message-ID": "<20210406144144.19925-21-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406144144.19925-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406144144.19925-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "6FkKXMPgDLUmTZc7P1SZKZ7FBYWW56oE", "X-Proofpoint-ORIG-GUID": "6FkKXMPgDLUmTZc7P1SZKZ7FBYWW56oE", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_03:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v5 20/52] common/cnxk: add nix Tx queue\n management API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThis patch adds support to init/modify/fini NIX\nSQ(send queue) for both CN9K and CN10K platforms.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 19 ++\n drivers/common/cnxk/roc_nix_queue.c | 358 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 2 +\n 3 files changed, 379 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 227167e..8027e6d 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -83,6 +83,23 @@ struct roc_nix_cq {\n \tuint32_t head;\n };\n \n+struct roc_nix_sq {\n+\t/* Input parameters */\n+\tenum roc_nix_sq_max_sqe_sz max_sqe_sz;\n+\tuint32_t nb_desc;\n+\tuint16_t qid;\n+\t/* End of Input parameters */\n+\tuint16_t sqes_per_sqb_log2;\n+\tstruct roc_nix *roc_nix;\n+\tuint64_t aura_handle;\n+\tint16_t nb_sqb_bufs_adj;\n+\tuint16_t nb_sqb_bufs;\n+\tplt_iova_t io_addr;\n+\tvoid *lmt_addr;\n+\tvoid *sqe_mem;\n+\tvoid *fc;\n+};\n+\n struct roc_nix {\n \t/* Input parameters */\n \tstruct plt_pci_device *pci_dev;\n@@ -144,5 +161,7 @@ int __roc_api roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable);\n int __roc_api roc_nix_rq_fini(struct roc_nix_rq *rq);\n int __roc_api roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq);\n int __roc_api roc_nix_cq_fini(struct roc_nix_cq *cq);\n+int __roc_api roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq);\n+int __roc_api roc_nix_sq_fini(struct roc_nix_sq *sq);\n \n #endif /* _ROC_NIX_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 524b3bc..c5287a9 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -494,3 +494,361 @@ roc_nix_cq_fini(struct roc_nix_cq *cq)\n \tplt_free(cq->desc_base);\n \treturn 0;\n }\n+\n+static int\n+sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint16_t sqes_per_sqb, count, nb_sqb_bufs;\n+\tstruct npa_pool_s pool;\n+\tstruct npa_aura_s aura;\n+\tuint64_t blk_sz;\n+\tuint64_t iova;\n+\tint rc;\n+\n+\tblk_sz = nix->sqb_size;\n+\tif (sq->max_sqe_sz == roc_nix_maxsqesz_w16)\n+\t\tsqes_per_sqb = (blk_sz / 8) / 16;\n+\telse\n+\t\tsqes_per_sqb = (blk_sz / 8) / 8;\n+\n+\tsq->nb_desc = PLT_MAX(256U, sq->nb_desc);\n+\tnb_sqb_bufs = sq->nb_desc / sqes_per_sqb;\n+\tnb_sqb_bufs += NIX_SQB_LIST_SPACE;\n+\t/* Clamp up the SQB count */\n+\tnb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count,\n+\t\t\t (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs));\n+\n+\tsq->nb_sqb_bufs = nb_sqb_bufs;\n+\tsq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb);\n+\tsq->nb_sqb_bufs_adj =\n+\t\tnb_sqb_bufs -\n+\t\t(PLT_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb);\n+\tsq->nb_sqb_bufs_adj =\n+\t\t(sq->nb_sqb_bufs_adj * NIX_SQB_LOWER_THRESH) / 100;\n+\n+\t/* Explicitly set nat_align alone as by default pool is with both\n+\t * nat_align and buf_offset = 1 which we don't want for SQB.\n+\t */\n+\tmemset(&pool, 0, sizeof(struct npa_pool_s));\n+\tpool.nat_align = 1;\n+\n+\tmemset(&aura, 0, sizeof(aura));\n+\taura.fc_ena = 1;\n+\taura.fc_addr = (uint64_t)sq->fc;\n+\taura.fc_hyst_bits = 0; /* Store count on all updates */\n+\trc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura,\n+\t\t\t\t &pool);\n+\tif (rc)\n+\t\tgoto fail;\n+\n+\tsq->sqe_mem = plt_zmalloc(blk_sz * nb_sqb_bufs, blk_sz);\n+\tif (sq->sqe_mem == NULL) {\n+\t\trc = NIX_ERR_NO_MEM;\n+\t\tgoto nomem;\n+\t}\n+\n+\t/* Fill the initial buffers */\n+\tiova = (uint64_t)sq->sqe_mem;\n+\tfor (count = 0; count < nb_sqb_bufs; count++) {\n+\t\troc_npa_aura_op_free(sq->aura_handle, 0, iova);\n+\t\tiova += blk_sz;\n+\t}\n+\troc_npa_aura_op_range_set(sq->aura_handle, (uint64_t)sq->sqe_mem, iova);\n+\n+\treturn rc;\n+nomem:\n+\troc_npa_pool_destroy(sq->aura_handle);\n+fail:\n+\treturn rc;\n+}\n+\n+static void\n+sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n+\t uint16_t smq)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_aq_enq_req *aq;\n+\n+\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_INIT;\n+\taq->sq.max_sqe_size = sq->max_sqe_sz;\n+\n+\taq->sq.max_sqe_size = sq->max_sqe_sz;\n+\taq->sq.smq = smq;\n+\taq->sq.smq_rr_quantum = rr_quantum;\n+\taq->sq.default_chan = nix->tx_chan_base;\n+\taq->sq.sqe_stype = NIX_STYPE_STF;\n+\taq->sq.ena = 1;\n+\tif (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)\n+\t\taq->sq.sqe_stype = NIX_STYPE_STP;\n+\taq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);\n+\taq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);\n+\taq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);\n+\taq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);\n+\taq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);\n+\n+\t/* Many to one reduction */\n+\taq->sq.qint_idx = sq->qid % nix->qints;\n+}\n+\n+static int\n+sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_aq_enq_rsp *rsp;\n+\tstruct nix_aq_enq_req *aq;\n+\tuint16_t sqes_per_sqb;\n+\tvoid *sqb_buf;\n+\tint rc, count;\n+\n+\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_READ;\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Check if sq is already cleaned up */\n+\tif (!rsp->sq.ena)\n+\t\treturn 0;\n+\n+\t/* Disable sq */\n+\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\taq->sq_mask.ena = ~aq->sq_mask.ena;\n+\taq->sq.ena = 0;\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Read SQ and free sqb's */\n+\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_READ;\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (aq->sq.smq_pend)\n+\t\tplt_err(\"SQ has pending SQE's\");\n+\n+\tcount = aq->sq.sqb_count;\n+\tsqes_per_sqb = 1 << sq->sqes_per_sqb_log2;\n+\t/* Free SQB's that are used */\n+\tsqb_buf = (void *)rsp->sq.head_sqb;\n+\twhile (count) {\n+\t\tvoid *next_sqb;\n+\n+\t\tnext_sqb = *(void **)((uintptr_t)sqb_buf +\n+\t\t\t\t (uint32_t)((sqes_per_sqb - 1) *\n+\t\t\t\t\t\t sq->max_sqe_sz));\n+\t\troc_npa_aura_op_free(sq->aura_handle, 1, (uint64_t)sqb_buf);\n+\t\tsqb_buf = next_sqb;\n+\t\tcount--;\n+\t}\n+\n+\t/* Free next to use sqb */\n+\tif (rsp->sq.next_sqb)\n+\t\troc_npa_aura_op_free(sq->aura_handle, 1, rsp->sq.next_sqb);\n+\treturn 0;\n+}\n+\n+static void\n+sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n+\tuint16_t smq)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_INIT;\n+\taq->sq.max_sqe_size = sq->max_sqe_sz;\n+\n+\taq->sq.max_sqe_size = sq->max_sqe_sz;\n+\taq->sq.smq = smq;\n+\taq->sq.smq_rr_weight = rr_quantum;\n+\taq->sq.default_chan = nix->tx_chan_base;\n+\taq->sq.sqe_stype = NIX_STYPE_STF;\n+\taq->sq.ena = 1;\n+\tif (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)\n+\t\taq->sq.sqe_stype = NIX_STYPE_STP;\n+\taq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);\n+\taq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);\n+\taq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);\n+\taq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);\n+\taq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);\n+\n+\t/* Many to one reduction */\n+\taq->sq.qint_idx = sq->qid % nix->qints;\n+}\n+\n+static int\n+sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_cn10k_aq_enq_rsp *rsp;\n+\tstruct nix_cn10k_aq_enq_req *aq;\n+\tuint16_t sqes_per_sqb;\n+\tvoid *sqb_buf;\n+\tint rc, count;\n+\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_READ;\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Check if sq is already cleaned up */\n+\tif (!rsp->sq.ena)\n+\t\treturn 0;\n+\n+\t/* Disable sq */\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\taq->sq_mask.ena = ~aq->sq_mask.ena;\n+\taq->sq.ena = 0;\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Read SQ and free sqb's */\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\taq->qidx = sq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_READ;\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (aq->sq.smq_pend)\n+\t\tplt_err(\"SQ has pending SQE's\");\n+\n+\tcount = aq->sq.sqb_count;\n+\tsqes_per_sqb = 1 << sq->sqes_per_sqb_log2;\n+\t/* Free SQB's that are used */\n+\tsqb_buf = (void *)rsp->sq.head_sqb;\n+\twhile (count) {\n+\t\tvoid *next_sqb;\n+\n+\t\tnext_sqb = *(void **)((uintptr_t)sqb_buf +\n+\t\t\t\t (uint32_t)((sqes_per_sqb - 1) *\n+\t\t\t\t\t\t sq->max_sqe_sz));\n+\t\troc_npa_aura_op_free(sq->aura_handle, 1, (uint64_t)sqb_buf);\n+\t\tsqb_buf = next_sqb;\n+\t\tcount--;\n+\t}\n+\n+\t/* Free next to use sqb */\n+\tif (rsp->sq.next_sqb)\n+\t\troc_npa_aura_op_free(sq->aura_handle, 1, rsp->sq.next_sqb);\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tuint16_t qid, smq = UINT16_MAX;\n+\tuint32_t rr_quantum = 0;\n+\tint rc;\n+\n+\tif (sq == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tqid = sq->qid;\n+\tif (qid >= nix->nb_tx_queues)\n+\t\treturn NIX_ERR_QUEUE_INVALID_RANGE;\n+\n+\tsq->roc_nix = roc_nix;\n+\t/*\n+\t * Allocate memory for flow control updates from HW.\n+\t * Alloc one cache line, so that fits all FC_STYPE modes.\n+\t */\n+\tsq->fc = plt_zmalloc(ROC_ALIGN, ROC_ALIGN);\n+\tif (sq->fc == NULL) {\n+\t\trc = NIX_ERR_NO_MEM;\n+\t\tgoto fail;\n+\t}\n+\n+\trc = sqb_pool_populate(roc_nix, sq);\n+\tif (rc)\n+\t\tgoto nomem;\n+\n+\t/* Init SQ context */\n+\tif (roc_model_is_cn9k())\n+\t\tsq_cn9k_init(nix, sq, rr_quantum, smq);\n+\telse\n+\t\tsq_init(nix, sq, rr_quantum, smq);\n+\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tgoto nomem;\n+\n+\tnix->sqs[qid] = sq;\n+\tsq->io_addr = nix->base + NIX_LF_OP_SENDX(0);\n+\t/* Evenly distribute LMT slot for each sq */\n+\tif (roc_model_is_cn9k()) {\n+\t\t/* Multiple cores/SQ's can use same LMTLINE safely in CN9K */\n+\t\tsq->lmt_addr = (void *)(nix->lmt_base +\n+\t\t\t\t\t((qid & RVU_CN9K_LMT_SLOT_MASK) << 12));\n+\t}\n+\n+\treturn rc;\n+nomem:\n+\tplt_free(sq->fc);\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_sq_fini(struct roc_nix_sq *sq)\n+{\n+\tstruct nix *nix;\n+\tstruct mbox *mbox;\n+\tstruct ndc_sync_op *ndc_req;\n+\tuint16_t qid;\n+\tint rc = 0;\n+\n+\tif (sq == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tnix = roc_nix_to_nix_priv(sq->roc_nix);\n+\tmbox = (&nix->dev)->mbox;\n+\n+\tqid = sq->qid;\n+\n+\t/* Release SQ context */\n+\tif (roc_model_is_cn9k())\n+\t\trc |= sq_cn9k_fini(roc_nix_to_nix_priv(sq->roc_nix), sq);\n+\telse\n+\t\trc |= sq_fini(roc_nix_to_nix_priv(sq->roc_nix), sq);\n+\n+\t/* Sync NDC-NIX-TX for LF */\n+\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n+\tif (ndc_req == NULL)\n+\t\treturn -ENOSPC;\n+\tndc_req->nix_lf_tx_sync = 1;\n+\tif (mbox_process(mbox))\n+\t\trc |= NIX_ERR_NDC_SYNC;\n+\n+\trc |= roc_npa_pool_destroy(sq->aura_handle);\n+\tplt_free(sq->fc);\n+\tplt_free(sq->sqe_mem);\n+\tnix->sqs[qid] = NULL;\n+\n+\treturn rc;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex ae51db1..90bbf07 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -39,6 +39,8 @@ INTERNAL {\n \troc_nix_rq_modify;\n \troc_nix_rx_queue_intr_disable;\n \troc_nix_rx_queue_intr_enable;\n+\troc_nix_sq_fini;\n+\troc_nix_sq_init;\n \troc_nix_unregister_cq_irqs;\n \troc_nix_unregister_queue_irqs;\n \troc_npa_aura_limit_modify;\n", "prefixes": [ "v5", "20/52" ] }