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GET /api/patches/90643/?format=api
{ "id": 90643, "url": "http://patches.dpdk.org/api/patches/90643/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-31-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406114131.25874-31-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406114131.25874-31-ndabilpuram@marvell.com", "date": "2021-04-06T11:41:09", "name": "[v4,30/52] common/cnxk: add nix flow control support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "69325bee2bc06cd66065d220452baf744231e12e", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-31-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16128, "url": "http://patches.dpdk.org/api/series/16128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16128", "date": "2021-04-06T11:40:39", "name": "Add Marvell CNXK common driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90643/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90643/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C9F54A0546;\n\tTue, 6 Apr 2021 13:46:12 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 64D72140F8B;\n\tTue, 6 Apr 2021 13:43:13 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 597EE141048\n for <dev@dpdk.org>; Tue, 6 Apr 2021 13:43:12 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136BeNRs017483 for <dev@dpdk.org>; Tue, 6 Apr 2021 04:43:11 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 37redm9bjq-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 04:43:11 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 04:43:10 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 04:43:10 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 411113F703F;\n Tue, 6 Apr 2021 04:43:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=0TAivB3ta5Z3PRpily7NfVqh0J9JO0lEujmQI/5ATdk=;\n b=C3oCtLU1UvYPjsE8jy46L0pHMO4ihdsebV28bCMxdZ2I+XkLzqh7YnfzYX1ipsbkKOi4\n RBTIdyhXJxiexeg2RVTYYr4j5WPiyg7bD11u6mk5Kn4yPrZMCiUU1+s68iIqPa5Nj46R\n FWl80ljPeQJURK5D2NoQ+MPocFSANyRnoT7QS93CaF7Lnse8WRPN3Sh5NgKU1zWCmc4w\n jfLDrFPO6MnUhXl9/ZHfFxBZ1qF7raonBsvUYRkQadaby2VKjPI0SyyMsUiZtuTRlwRA\n 3cByygN7Ln33jQGK4WhtG2pqGpCPWrGDIuX2T+uh1Sobq4qcJBtpuo+QwFLNMS1cr0r+ /Q==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Tue, 6 Apr 2021 17:11:09 +0530", "Message-ID": "<20210406114131.25874-31-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406114131.25874-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406114131.25874-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "YvVh-nXUIHN-kqjErGMbvNbFaYhHBBjN", "X-Proofpoint-ORIG-GUID": "YvVh-nXUIHN-kqjErGMbvNbFaYhHBBjN", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_02:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 30/52] common/cnxk: add nix flow control\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nAdd support to enable/disable Rx/Tx flow control and pause\nframe configuration on NIX.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_nix.h | 34 ++++++\n drivers/common/cnxk/roc_nix_fc.c | 251 +++++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 4 +\n 4 files changed, 290 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_fc.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex f975681..33eeb8c 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -17,6 +17,7 @@ sources = files('roc_dev.c',\n \t\t'roc_model.c',\n \t\t'roc_nix.c',\n \t\t'roc_nix_debug.c',\n+\t\t'roc_nix_fc.c',\n \t\t'roc_nix_irq.c',\n \t\t'roc_nix_mac.c',\n \t\t'roc_nix_mcast.c',\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex ba3575b..2158f8c 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -17,6 +17,13 @@ enum roc_nix_sq_max_sqe_sz {\n \troc_nix_maxsqesz_w8 = NIX_MAXSQESZ_W8,\n };\n \n+enum roc_nix_fc_mode {\n+\tROC_NIX_FC_NONE = 0,\n+\tROC_NIX_FC_RX,\n+\tROC_NIX_FC_TX,\n+\tROC_NIX_FC_FULL\n+};\n+\n enum roc_nix_vlan_type {\n \tROC_NIX_VLAN_TYPE_INNER = 0x01,\n \tROC_NIX_VLAN_TYPE_OUTER = 0x02,\n@@ -37,6 +44,21 @@ struct roc_nix_vlan_config {\n \t};\n };\n \n+struct roc_nix_fc_cfg {\n+\tbool cq_cfg_valid;\n+\tunion {\n+\t\tstruct {\n+\t\t\tbool enable;\n+\t\t} rxchan_cfg;\n+\n+\t\tstruct {\n+\t\t\tuint32_t rq;\n+\t\t\tuint16_t cq_drop;\n+\t\t\tbool enable;\n+\t\t} cq_cfg;\n+\t};\n+};\n+\n /* Range to adjust PTP frequency. Valid range is\n * (-ROC_NIX_PTP_FREQ_ADJUST, ROC_NIX_PTP_FREQ_ADJUST)\n */\n@@ -293,6 +315,18 @@ int __roc_api roc_nix_mac_link_cb_register(struct roc_nix *roc_nix,\n \t\t\t\t\t link_status_t link_update);\n void __roc_api roc_nix_mac_link_cb_unregister(struct roc_nix *roc_nix);\n \n+/* Flow control */\n+int __roc_api roc_nix_fc_config_set(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_fc_cfg *fc_cfg);\n+\n+int __roc_api roc_nix_fc_config_get(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_fc_cfg *fc_cfg);\n+\n+int __roc_api roc_nix_fc_mode_set(struct roc_nix *roc_nix,\n+\t\t\t\t enum roc_nix_fc_mode mode);\n+\n+enum roc_nix_fc_mode __roc_api roc_nix_fc_mode_get(struct roc_nix *roc_nix);\n+\n /* NPC */\n int __roc_api roc_nix_npc_promisc_ena_dis(struct roc_nix *roc_nix, int enable);\n \ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nnew file mode 100644\nindex 0000000..47be8aa\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -0,0 +1,251 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static inline struct mbox *\n+get_mbox(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\treturn dev->mbox;\n+}\n+\n+static int\n+nix_fc_rxchan_bpid_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (nix->chan_cnt != 0)\n+\t\tfc_cfg->rxchan_cfg.enable = true;\n+\telse\n+\t\tfc_cfg->rxchan_cfg.enable = false;\n+\n+\tfc_cfg->cq_cfg_valid = false;\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix_bp_cfg_req *req;\n+\tstruct nix_bp_cfg_rsp *rsp;\n+\tint rc = -ENOSPC;\n+\n+\tif (roc_nix_is_sdp(roc_nix))\n+\t\treturn 0;\n+\n+\tif (enable) {\n+\t\treq = mbox_alloc_msg_nix_bp_enable(mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->chan_base = 0;\n+\t\treq->chan_cnt = 1;\n+\t\treq->bpid_per_chan = 0;\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc || (req->chan_cnt != rsp->chan_cnt))\n+\t\t\tgoto exit;\n+\n+\t\tnix->bpid[0] = rsp->chan_bpid[0];\n+\t\tnix->chan_cnt = rsp->chan_cnt;\n+\t} else {\n+\t\treq = mbox_alloc_msg_nix_bp_disable(mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->chan_base = 0;\n+\t\treq->chan_cnt = 1;\n+\n+\t\trc = mbox_process(mbox);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\tmemset(nix->bpid, 0, sizeof(uint16_t) * NIX_MAX_CHAN);\n+\t\tnix->chan_cnt = 0;\n+\t}\n+\n+exit:\n+\treturn rc;\n+}\n+\n+static int\n+nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix_aq_enq_rsp *rsp;\n+\tint rc;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = fc_cfg->cq_cfg.rq;\n+\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\taq->qidx = fc_cfg->cq_cfg.rq;\n+\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t}\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tfc_cfg->cq_cfg.cq_drop = rsp->cq.bp;\n+\tfc_cfg->cq_cfg.enable = rsp->cq.bp_ena;\n+\tfc_cfg->cq_cfg_valid = true;\n+\n+exit:\n+\treturn rc;\n+}\n+\n+static int\n+nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = fc_cfg->cq_cfg.rq;\n+\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\t\tif (fc_cfg->cq_cfg.enable) {\n+\t\t\taq->cq.bpid = nix->bpid[0];\n+\t\t\taq->cq_mask.bpid = ~(aq->cq_mask.bpid);\n+\t\t\taq->cq.bp = fc_cfg->cq_cfg.cq_drop;\n+\t\t\taq->cq_mask.bp = ~(aq->cq_mask.bp);\n+\t\t}\n+\n+\t\taq->cq.bp_ena = !!(fc_cfg->cq_cfg.enable);\n+\t\taq->cq_mask.bp_ena = ~(aq->cq_mask.bp_ena);\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\taq->qidx = fc_cfg->cq_cfg.rq;\n+\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\t\tif (fc_cfg->cq_cfg.enable) {\n+\t\t\taq->cq.bpid = nix->bpid[0];\n+\t\t\taq->cq_mask.bpid = ~(aq->cq_mask.bpid);\n+\t\t\taq->cq.bp = fc_cfg->cq_cfg.cq_drop;\n+\t\t\taq->cq_mask.bp = ~(aq->cq_mask.bp);\n+\t\t}\n+\n+\t\taq->cq.bp_ena = !!(fc_cfg->cq_cfg.enable);\n+\t\taq->cq_mask.bp_ena = ~(aq->cq_mask.bp_ena);\n+\t}\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+int\n+roc_nix_fc_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n+{\n+\tif (roc_nix_is_vf_or_sdp(roc_nix))\n+\t\treturn 0;\n+\n+\tif (fc_cfg->cq_cfg_valid)\n+\t\treturn nix_fc_cq_config_get(roc_nix, fc_cfg);\n+\telse\n+\t\treturn nix_fc_rxchan_bpid_get(roc_nix, fc_cfg);\n+}\n+\n+int\n+roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n+{\n+\tif (roc_nix_is_vf_or_sdp(roc_nix))\n+\t\treturn 0;\n+\n+\tif (fc_cfg->cq_cfg_valid)\n+\t\treturn nix_fc_cq_config_set(roc_nix, fc_cfg);\n+\telse\n+\t\treturn nix_fc_rxchan_bpid_set(roc_nix,\n+\t\t\t\t\t fc_cfg->rxchan_cfg.enable);\n+}\n+\n+enum roc_nix_fc_mode\n+roc_nix_fc_mode_get(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct cgx_pause_frm_cfg *req, *rsp;\n+\tenum roc_nix_fc_mode mode;\n+\tint rc = -ENOSPC;\n+\n+\tif (roc_nix_is_lbk(roc_nix))\n+\t\treturn ROC_NIX_FC_NONE;\n+\n+\treq = mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->set = 0;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tif (rsp->rx_pause && rsp->tx_pause)\n+\t\tmode = ROC_NIX_FC_FULL;\n+\telse if (rsp->rx_pause)\n+\t\tmode = ROC_NIX_FC_RX;\n+\telse if (rsp->tx_pause)\n+\t\tmode = ROC_NIX_FC_TX;\n+\telse\n+\t\tmode = ROC_NIX_FC_NONE;\n+\n+\tnix->rx_pause = rsp->rx_pause;\n+\tnix->tx_pause = rsp->tx_pause;\n+\treturn mode;\n+\n+exit:\n+\treturn ROC_NIX_FC_NONE;\n+}\n+\n+int\n+roc_nix_fc_mode_set(struct roc_nix *roc_nix, enum roc_nix_fc_mode mode)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct cgx_pause_frm_cfg *req;\n+\tuint8_t tx_pause, rx_pause;\n+\tint rc = -ENOSPC;\n+\n+\tif (roc_nix_is_lbk(roc_nix))\n+\t\treturn NIX_ERR_OP_NOTSUP;\n+\n+\trx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_RX);\n+\ttx_pause = (mode == ROC_NIX_FC_FULL) || (mode == ROC_NIX_FC_TX);\n+\n+\treq = mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->set = 1;\n+\treq->rx_pause = rx_pause;\n+\treq->tx_pause = tx_pause;\n+\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tnix->rx_pause = rx_pause;\n+\tnix->tx_pause = tx_pause;\n+\n+exit:\n+\treturn rc;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 5e90129..48182a0 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -21,6 +21,10 @@ INTERNAL {\n \troc_nix_dev_init;\n \troc_nix_dump;\n \troc_nix_err_intr_ena_dis;\n+\troc_nix_fc_config_get;\n+\troc_nix_fc_config_set;\n+\troc_nix_fc_mode_set;\n+\troc_nix_fc_mode_get;\n \troc_nix_get_base_chan;\n \troc_nix_get_pf;\n \troc_nix_get_pf_func;\n", "prefixes": [ "v4", "30/52" ] }