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GET /api/patches/90621/?format=api
{ "id": 90621, "url": "http://patches.dpdk.org/api/patches/90621/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-9-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406114131.25874-9-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406114131.25874-9-ndabilpuram@marvell.com", "date": "2021-04-06T11:40:47", "name": "[v4,08/52] common/cnxk: add base device class", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8e414a1e589ad71dab0e4cd20bbfaa3745e01ba9", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-9-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16128, "url": "http://patches.dpdk.org/api/series/16128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16128", "date": "2021-04-06T11:40:39", "name": "Add Marvell CNXK common driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90621/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90621/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 17EFCA0546;\n\tTue, 6 Apr 2021 13:43:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7CE12140F4A;\n\tTue, 6 Apr 2021 13:42:08 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id D4BD6140F43\n for <dev@dpdk.org>; Tue, 6 Apr 2021 13:42:06 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136BeSq3017530 for <dev@dpdk.org>; Tue, 6 Apr 2021 04:42:06 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 37redm9ber-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 04:42:06 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 04:42:03 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 04:42:03 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 071A53F705B;\n Tue, 6 Apr 2021 04:42:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=UVaHD28czy+OqyHSmCBH47uxCRdffoafwi1atIh8Erk=;\n b=g6NX88sCZYTt7YTKf9F5seTMQJmV/xeOFU3TzgumhDJsvORdZ9Gk89PIQDUkyqu7zsG1\n ukfDYRUz4U/53VpWc8WOGReDUGK+XRODF+xhBgMSQn0uJGtRJS/cOVUiwgQ6adzPBwAX\n eHLr0yc4F+6YaRvw/X7aR94tkb+/uDRoMH002nE7CI5ZNDgLIwRBHCSB7zz8Xj9oAspJ\n HHB2/wnSYn26zaW7cqxReWLKqn+T84c+7o4wXp7GGT4cSbe6CT1nmxgy+8U31QNQuCa/\n 6iqy3uaT9iWG2E0xaQ3M282ZACtO+JKtr/HNq2SFirQU0Fg0h9Xc9H0bqfJI5fKB5ZDX Jg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Tue, 6 Apr 2021 17:10:47 +0530", "Message-ID": "<20210406114131.25874-9-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406114131.25874-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406114131.25874-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "0Dk6P-JZynrjzD2OOt14BXeuXmHtkDqR", "X-Proofpoint-ORIG-GUID": "0Dk6P-JZynrjzD2OOt14BXeuXmHtkDqR", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_02:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 08/52] common/cnxk: add base device class", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nIntroduce 'dev' class to hold cnxk PCIe device specific\ninformation and operations.\n\nAll PCIe drivers(ethdev, mempool, cryptodev and eventdev) of cnxk\ninherits this base object to avail the common functionalities such\nas mailbox creation, interrupt registration, LMT setup, VF message\nmbox forwarding, etc.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/meson.build | 4 +-\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_dev.c | 362 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_dev_priv.h | 42 +++++\n drivers/common/cnxk/roc_idev.c | 77 ++++++++\n drivers/common/cnxk/roc_idev.h | 12 ++\n drivers/common/cnxk/roc_idev_priv.h | 22 +++\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/version.map | 2 +\n 9 files changed, 526 insertions(+), 1 deletion(-)\n create mode 100644 drivers/common/cnxk/roc_dev.c\n create mode 100644 drivers/common/cnxk/roc_idev.c\n create mode 100644 drivers/common/cnxk/roc_idev.h\n create mode 100644 drivers/common/cnxk/roc_idev_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex a7e7968..17cbc36 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -10,7 +10,9 @@ endif\n \n config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'\n deps = ['eal', 'pci', 'bus_pci', 'mbuf']\n-sources = files('roc_irq.c',\n+sources = files('roc_dev.c',\n+\t\t'roc_idev.c',\n+\t\t'roc_irq.c',\n \t\t'roc_mbox.c',\n \t\t'roc_model.c',\n \t\t'roc_platform.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex f2f1f5e..27ddc3a 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -82,4 +82,7 @@\n /* Utils */\n #include \"roc_utils.h\"\n \n+/* Idev */\n+#include \"roc_idev.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nnew file mode 100644\nindex 0000000..380c71b\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -0,0 +1,362 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <fcntl.h>\n+#include <inttypes.h>\n+#include <string.h>\n+#include <sys/mman.h>\n+#include <unistd.h>\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+/* PCI Extended capability ID */\n+#define ROC_PCI_EXT_CAP_ID_SRIOV 0x10 /* SRIOV cap */\n+\n+/* Single Root I/O Virtualization */\n+#define ROC_PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */\n+\n+static void\n+process_msgs(struct dev *dev, struct mbox *mbox)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[0];\n+\tstruct mbox_hdr *req_hdr;\n+\tstruct mbox_msghdr *msg;\n+\tint msgs_acked = 0;\n+\tint offset;\n+\tuint16_t i;\n+\n+\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n+\tif (req_hdr->num_msgs == 0)\n+\t\treturn;\n+\n+\toffset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n+\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n+\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n+\n+\t\tmsgs_acked++;\n+\t\tplt_base_dbg(\"Message 0x%x (%s) pf:%d/vf:%d\", msg->id,\n+\t\t\t mbox_id2name(msg->id), dev_get_pf(msg->pcifunc),\n+\t\t\t dev_get_vf(msg->pcifunc));\n+\n+\t\tswitch (msg->id) {\n+\t\t\t/* Add message id's that are handled here */\n+\t\tcase MBOX_MSG_READY:\n+\t\t\t/* Get our identity */\n+\t\t\tdev->pf_func = msg->pcifunc;\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tif (msg->rc)\n+\t\t\t\tplt_err(\"Message (%s) response has err=%d\",\n+\t\t\t\t\tmbox_id2name(msg->id), msg->rc);\n+\t\t\tbreak;\n+\t\t}\n+\t\toffset = mbox->rx_start + msg->next_msgoff;\n+\t}\n+\n+\tmbox_reset(mbox, 0);\n+\t/* Update acked if someone is waiting a message */\n+\tmdev->msgs_acked = msgs_acked;\n+\tplt_wmb();\n+}\n+\n+static int\n+mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req)\n+{\n+\t/* Check if valid, if not reply with a invalid msg */\n+\tif (req->sig != MBOX_REQ_SIG)\n+\t\treturn -EIO;\n+\n+\tswitch (req->id) {\n+\tdefault:\n+\t\treply_invalid_msg(&dev->mbox_up, 0, 0, req->id);\n+\t\tbreak;\n+\t}\n+\n+\treturn -ENODEV;\n+}\n+\n+static void\n+process_msgs_up(struct dev *dev, struct mbox *mbox)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[0];\n+\tstruct mbox_hdr *req_hdr;\n+\tstruct mbox_msghdr *msg;\n+\tint i, err, offset;\n+\n+\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n+\tif (req_hdr->num_msgs == 0)\n+\t\treturn;\n+\n+\toffset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n+\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n+\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n+\n+\t\tplt_base_dbg(\"Message 0x%x (%s) pf:%d/vf:%d\", msg->id,\n+\t\t\t mbox_id2name(msg->id), dev_get_pf(msg->pcifunc),\n+\t\t\t dev_get_vf(msg->pcifunc));\n+\t\terr = mbox_process_msgs_up(dev, msg);\n+\t\tif (err)\n+\t\t\tplt_err(\"Error %d handling 0x%x (%s)\", err, msg->id,\n+\t\t\t\tmbox_id2name(msg->id));\n+\t\toffset = mbox->rx_start + msg->next_msgoff;\n+\t}\n+\t/* Send mbox responses */\n+\tif (mdev->num_msgs) {\n+\t\tplt_base_dbg(\"Reply num_msgs:%d\", mdev->num_msgs);\n+\t\tmbox_msg_send(mbox, 0);\n+\t}\n+}\n+\n+static void\n+roc_af_pf_mbox_irq(void *param)\n+{\n+\tstruct dev *dev = param;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(dev->bar2 + RVU_PF_INT);\n+\tif (intr == 0)\n+\t\tplt_base_dbg(\"Proceeding to check mbox UP messages if any\");\n+\n+\tplt_write64(intr, dev->bar2 + RVU_PF_INT);\n+\tplt_base_dbg(\"Irq 0x%\" PRIx64 \"(pf:%d)\", intr, dev->pf);\n+\n+\t/* First process all configuration messages */\n+\tprocess_msgs(dev, dev->mbox);\n+\n+\t/* Process Uplink messages */\n+\tprocess_msgs_up(dev, &dev->mbox_up);\n+}\n+\n+static int\n+mbox_register_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)\n+{\n+\tstruct plt_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tint rc;\n+\n+\tplt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n+\n+\t/* MBOX interrupt AF <-> PF */\n+\trc = dev_irq_register(intr_handle, roc_af_pf_mbox_irq, dev,\n+\t\t\t RVU_PF_INT_VEC_AFPF_MBOX);\n+\tif (rc) {\n+\t\tplt_err(\"Fail to register AF<->PF mbox irq\");\n+\t\treturn rc;\n+\t}\n+\n+\tplt_write64(~0ull, dev->bar2 + RVU_PF_INT);\n+\tplt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static int\n+mbox_register_irq(struct plt_pci_device *pci_dev, struct dev *dev)\n+{\n+\treturn mbox_register_pf_irq(pci_dev, dev);\n+}\n+\n+static void\n+mbox_unregister_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)\n+{\n+\tstruct plt_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\n+\tplt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n+\n+\t/* MBOX interrupt AF <-> PF */\n+\tdev_irq_unregister(intr_handle, roc_af_pf_mbox_irq, dev,\n+\t\t\t RVU_PF_INT_VEC_AFPF_MBOX);\n+}\n+\n+static void\n+mbox_unregister_irq(struct plt_pci_device *pci_dev, struct dev *dev)\n+{\n+\tmbox_unregister_pf_irq(pci_dev, dev);\n+}\n+\n+static uint16_t\n+dev_pf_total_vfs(struct plt_pci_device *pci_dev)\n+{\n+\tuint16_t total_vfs = 0;\n+\tint sriov_pos, rc;\n+\n+\tsriov_pos =\n+\t\tplt_pci_find_ext_capability(pci_dev, ROC_PCI_EXT_CAP_ID_SRIOV);\n+\tif (sriov_pos <= 0) {\n+\t\tplt_warn(\"Unable to find SRIOV cap, rc=%d\", sriov_pos);\n+\t\treturn 0;\n+\t}\n+\n+\trc = plt_pci_read_config(pci_dev, &total_vfs, 2,\n+\t\t\t\t sriov_pos + ROC_PCI_SRIOV_TOTAL_VF);\n+\tif (rc < 0) {\n+\t\tplt_warn(\"Unable to read SRIOV cap, rc=%d\", rc);\n+\t\treturn 0;\n+\t}\n+\n+\treturn total_vfs;\n+}\n+\n+static int\n+dev_setup_shared_lmt_region(struct mbox *mbox)\n+{\n+\tstruct lmtst_tbl_setup_req *req;\n+\n+\treq = mbox_alloc_msg_lmtst_tbl_setup(mbox);\n+\treq->pcifunc = idev_lmt_pffunc_get();\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static int\n+dev_lmt_setup(struct plt_pci_device *pci_dev, struct dev *dev)\n+{\n+\tuint64_t bar4_mbox_sz = MBOX_SIZE;\n+\tstruct idev_cfg *idev;\n+\tint rc;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tdev->lmt_base = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);\n+\t\treturn 0;\n+\t}\n+\n+\t/* [CN10K, .) */\n+\n+\t/* Set common lmt region from second pf_func onwards. */\n+\tif (!dev->disable_shared_lmt && idev_lmt_pffunc_get() &&\n+\t dev->pf_func != idev_lmt_pffunc_get()) {\n+\t\trc = dev_setup_shared_lmt_region(dev->mbox);\n+\t\tif (!rc) {\n+\t\t\tdev->lmt_base = roc_idev_lmt_base_addr_get();\n+\t\t\treturn rc;\n+\t\t}\n+\t\tplt_err(\"Failed to setup shared lmt region, pf_func %d err %d \"\n+\t\t\t\"Using respective LMT region per pf func\",\n+\t\t\tdev->pf_func, rc);\n+\t}\n+\n+\t/* PF BAR4 should always be sufficient enough to\n+\t * hold PF-AF MBOX + PF-VF MBOX + LMT lines.\n+\t */\n+\tif (pci_dev->mem_resource[4].len <\n+\t (bar4_mbox_sz + (RVU_LMT_LINE_MAX * RVU_LMT_SZ))) {\n+\t\tplt_err(\"Not enough bar4 space for lmt lines and mbox\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* LMT base is just after total VF MBOX area */\n+\tbar4_mbox_sz += (MBOX_SIZE * dev_pf_total_vfs(pci_dev));\n+\tdev->lmt_base = dev->bar4 + bar4_mbox_sz;\n+\n+\t/* Base LMT address should be chosen from only those pci funcs which\n+\t * participate in LMT shared mode.\n+\t */\n+\tif (!dev->disable_shared_lmt) {\n+\t\tidev = idev_get_cfg();\n+\t\tif (!__atomic_load_n(&idev->lmt_pf_func, __ATOMIC_ACQUIRE)) {\n+\t\t\tidev->lmt_base_addr = dev->lmt_base;\n+\t\t\tidev->lmt_pf_func = dev->pf_func;\n+\t\t\tidev->num_lmtlines = RVU_LMT_LINE_MAX;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+dev_init(struct dev *dev, struct plt_pci_device *pci_dev)\n+{\n+\tint direction, up_direction, rc;\n+\tuintptr_t bar2, bar4, mbox;\n+\tuint64_t intr_offset;\n+\n+\tbar2 = (uintptr_t)pci_dev->mem_resource[2].addr;\n+\tbar4 = (uintptr_t)pci_dev->mem_resource[4].addr;\n+\tif (bar2 == 0 || bar4 == 0) {\n+\t\tplt_err(\"Failed to get PCI bars\");\n+\t\trc = -ENODEV;\n+\t\tgoto error;\n+\t}\n+\n+\t/* Trigger fault on bar2 and bar4 regions\n+\t * to avoid BUG_ON in remap_pfn_range()\n+\t * in latest kernel.\n+\t */\n+\t*(volatile uint64_t *)bar2;\n+\t*(volatile uint64_t *)bar4;\n+\n+\t/* Check ROC model supported */\n+\tif (roc_model->flag == 0) {\n+\t\trc = UTIL_ERR_INVALID_MODEL;\n+\t\tgoto error;\n+\t}\n+\n+\tdev->bar2 = bar2;\n+\tdev->bar4 = bar4;\n+\n+\tmbox = bar4;\n+\tdirection = MBOX_DIR_PFAF;\n+\tup_direction = MBOX_DIR_PFAF_UP;\n+\tintr_offset = RVU_PF_INT;\n+\n+\t/* Initialize the local mbox */\n+\trc = mbox_init(&dev->mbox_local, mbox, bar2, direction, 1, intr_offset);\n+\tif (rc)\n+\t\tgoto error;\n+\tdev->mbox = &dev->mbox_local;\n+\n+\trc = mbox_init(&dev->mbox_up, mbox, bar2, up_direction, 1, intr_offset);\n+\tif (rc)\n+\t\tgoto mbox_fini;\n+\n+\t/* Register mbox interrupts */\n+\trc = mbox_register_irq(pci_dev, dev);\n+\tif (rc)\n+\t\tgoto mbox_fini;\n+\n+\t/* Check the readiness of PF/VF */\n+\trc = send_ready_msg(dev->mbox, &dev->pf_func);\n+\tif (rc)\n+\t\tgoto mbox_unregister;\n+\n+\tdev->pf = dev_get_pf(dev->pf_func);\n+\n+\tdev->mbox_active = 1;\n+\n+\t/* Setup LMT line base */\n+\trc = dev_lmt_setup(pci_dev, dev);\n+\tif (rc)\n+\t\tgoto iounmap;\n+\n+\treturn rc;\n+iounmap:\n+mbox_unregister:\n+\tmbox_unregister_irq(pci_dev, dev);\n+mbox_fini:\n+\tmbox_fini(dev->mbox);\n+\tmbox_fini(&dev->mbox_up);\n+error:\n+\treturn rc;\n+}\n+\n+int\n+dev_fini(struct dev *dev, struct plt_pci_device *pci_dev)\n+{\n+\tstruct plt_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tstruct mbox *mbox;\n+\n+\tmbox_unregister_irq(pci_dev, dev);\n+\n+\t/* Release PF - AF */\n+\tmbox = dev->mbox;\n+\tmbox_fini(mbox);\n+\tmbox = &dev->mbox_up;\n+\tmbox_fini(mbox);\n+\tdev->mbox_active = 0;\n+\n+\t/* Disable MSIX vectors */\n+\tdev_irqs_disable(intr_handle);\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex c7f79f7..c0308e7 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -5,9 +5,51 @@\n #ifndef _ROC_DEV_PRIV_H\n #define _ROC_DEV_PRIV_H\n \n+#define RVU_PFVF_PF_SHIFT 10\n+#define RVU_PFVF_PF_MASK 0x3F\n+#define RVU_PFVF_FUNC_SHIFT 0\n+#define RVU_PFVF_FUNC_MASK 0x3FF\n+#define RVU_MAX_INT_RETRY 3\n+\n+static inline int\n+dev_get_vf(uint16_t pf_func)\n+{\n+\treturn (((pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK) - 1);\n+}\n+\n+static inline int\n+dev_get_pf(uint16_t pf_func)\n+{\n+\treturn (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;\n+}\n+\n+static inline int\n+dev_pf_func(int pf, int vf)\n+{\n+\treturn (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1);\n+}\n+\n+struct dev {\n+\tuint16_t pf;\n+\tuint16_t pf_func;\n+\tuint8_t mbox_active;\n+\tbool drv_inited;\n+\tuintptr_t bar2;\n+\tuintptr_t bar4;\n+\tuintptr_t lmt_base;\n+\tstruct mbox mbox_local;\n+\tstruct mbox mbox_up;\n+\tuint64_t hwcap;\n+\tstruct mbox *mbox;\n+\tbool disable_shared_lmt; /* false(default): shared lmt mode enabled */\n+} __plt_cache_aligned;\n+\n extern uint16_t dev_rclk_freq;\n extern uint16_t dev_sclk_freq;\n \n+int dev_init(struct dev *dev, struct plt_pci_device *pci_dev);\n+int dev_fini(struct dev *dev, struct plt_pci_device *pci_dev);\n+\n int dev_irq_register(struct plt_intr_handle *intr_handle,\n \t\t plt_intr_callback_fn cb, void *data, unsigned int vec);\n void dev_irq_unregister(struct plt_intr_handle *intr_handle,\ndiff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nnew file mode 100644\nindex 0000000..7fbbbdc\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -0,0 +1,77 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+struct idev_cfg *\n+idev_get_cfg(void)\n+{\n+\tstatic const char name[] = \"roc_cn10k_intra_device_conf\";\n+\tconst struct plt_memzone *mz;\n+\tstruct idev_cfg *idev;\n+\n+\tmz = plt_memzone_lookup(name);\n+\tif (mz != NULL)\n+\t\treturn mz->addr;\n+\n+\t/* Request for the first time */\n+\tmz = plt_memzone_reserve_cache_align(name, sizeof(struct idev_cfg));\n+\tif (mz != NULL) {\n+\t\tidev = mz->addr;\n+\t\tidev_set_defaults(idev);\n+\t\treturn idev;\n+\t}\n+\treturn NULL;\n+}\n+\n+void\n+idev_set_defaults(struct idev_cfg *idev)\n+{\n+\tidev->lmt_pf_func = 0;\n+\tidev->lmt_base_addr = 0;\n+\tidev->num_lmtlines = 0;\n+}\n+\n+uint16_t\n+idev_lmt_pffunc_get(void)\n+{\n+\tstruct idev_cfg *idev;\n+\tuint16_t lmt_pf_func;\n+\n+\tidev = idev_get_cfg();\n+\tlmt_pf_func = 0;\n+\tif (idev != NULL)\n+\t\tlmt_pf_func = idev->lmt_pf_func;\n+\n+\treturn lmt_pf_func;\n+}\n+\n+uint64_t\n+roc_idev_lmt_base_addr_get(void)\n+{\n+\tuint64_t lmt_base_addr;\n+\tstruct idev_cfg *idev;\n+\n+\tidev = idev_get_cfg();\n+\tlmt_base_addr = 0;\n+\tif (idev != NULL)\n+\t\tlmt_base_addr = idev->lmt_base_addr;\n+\n+\treturn lmt_base_addr;\n+}\n+\n+uint16_t\n+roc_idev_num_lmtlines_get(void)\n+{\n+\tstruct idev_cfg *idev;\n+\tuint16_t num_lmtlines;\n+\n+\tidev = idev_get_cfg();\n+\tnum_lmtlines = 0;\n+\tif (idev != NULL)\n+\t\tnum_lmtlines = idev->num_lmtlines;\n+\n+\treturn num_lmtlines;\n+}\ndiff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h\nnew file mode 100644\nindex 0000000..dff0741\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_idev.h\n@@ -0,0 +1,12 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_IDEV_H_\n+#define _ROC_IDEV_H_\n+\n+/* LMT */\n+uint64_t __roc_api roc_idev_lmt_base_addr_get(void);\n+uint16_t __roc_api roc_idev_num_lmtlines_get(void);\n+\n+#endif /* _ROC_IDEV_H_ */\ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nnew file mode 100644\nindex 0000000..a096288\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_IDEV_PRIV_H_\n+#define _ROC_IDEV_PRIV_H_\n+\n+/* Intra device related functions */\n+struct idev_cfg {\n+\tuint16_t lmt_pf_func;\n+\tuint16_t num_lmtlines;\n+\tuint64_t lmt_base_addr;\n+};\n+\n+/* Generic */\n+struct idev_cfg *idev_get_cfg(void);\n+void idev_set_defaults(struct idev_cfg *idev);\n+\n+/* idev lmt */\n+uint16_t idev_lmt_pffunc_get(void);\n+\n+#endif /* _ROC_IDEV_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex c385f11..2df2d66 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -14,4 +14,7 @@\n /* Dev */\n #include \"roc_dev_priv.h\"\n \n+/* idev */\n+#include \"roc_idev_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 8ea8e95..369cff3 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -5,6 +5,8 @@ INTERNAL {\n \tcnxk_logtype_mbox;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n+\troc_idev_lmt_base_addr_get;\n+\troc_idev_num_lmtlines_get;\n \troc_model;\n \troc_plt_init;\n \troc_plt_init_cb_register;\n", "prefixes": [ "v4", "08/52" ] }