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GET /api/patches/90620/?format=api
{ "id": 90620, "url": "http://patches.dpdk.org/api/patches/90620/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-8-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406114131.25874-8-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406114131.25874-8-ndabilpuram@marvell.com", "date": "2021-04-06T11:40:46", "name": "[v4,07/52] common/cnxk: add mailbox base infra", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d30ea09eff145daff8c2bf9dc631f71685a46e0a", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-8-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16128, "url": "http://patches.dpdk.org/api/series/16128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16128", "date": "2021-04-06T11:40:39", "name": "Add Marvell CNXK common driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90620/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/90620/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 95704A0546;\n\tTue, 6 Apr 2021 13:42:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4649B140F39;\n\tTue, 6 Apr 2021 13:42:06 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 5B894140F43\n for <dev@dpdk.org>; Tue, 6 Apr 2021 13:42:04 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136Bdw7e008331 for <dev@dpdk.org>; Tue, 6 Apr 2021 04:42:03 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 37r72p2dnq-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 04:42:03 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 04:42:00 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 04:42:00 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 1F46F3F703F;\n Tue, 6 Apr 2021 04:41:57 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=XYGC1cz/5mSm6qtxzjrf2PXULsSS7qANfPDww06gV8U=;\n b=dsQQEFoX6WMXlidSCuGklytmZpvyHjl8uzRoBJSeffdqYhp5UlYvs10AuAAzxL0eOVaQ\n JlP07maR0cIoJ/CGzC5Raty8JuEGdiKG/rvhKAcMVQKk8gnXUshUDBdKlc1Fa/wk3bkm\n E0+7Wy93UxSP/KDhXNtJWjrf7gLvYgUXSoLxPTwdfYXXTmvmRums6zk8tS2ImJaRjwPA\n pTieEhA9l/fRePg38/t+EaqLMY8BvVRf7yxuhd5zly4wCrAPz56/CBMKscFbVm4bYSyo\n 83HZPzb9c/GT65Mh9l+bPg60+BUmypxUE1+wurfZRjRQgm0PYoEw/DUYDFSWHYL/DqhH aw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Tue, 6 Apr 2021 17:10:46 +0530", "Message-ID": "<20210406114131.25874-8-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406114131.25874-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406114131.25874-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "5TZeF47a7dzkmtDAhaGC6FtO8bM_DIN7", "X-Proofpoint-ORIG-GUID": "5TZeF47a7dzkmtDAhaGC6FtO8bM_DIN7", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_02:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 07/52] common/cnxk: add mailbox base infra", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThis patch adds mailbox infra API's to communicate with Kernel AF\ndriver. These API's will be used by all the other cnxk drivers\nfor mbox init/fini, send/recv functionality.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_dev_priv.h | 3 +\n drivers/common/cnxk/roc_mbox.c | 483 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_mbox_priv.h | 215 ++++++++++++++++\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 3 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_utils.c | 7 +\n drivers/common/cnxk/roc_utils.h | 2 +\n drivers/common/cnxk/version.map | 2 +\n 10 files changed, 720 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_mbox.c\n create mode 100644 drivers/common/cnxk/roc_mbox_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 3e0678d..a7e7968 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -11,6 +11,7 @@ endif\n config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'\n deps = ['eal', 'pci', 'bus_pci', 'mbuf']\n sources = files('roc_irq.c',\n+\t\t'roc_mbox.c',\n \t\t'roc_model.c',\n \t\t'roc_platform.c',\n \t\t'roc_utils.c')\ndiff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex 2254677..c7f79f7 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -5,6 +5,9 @@\n #ifndef _ROC_DEV_PRIV_H\n #define _ROC_DEV_PRIV_H\n \n+extern uint16_t dev_rclk_freq;\n+extern uint16_t dev_sclk_freq;\n+\n int dev_irq_register(struct plt_intr_handle *intr_handle,\n \t\t plt_intr_callback_fn cb, void *data, unsigned int vec);\n void dev_irq_unregister(struct plt_intr_handle *intr_handle,\ndiff --git a/drivers/common/cnxk/roc_mbox.c b/drivers/common/cnxk/roc_mbox.c\nnew file mode 100644\nindex 0000000..6f4ee68\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mbox.c\n@@ -0,0 +1,483 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <errno.h>\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <string.h>\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+#define RVU_AF_AFPF_MBOX0 (0x02000)\n+#define RVU_AF_AFPF_MBOX1 (0x02008)\n+\n+#define RVU_PF_PFAF_MBOX0 (0xC00)\n+#define RVU_PF_PFAF_MBOX1 (0xC08)\n+\n+#define RVU_PF_VFX_PFVF_MBOX0 (0x0000)\n+#define RVU_PF_VFX_PFVF_MBOX1 (0x0008)\n+\n+#define RVU_VF_VFPF_MBOX0 (0x0000)\n+#define RVU_VF_VFPF_MBOX1 (0x0008)\n+\n+/* RCLK, SCLK in MHz */\n+uint16_t dev_rclk_freq;\n+uint16_t dev_sclk_freq;\n+\n+static inline uint16_t\n+msgs_offset(void)\n+{\n+\treturn PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+}\n+\n+void\n+mbox_fini(struct mbox *mbox)\n+{\n+\tmbox->reg_base = 0;\n+\tmbox->hwbase = 0;\n+\tplt_free(mbox->dev);\n+\tmbox->dev = NULL;\n+}\n+\n+void\n+mbox_reset(struct mbox *mbox, int devid)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_hdr *tx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);\n+\tstruct mbox_hdr *rx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n+\n+\tplt_spinlock_lock(&mdev->mbox_lock);\n+\tmdev->msg_size = 0;\n+\tmdev->rsp_size = 0;\n+\ttx_hdr->msg_size = 0;\n+\ttx_hdr->num_msgs = 0;\n+\trx_hdr->msg_size = 0;\n+\trx_hdr->num_msgs = 0;\n+\tplt_spinlock_unlock(&mdev->mbox_lock);\n+}\n+\n+int\n+mbox_init(struct mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,\n+\t int direction, int ndevs, uint64_t intr_offset)\n+{\n+\tstruct mbox_dev *mdev;\n+\tchar *var, *var_to;\n+\tint devid;\n+\n+\tmbox->intr_offset = intr_offset;\n+\tmbox->reg_base = reg_base;\n+\tmbox->hwbase = hwbase;\n+\n+\tswitch (direction) {\n+\tcase MBOX_DIR_AFPF:\n+\tcase MBOX_DIR_PFVF:\n+\t\tmbox->tx_start = MBOX_DOWN_TX_START;\n+\t\tmbox->rx_start = MBOX_DOWN_RX_START;\n+\t\tmbox->tx_size = MBOX_DOWN_TX_SIZE;\n+\t\tmbox->rx_size = MBOX_DOWN_RX_SIZE;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFAF:\n+\tcase MBOX_DIR_VFPF:\n+\t\tmbox->tx_start = MBOX_DOWN_RX_START;\n+\t\tmbox->rx_start = MBOX_DOWN_TX_START;\n+\t\tmbox->tx_size = MBOX_DOWN_RX_SIZE;\n+\t\tmbox->rx_size = MBOX_DOWN_TX_SIZE;\n+\t\tbreak;\n+\tcase MBOX_DIR_AFPF_UP:\n+\tcase MBOX_DIR_PFVF_UP:\n+\t\tmbox->tx_start = MBOX_UP_TX_START;\n+\t\tmbox->rx_start = MBOX_UP_RX_START;\n+\t\tmbox->tx_size = MBOX_UP_TX_SIZE;\n+\t\tmbox->rx_size = MBOX_UP_RX_SIZE;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFAF_UP:\n+\tcase MBOX_DIR_VFPF_UP:\n+\t\tmbox->tx_start = MBOX_UP_RX_START;\n+\t\tmbox->rx_start = MBOX_UP_TX_START;\n+\t\tmbox->tx_size = MBOX_UP_RX_SIZE;\n+\t\tmbox->rx_size = MBOX_UP_TX_SIZE;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tswitch (direction) {\n+\tcase MBOX_DIR_AFPF:\n+\tcase MBOX_DIR_AFPF_UP:\n+\t\tmbox->trigger = RVU_AF_AFPF_MBOX0;\n+\t\tmbox->tr_shift = 4;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFAF:\n+\tcase MBOX_DIR_PFAF_UP:\n+\t\tmbox->trigger = RVU_PF_PFAF_MBOX1;\n+\t\tmbox->tr_shift = 0;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFVF:\n+\tcase MBOX_DIR_PFVF_UP:\n+\t\tmbox->trigger = RVU_PF_VFX_PFVF_MBOX0;\n+\t\tmbox->tr_shift = 12;\n+\t\tbreak;\n+\tcase MBOX_DIR_VFPF:\n+\tcase MBOX_DIR_VFPF_UP:\n+\t\tmbox->trigger = RVU_VF_VFPF_MBOX1;\n+\t\tmbox->tr_shift = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tmbox->dev = plt_zmalloc(ndevs * sizeof(struct mbox_dev), ROC_ALIGN);\n+\tif (!mbox->dev) {\n+\t\tmbox_fini(mbox);\n+\t\treturn -ENOMEM;\n+\t}\n+\tmbox->ndevs = ndevs;\n+\tfor (devid = 0; devid < ndevs; devid++) {\n+\t\tmdev = &mbox->dev[devid];\n+\t\tmdev->mbase = (void *)(mbox->hwbase + (devid * MBOX_SIZE));\n+\t\tplt_spinlock_init(&mdev->mbox_lock);\n+\t\t/* Init header to reset value */\n+\t\tmbox_reset(mbox, devid);\n+\t}\n+\n+\tvar = getenv(\"ROC_CN10K_MBOX_TIMEOUT\");\n+\tvar_to = getenv(\"ROC_MBOX_TIMEOUT\");\n+\n+\tif (var)\n+\t\tmbox->rsp_tmo = atoi(var);\n+\telse if (var_to)\n+\t\tmbox->rsp_tmo = atoi(var_to);\n+\telse\n+\t\tmbox->rsp_tmo = MBOX_RSP_TIMEOUT;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * @internal\n+ * Allocate a message response\n+ */\n+struct mbox_msghdr *\n+mbox_alloc_msg_rsp(struct mbox *mbox, int devid, int size, int size_rsp)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_msghdr *msghdr = NULL;\n+\n+\tplt_spinlock_lock(&mdev->mbox_lock);\n+\tsize = PLT_ALIGN(size, MBOX_MSG_ALIGN);\n+\tsize_rsp = PLT_ALIGN(size_rsp, MBOX_MSG_ALIGN);\n+\t/* Check if there is space in mailbox */\n+\tif ((mdev->msg_size + size) > mbox->tx_size - msgs_offset())\n+\t\tgoto exit;\n+\tif ((mdev->rsp_size + size_rsp) > mbox->rx_size - msgs_offset())\n+\t\tgoto exit;\n+\tif (mdev->msg_size == 0)\n+\t\tmdev->num_msgs = 0;\n+\tmdev->num_msgs++;\n+\n+\tmsghdr = (struct mbox_msghdr *)(((uintptr_t)mdev->mbase +\n+\t\t\t\t\t mbox->tx_start + msgs_offset() +\n+\t\t\t\t\t mdev->msg_size));\n+\n+\t/* Clear the whole msg region */\n+\tmbox_memset(msghdr, 0, sizeof(*msghdr) + size);\n+\t/* Init message header with reset values */\n+\tmsghdr->ver = MBOX_VERSION;\n+\tmdev->msg_size += size;\n+\tmdev->rsp_size += size_rsp;\n+\tmsghdr->next_msgoff = mdev->msg_size + msgs_offset();\n+exit:\n+\tplt_spinlock_unlock(&mdev->mbox_lock);\n+\n+\treturn msghdr;\n+}\n+\n+/**\n+ * @internal\n+ * Send a mailbox message\n+ */\n+void\n+mbox_msg_send(struct mbox *mbox, int devid)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_hdr *tx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);\n+\tstruct mbox_hdr *rx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n+\n+\t/* Reset header for next messages */\n+\ttx_hdr->msg_size = mdev->msg_size;\n+\tmdev->msg_size = 0;\n+\tmdev->rsp_size = 0;\n+\tmdev->msgs_acked = 0;\n+\n+\t/* num_msgs != 0 signals to the peer that the buffer has a number of\n+\t * messages. So this should be written after copying txmem\n+\t */\n+\ttx_hdr->num_msgs = mdev->num_msgs;\n+\trx_hdr->num_msgs = 0;\n+\n+\t/* Sync mbox data into memory */\n+\tplt_wmb();\n+\n+\t/* The interrupt should be fired after num_msgs is written\n+\t * to the shared memory\n+\t */\n+\tplt_write64(1, (volatile void *)(mbox->reg_base +\n+\t\t\t\t\t (mbox->trigger |\n+\t\t\t\t\t (devid << mbox->tr_shift))));\n+}\n+\n+/**\n+ * @internal\n+ * Wait and get mailbox response\n+ */\n+int\n+mbox_get_rsp(struct mbox *mbox, int devid, void **msg)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_msghdr *msghdr;\n+\tuint64_t offset;\n+\tint rc;\n+\n+\trc = mbox_wait_for_rsp(mbox, devid);\n+\tif (rc < 0)\n+\t\treturn -EIO;\n+\n+\tplt_rmb();\n+\n+\toffset = mbox->rx_start +\n+\t\t PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n+\tif (msg != NULL)\n+\t\t*msg = msghdr;\n+\n+\treturn msghdr->rc;\n+}\n+\n+/**\n+ * Polling for given wait time to get mailbox response\n+ */\n+static int\n+mbox_poll(struct mbox *mbox, uint32_t wait)\n+{\n+\tuint32_t timeout = 0, sleep = 1;\n+\tuint32_t wait_us = wait * 1000;\n+\tuint64_t rsp_reg = 0;\n+\tuintptr_t reg_addr;\n+\n+\treg_addr = mbox->reg_base + mbox->intr_offset;\n+\tdo {\n+\t\trsp_reg = plt_read64(reg_addr);\n+\n+\t\tif (timeout >= wait_us)\n+\t\t\treturn -ETIMEDOUT;\n+\n+\t\tplt_delay_us(sleep);\n+\t\ttimeout += sleep;\n+\t} while (!rsp_reg);\n+\n+\tplt_rmb();\n+\n+\t/* Clear interrupt */\n+\tplt_write64(rsp_reg, reg_addr);\n+\n+\t/* Reset mbox */\n+\tmbox_reset(mbox, 0);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * @internal\n+ * Wait and get mailbox response with timeout\n+ */\n+int\n+mbox_get_rsp_tmo(struct mbox *mbox, int devid, void **msg, uint32_t tmo)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_msghdr *msghdr;\n+\tuint64_t offset;\n+\tint rc;\n+\n+\trc = mbox_wait_for_rsp_tmo(mbox, devid, tmo);\n+\tif (rc != 1)\n+\t\treturn -EIO;\n+\n+\tplt_rmb();\n+\n+\toffset = mbox->rx_start +\n+\t\t PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n+\tif (msg != NULL)\n+\t\t*msg = msghdr;\n+\n+\treturn msghdr->rc;\n+}\n+\n+static int\n+mbox_wait(struct mbox *mbox, int devid, uint32_t rst_timo)\n+{\n+\tvolatile struct mbox_dev *mdev = &mbox->dev[devid];\n+\tuint32_t timeout = 0, sleep = 1;\n+\n+\trst_timo = rst_timo * 1000; /* Milli seconds to micro seconds */\n+\twhile (mdev->num_msgs > mdev->msgs_acked) {\n+\t\tplt_delay_us(sleep);\n+\t\ttimeout += sleep;\n+\t\tif (timeout >= rst_timo) {\n+\t\t\tstruct mbox_hdr *tx_hdr =\n+\t\t\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase +\n+\t\t\t\t\t\t mbox->tx_start);\n+\t\t\tstruct mbox_hdr *rx_hdr =\n+\t\t\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase +\n+\t\t\t\t\t\t mbox->rx_start);\n+\n+\t\t\tplt_err(\"MBOX[devid: %d] message wait timeout %d, \"\n+\t\t\t\t\"num_msgs: %d, msgs_acked: %d \"\n+\t\t\t\t\"(tx/rx num_msgs: %d/%d), msg_size: %d, \"\n+\t\t\t\t\"rsp_size: %d\",\n+\t\t\t\tdevid, timeout, mdev->num_msgs,\n+\t\t\t\tmdev->msgs_acked, tx_hdr->num_msgs,\n+\t\t\t\trx_hdr->num_msgs, mdev->msg_size,\n+\t\t\t\tmdev->rsp_size);\n+\n+\t\t\treturn -EIO;\n+\t\t}\n+\t\tplt_rmb();\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+mbox_wait_for_rsp_tmo(struct mbox *mbox, int devid, uint32_t tmo)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tint rc = 0;\n+\n+\t/* Sync with mbox region */\n+\tplt_rmb();\n+\n+\tif (mbox->trigger == RVU_PF_VFX_PFVF_MBOX1 ||\n+\t mbox->trigger == RVU_PF_VFX_PFVF_MBOX0) {\n+\t\t/* In case of VF, Wait a bit more to account round trip delay */\n+\t\ttmo = tmo * 2;\n+\t}\n+\n+\t/* Wait message */\n+\tif (plt_thread_is_intr())\n+\t\trc = mbox_poll(mbox, tmo);\n+\telse\n+\t\trc = mbox_wait(mbox, devid, tmo);\n+\n+\tif (!rc)\n+\t\trc = mdev->num_msgs;\n+\n+\treturn rc;\n+}\n+\n+/**\n+ * @internal\n+ * Wait for the mailbox response\n+ */\n+int\n+mbox_wait_for_rsp(struct mbox *mbox, int devid)\n+{\n+\treturn mbox_wait_for_rsp_tmo(mbox, devid, mbox->rsp_tmo);\n+}\n+\n+int\n+mbox_get_availmem(struct mbox *mbox, int devid)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tint avail;\n+\n+\tplt_spinlock_lock(&mdev->mbox_lock);\n+\tavail = mbox->tx_size - mdev->msg_size - msgs_offset();\n+\tplt_spinlock_unlock(&mdev->mbox_lock);\n+\n+\treturn avail;\n+}\n+\n+int\n+send_ready_msg(struct mbox *mbox, uint16_t *pcifunc)\n+{\n+\tstruct ready_msg_rsp *rsp;\n+\tint rc;\n+\n+\tmbox_alloc_msg_ready(mbox);\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (rsp->hdr.ver != MBOX_VERSION) {\n+\t\tplt_err(\"Incompatible MBox versions(AF: 0x%04x Client: 0x%04x)\",\n+\t\t\trsp->hdr.ver, MBOX_VERSION);\n+\t\treturn -EPIPE;\n+\t}\n+\n+\tif (pcifunc)\n+\t\t*pcifunc = rsp->hdr.pcifunc;\n+\n+\t/* Save rclk & sclk freq */\n+\tif (!dev_rclk_freq || !dev_sclk_freq) {\n+\t\tdev_rclk_freq = rsp->rclk_freq;\n+\t\tdev_sclk_freq = rsp->sclk_freq;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+reply_invalid_msg(struct mbox *mbox, int devid, uint16_t pcifunc, uint16_t id)\n+{\n+\tstruct msg_rsp *rsp;\n+\n+\trsp = (struct msg_rsp *)mbox_alloc_msg(mbox, devid, sizeof(*rsp));\n+\tif (!rsp)\n+\t\treturn -ENOMEM;\n+\trsp->hdr.id = id;\n+\trsp->hdr.sig = MBOX_RSP_SIG;\n+\trsp->hdr.rc = MBOX_MSG_INVALID;\n+\trsp->hdr.pcifunc = pcifunc;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * @internal\n+ * Convert mail box ID to name\n+ */\n+const char *\n+mbox_id2name(uint16_t id)\n+{\n+\tswitch (id) {\n+\tdefault:\n+\t\treturn \"INVALID ID\";\n+#define M(_name, _id, _1, _2, _3) \\\n+\tcase _id: \\\n+\t\treturn #_name;\n+\t\tMBOX_MESSAGES\n+\t\tMBOX_UP_CGX_MESSAGES\n+#undef M\n+\t}\n+}\n+\n+int\n+mbox_id2size(uint16_t id)\n+{\n+\tswitch (id) {\n+\tdefault:\n+\t\treturn 0;\n+#define M(_1, _id, _2, _req_type, _3) \\\n+\tcase _id: \\\n+\t\treturn sizeof(struct _req_type);\n+\t\tMBOX_MESSAGES\n+\t\tMBOX_UP_CGX_MESSAGES\n+#undef M\n+\t}\n+}\ndiff --git a/drivers/common/cnxk/roc_mbox_priv.h b/drivers/common/cnxk/roc_mbox_priv.h\nnew file mode 100644\nindex 0000000..84516fb\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mbox_priv.h\n@@ -0,0 +1,215 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __ROC_MBOX_PRIV_H__\n+#define __ROC_MBOX_PRIV_H__\n+\n+#include <errno.h>\n+#include <stdbool.h>\n+#include <stdint.h>\n+\n+#define SZ_64K\t (64ULL * 1024ULL)\n+#define SZ_1K\t (1ULL * 1024ULL)\n+#define MBOX_SIZE SZ_64K\n+\n+/* AF/PF: PF initiated, PF/VF VF initiated */\n+#define MBOX_DOWN_RX_START 0\n+#define MBOX_DOWN_RX_SIZE (46 * SZ_1K)\n+#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)\n+#define MBOX_DOWN_TX_SIZE (16 * SZ_1K)\n+/* AF/PF: AF initiated, PF/VF PF initiated */\n+#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)\n+#define MBOX_UP_RX_SIZE\t SZ_1K\n+#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)\n+#define MBOX_UP_TX_SIZE\t SZ_1K\n+\n+#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE\n+#error \"Incorrect mailbox area sizes\"\n+#endif\n+\n+#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))\n+\n+#define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */\n+\n+#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */\n+\n+/* Mailbox directions */\n+#define MBOX_DIR_AFPF\t 0 /* AF replies to PF */\n+#define MBOX_DIR_PFAF\t 1 /* PF sends messages to AF */\n+#define MBOX_DIR_PFVF\t 2 /* PF replies to VF */\n+#define MBOX_DIR_VFPF\t 3 /* VF sends messages to PF */\n+#define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */\n+#define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */\n+#define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */\n+#define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */\n+\n+struct mbox_dev {\n+\tvoid *mbase; /* This dev's mbox region */\n+\tplt_spinlock_t mbox_lock;\n+\tuint16_t msg_size; /* Total msg size to be sent */\n+\tuint16_t rsp_size; /* Total rsp size to be sure the reply is ok */\n+\tuint16_t num_msgs; /* No of msgs sent or waiting for response */\n+\tuint16_t msgs_acked; /* No of msgs for which response is received */\n+};\n+\n+struct mbox {\n+\tuintptr_t hwbase; /* Mbox region advertised by HW */\n+\tuintptr_t reg_base; /* CSR base for this dev */\n+\tuint64_t trigger; /* Trigger mbox notification */\n+\tuint16_t tr_shift; /* Mbox trigger shift */\n+\tuint64_t rx_start; /* Offset of Rx region in mbox memory */\n+\tuint64_t tx_start; /* Offset of Tx region in mbox memory */\n+\tuint16_t rx_size; /* Size of Rx region */\n+\tuint16_t tx_size; /* Size of Tx region */\n+\tuint16_t ndevs;\t /* The number of peers */\n+\tstruct mbox_dev *dev;\n+\tuint64_t intr_offset; /* Offset to interrupt register */\n+\tuint32_t rsp_tmo;\n+};\n+\n+const char *mbox_id2name(uint16_t id);\n+int mbox_id2size(uint16_t id);\n+void mbox_reset(struct mbox *mbox, int devid);\n+int mbox_init(struct mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,\n+\t int direction, int ndevsi, uint64_t intr_offset);\n+void mbox_fini(struct mbox *mbox);\n+void mbox_msg_send(struct mbox *mbox, int devid);\n+int mbox_wait_for_rsp(struct mbox *mbox, int devid);\n+int mbox_wait_for_rsp_tmo(struct mbox *mbox, int devid, uint32_t tmo);\n+int mbox_get_rsp(struct mbox *mbox, int devid, void **msg);\n+int mbox_get_rsp_tmo(struct mbox *mbox, int devid, void **msg, uint32_t tmo);\n+int mbox_get_availmem(struct mbox *mbox, int devid);\n+struct mbox_msghdr *mbox_alloc_msg_rsp(struct mbox *mbox, int devid, int size,\n+\t\t\t\t int size_rsp);\n+\n+static inline struct mbox_msghdr *\n+mbox_alloc_msg(struct mbox *mbox, int devid, int size)\n+{\n+\treturn mbox_alloc_msg_rsp(mbox, devid, size, 0);\n+}\n+\n+static inline void\n+mbox_req_init(uint16_t mbox_id, void *msghdr)\n+{\n+\tstruct mbox_msghdr *hdr = msghdr;\n+\n+\thdr->sig = MBOX_REQ_SIG;\n+\thdr->ver = MBOX_VERSION;\n+\thdr->id = mbox_id;\n+\thdr->pcifunc = 0;\n+}\n+\n+static inline void\n+mbox_rsp_init(uint16_t mbox_id, void *msghdr)\n+{\n+\tstruct mbox_msghdr *hdr = msghdr;\n+\n+\thdr->sig = MBOX_RSP_SIG;\n+\thdr->rc = -ETIMEDOUT;\n+\thdr->id = mbox_id;\n+}\n+\n+static inline bool\n+mbox_nonempty(struct mbox *mbox, int devid)\n+{\n+\tstruct mbox_dev *mdev = &mbox->dev[devid];\n+\tbool ret;\n+\n+\tplt_spinlock_lock(&mdev->mbox_lock);\n+\tret = mdev->num_msgs != 0;\n+\tplt_spinlock_unlock(&mdev->mbox_lock);\n+\n+\treturn ret;\n+}\n+\n+static inline int\n+mbox_process(struct mbox *mbox)\n+{\n+\tmbox_msg_send(mbox, 0);\n+\treturn mbox_get_rsp(mbox, 0, NULL);\n+}\n+\n+static inline int\n+mbox_process_msg(struct mbox *mbox, void **msg)\n+{\n+\tmbox_msg_send(mbox, 0);\n+\treturn mbox_get_rsp(mbox, 0, msg);\n+}\n+\n+static inline int\n+mbox_process_tmo(struct mbox *mbox, uint32_t tmo)\n+{\n+\tmbox_msg_send(mbox, 0);\n+\treturn mbox_get_rsp_tmo(mbox, 0, NULL, tmo);\n+}\n+\n+static inline int\n+mbox_process_msg_tmo(struct mbox *mbox, void **msg, uint32_t tmo)\n+{\n+\tmbox_msg_send(mbox, 0);\n+\treturn mbox_get_rsp_tmo(mbox, 0, msg, tmo);\n+}\n+\n+int send_ready_msg(struct mbox *mbox, uint16_t *pf_func /* out */);\n+int reply_invalid_msg(struct mbox *mbox, int devid, uint16_t pf_func,\n+\t\t uint16_t id);\n+\n+#define M(_name, _id, _fn_name, _req_type, _rsp_type) \\\n+\tstatic inline struct _req_type *mbox_alloc_msg_##_fn_name( \\\n+\t\tstruct mbox *mbox) \\\n+\t{ \\\n+\t\tstruct _req_type *req; \\\n+\t\treq = (struct _req_type *)mbox_alloc_msg_rsp( \\\n+\t\t\tmbox, 0, sizeof(struct _req_type), \\\n+\t\t\tsizeof(struct _rsp_type)); \\\n+\t\tif (!req) \\\n+\t\t\treturn NULL; \\\n+\t\treq->hdr.sig = MBOX_REQ_SIG; \\\n+\t\treq->hdr.id = _id; \\\n+\t\tplt_mbox_dbg(\"id=0x%x (%s)\", req->hdr.id, \\\n+\t\t\t mbox_id2name(req->hdr.id)); \\\n+\t\treturn req; \\\n+\t}\n+\n+MBOX_MESSAGES\n+#undef M\n+\n+/* This is required for copy operations from device memory which do not work on\n+ * addresses which are unaligned to 16B. This is because of specific\n+ * optimizations to libc memcpy.\n+ */\n+static inline volatile void *\n+mbox_memcpy(volatile void *d, const volatile void *s, size_t l)\n+{\n+\tconst volatile uint8_t *sb;\n+\tvolatile uint8_t *db;\n+\tsize_t i;\n+\n+\tif (!d || !s)\n+\t\treturn NULL;\n+\tdb = (volatile uint8_t *)d;\n+\tsb = (const volatile uint8_t *)s;\n+\tfor (i = 0; i < l; i++)\n+\t\tdb[i] = sb[i];\n+\treturn d;\n+}\n+\n+/* This is required for memory operations from device memory which do not\n+ * work on addresses which are unaligned to 16B. This is because of specific\n+ * optimizations to libc memset.\n+ */\n+static inline void\n+mbox_memset(volatile void *d, uint8_t val, size_t l)\n+{\n+\tvolatile uint8_t *db;\n+\tsize_t i = 0;\n+\n+\tif (!d || !l)\n+\t\treturn;\n+\tdb = (volatile uint8_t *)d;\n+\tfor (i = 0; i < l; i++)\n+\t\tdb[i] = val;\n+}\n+\n+#endif /* __ROC_MBOX_PRIV_H__ */\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 43ee7a1..4a32978 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -54,3 +54,4 @@ roc_plt_init(void)\n }\n \n RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 4fa4631..c4b6258 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -133,6 +133,8 @@\n \n /* Log */\n extern int cnxk_logtype_base;\n+extern int cnxk_logtype_mbox;\n+\n #define plt_err(fmt, args...) \\\n \tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt \"\\n\", ##args)\n@@ -148,6 +150,7 @@ extern int cnxk_logtype_base;\n \t\t##args)\n \n #define plt_base_dbg(fmt, ...)\tplt_dbg(base, fmt, ##__VA_ARGS__)\n+#define plt_mbox_dbg(fmt, ...)\tplt_dbg(mbox, fmt, ##__VA_ARGS__)\n \n #ifdef __cplusplus\n #define CNXK_PCI_ID(subsystem_dev, dev)\t\t\t\t\\\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex cd87035..c385f11 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -8,6 +8,9 @@\n /* Utils */\n #include \"roc_util_priv.h\"\n \n+/* Mbox */\n+#include \"roc_mbox_priv.h\"\n+\n /* Dev */\n #include \"roc_dev_priv.h\"\n \ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex c48f027..b21064a 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -33,3 +33,10 @@ roc_error_msg_get(int errorcode)\n \n \treturn err_msg;\n }\n+\n+void\n+roc_clk_freq_get(uint16_t *rclk_freq, uint16_t *sclk_freq)\n+{\n+\t*rclk_freq = dev_rclk_freq;\n+\t*sclk_freq = dev_sclk_freq;\n+}\ndiff --git a/drivers/common/cnxk/roc_utils.h b/drivers/common/cnxk/roc_utils.h\nindex 634810e..32d44ae 100644\n--- a/drivers/common/cnxk/roc_utils.h\n+++ b/drivers/common/cnxk/roc_utils.h\n@@ -10,4 +10,6 @@\n /* Utils */\n const char *__roc_api roc_error_msg_get(int errorcode);\n \n+void __roc_api roc_clk_freq_get(uint16_t *rclk_freq, uint16_t *sclk_freq);\n+\n #endif /* _ROC_UTILS_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex e2cb838..8ea8e95 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -2,6 +2,8 @@ INTERNAL {\n \tglobal:\n \n \tcnxk_logtype_base;\n+\tcnxk_logtype_mbox;\n+\troc_clk_freq_get;\n \troc_error_msg_get;\n \troc_model;\n \troc_plt_init;\n", "prefixes": [ "v4", "07/52" ] }