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GET /api/patches/90619/?format=api
{ "id": 90619, "url": "http://patches.dpdk.org/api/patches/90619/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-7-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406114131.25874-7-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406114131.25874-7-ndabilpuram@marvell.com", "date": "2021-04-06T11:40:45", "name": "[v4,06/52] common/cnxk: add mbox request and response definitions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3ba0d9a3bba09ddd99b71364801abe63099a6eaa", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-7-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16128, "url": "http://patches.dpdk.org/api/series/16128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16128", "date": "2021-04-06T11:40:39", "name": "Add Marvell CNXK common driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90619/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/90619/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8D5B5A0546;\n\tTue, 6 Apr 2021 13:42:44 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B127F140ED8;\n\tTue, 6 Apr 2021 13:42:02 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 055C6140DFB\n for <dev@dpdk.org>; Tue, 6 Apr 2021 13:42:00 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136BeUHg017940 for <dev@dpdk.org>; Tue, 6 Apr 2021 04:42:00 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 37redm9bec-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 04:41:59 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 04:41:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 04:41:57 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 5EFD53F7040;\n Tue, 6 Apr 2021 04:41:54 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=saskrqh1U4KElW7PRbDn6YVMiaM/kNt0KkYppXF0uiE=;\n b=eL3kZ2pJ2F2kRi70f+3iF2KpSZ3bE/BpD9vMp5xcyFKb7zr1gJtFkRNoCKOleGqnpJ3g\n vb5RWOzOeVJNoGDQq7LNN8rAyFSTS44FZ9DaEtq9lFDGqXWvCdmPww9jJJEcAU+c/yGP\n CRHRUqPQq6d+v8K5nC8JI4e2LwSFAfFLehHFbrdnuaqsGXmfvx06jMB1zdlJQ8320NdD\n yuZ2VKHYbpFXVa6KDevpSjobUeE/FIwD6z5YYKvZub202vz7zsd+KLogPoInA11YJPwi\n sDVCgWR8fiGnQ8KF4OTs0H3CWEyXdcS7Uo9s2XbfBpi0uVyOlOEs0QGNIcEXCdGMMGmw vA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Harman Kalra <hkalra@marvell.com>,\n Shijith Thotton <sthotton@marvell.com>", "Date": "Tue, 6 Apr 2021 17:10:45 +0530", "Message-ID": "<20210406114131.25874-7-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406114131.25874-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406114131.25874-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "wYApFGYvrVsqKDaDkgOg_w8pmLub30cX", "X-Proofpoint-ORIG-GUID": "wYApFGYvrVsqKDaDkgOg_w8pmLub30cX", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_02:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 06/52] common/cnxk: add mbox request and\n response definitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe admin function driver sits in Linux kernel as mailbox\nserver. The DPDK AF mailbox client, send the message to mailbox\nserver to complete the administrative task such as get mac\naddress.\n\nThis patch adds mailbox request and response definition of\nexisting mailbox defined between AF driver and DPDK driver.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_mbox.h | 1735 ++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 1738 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_mbox.h", "diff": "diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 70d9c4a..f2f1f5e 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -76,6 +76,9 @@\n /* Model */\n #include \"roc_model.h\"\n \n+/* Mbox */\n+#include \"roc_mbox.h\"\n+\n /* Utils */\n #include \"roc_utils.h\"\n \ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nnew file mode 100644\nindex 0000000..4864c76\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -0,0 +1,1735 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __ROC_MBOX_H__\n+#define __ROC_MBOX_H__\n+\n+#include <errno.h>\n+#include <stdbool.h>\n+#include <stdint.h>\n+\n+/* Device memory does not support unaligned access, instruct compiler to\n+ * not optimize the memory access when working with mailbox memory.\n+ */\n+#define __io volatile\n+\n+/* Header which precedes all mbox messages */\n+struct mbox_hdr {\n+\tuint64_t __io msg_size; /* Total msgs size embedded */\n+\tuint16_t __io num_msgs; /* No of msgs embedded */\n+};\n+\n+/* Header which precedes every msg and is also part of it */\n+struct mbox_msghdr {\n+\tuint16_t __io pcifunc; /* Who's sending this msg */\n+\tuint16_t __io id; /* Mbox message ID */\n+#define MBOX_REQ_SIG (0xdead)\n+#define MBOX_RSP_SIG (0xbeef)\n+\t/* Signature, for validating corrupted msgs */\n+\tuint16_t __io sig;\n+#define MBOX_VERSION (0x000a)\n+\t/* Version of msg's structure for this ID */\n+\tuint16_t __io ver;\n+\t/* Offset of next msg within mailbox region */\n+\tuint16_t __io next_msgoff;\n+\tint __io rc; /* Msg processed response code */\n+};\n+\n+/* Mailbox message types */\n+#define MBOX_MSG_MASK\t 0xFFFF\n+#define MBOX_MSG_INVALID 0xFFFE\n+#define MBOX_MSG_MAX\t 0xFFFF\n+\n+#define MBOX_MESSAGES \\\n+\t/* Generic mbox IDs (range 0x000 - 0x1FF) */ \\\n+\tM(READY, 0x001, ready, msg_req, ready_msg_rsp) \\\n+\tM(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp) \\\n+\tM(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp) \\\n+\tM(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \\\n+\tM(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \\\n+\tM(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \\\n+\tM(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \\\n+\tM(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \\\n+\tM(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \\\n+\tM(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \\\n+\t msg_rsp) \\\n+\t/* CGX mbox IDs (range 0x200 - 0x3FF) */ \\\n+\tM(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \\\n+\tM(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \\\n+\tM(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \\\n+\tM(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \\\n+\t cgx_mac_addr_set_or_get) \\\n+\tM(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \\\n+\t cgx_mac_addr_set_or_get) \\\n+\tM(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \\\n+\tM(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \\\n+\tM(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \\\n+\tM(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \\\n+\tM(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, \\\n+\t cgx_link_info_msg) \\\n+\tM(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \\\n+\tM(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \\\n+\tM(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \\\n+\tM(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \\\n+\tM(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \\\n+\t cgx_pause_frm_cfg) \\\n+\tM(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \\\n+\tM(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \\\n+\tM(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \\\n+\t cgx_mac_addr_add_rsp) \\\n+\tM(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \\\n+\t msg_rsp) \\\n+\tM(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \\\n+\t cgx_max_dmac_entries_get_rsp) \\\n+\tM(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \\\n+\t cgx_set_link_state_msg, msg_rsp) \\\n+\tM(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \\\n+\t cgx_phy_mod_type) \\\n+\tM(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \\\n+\t msg_rsp) \\\n+\tM(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \\\n+\tM(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req, \\\n+\t cgx_set_link_mode_rsp) \\\n+\tM(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, \\\n+\t msg_rsp) \\\n+\tM(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \\\n+\tM(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \\\n+\t/* NPA mbox IDs (range 0x400 - 0x5FF) */ \\\n+\tM(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \\\n+\t npa_lf_alloc_rsp) \\\n+\tM(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \\\n+\tM(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \\\n+\tM(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, \\\n+\t msg_rsp) \\\n+\t/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \\\n+\tM(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \\\n+\t sso_lf_alloc_rsp) \\\n+\tM(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \\\n+\tM(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp) \\\n+\tM(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \\\n+\tM(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \\\n+\t msg_rsp) \\\n+\tM(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \\\n+\t msg_rsp) \\\n+\tM(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \\\n+\t sso_grp_priority) \\\n+\tM(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \\\n+\tM(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \\\n+\t msg_rsp) \\\n+\tM(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \\\n+\t sso_grp_stats) \\\n+\tM(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \\\n+\t sso_hws_stats) \\\n+\tM(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \\\n+\t sso_hw_xaq_release, msg_rsp) \\\n+\t/* TIM mbox IDs (range 0x800 - 0x9FF) */ \\\n+\tM(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \\\n+\t tim_lf_alloc_rsp) \\\n+\tM(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \\\n+\tM(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp) \\\n+\tM(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \\\n+\t tim_enable_rsp) \\\n+\tM(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \\\n+\t/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \\\n+\tM(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, msg_rsp) \\\n+\tM(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \\\n+\tM(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \\\n+\t cpt_rd_wr_reg_msg) \\\n+\tM(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \\\n+\t cpt_set_crypto_grp_req_msg, msg_rsp) \\\n+\tM(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \\\n+\t cpt_inline_ipsec_cfg_msg, msg_rsp) \\\n+\tM(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \\\n+\tM(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \\\n+\t msg_rsp) \\\n+\tM(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \\\n+\t cpt_rx_inline_lf_cfg_msg, msg_rsp) \\\n+\tM(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \\\n+\tM(CPT_GET_ENG_GRP, 0xBFF, cpt_eng_grp_get, cpt_eng_grp_req, \\\n+\t cpt_eng_grp_rsp) \\\n+\t/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \\\n+\tM(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \\\n+\t npc_mcam_alloc_entry_req, npc_mcam_alloc_entry_rsp) \\\n+\tM(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \\\n+\t npc_mcam_free_entry_req, msg_rsp) \\\n+\tM(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \\\n+\t npc_mcam_write_entry_req, msg_rsp) \\\n+\tM(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \\\n+\t npc_mcam_ena_dis_entry_req, msg_rsp) \\\n+\tM(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \\\n+\t npc_mcam_ena_dis_entry_req, msg_rsp) \\\n+\tM(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \\\n+\t npc_mcam_shift_entry_req, npc_mcam_shift_entry_rsp) \\\n+\tM(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \\\n+\t npc_mcam_alloc_counter_req, npc_mcam_alloc_counter_rsp) \\\n+\tM(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \\\n+\t npc_mcam_oper_counter_req, msg_rsp) \\\n+\tM(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \\\n+\t npc_mcam_unmap_counter_req, msg_rsp) \\\n+\tM(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \\\n+\t npc_mcam_oper_counter_req, msg_rsp) \\\n+\tM(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \\\n+\t npc_mcam_oper_counter_req, npc_mcam_oper_counter_rsp) \\\n+\tM(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, \\\n+\t npc_mcam_alloc_and_write_entry, npc_mcam_alloc_and_write_entry_req, \\\n+\t npc_mcam_alloc_and_write_entry_rsp) \\\n+\tM(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \\\n+\t npc_get_kex_cfg_rsp) \\\n+\tM(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, npc_install_flow_req, \\\n+\t npc_install_flow_rsp) \\\n+\tM(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, npc_delete_flow_req, \\\n+\t msg_rsp) \\\n+\tM(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \\\n+\t npc_mcam_read_entry_req, npc_mcam_read_entry_rsp) \\\n+\tM(NPC_SET_PKIND, 0x6010, npc_set_pkind, npc_set_pkind, msg_rsp) \\\n+\tM(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \\\n+\t npc_mcam_read_base_rule_rsp) \\\n+\t/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \\\n+\tM(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \\\n+\t nix_lf_alloc_rsp) \\\n+\tM(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \\\n+\tM(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \\\n+\tM(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \\\n+\t msg_rsp) \\\n+\tM(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \\\n+\t nix_txsch_alloc_rsp) \\\n+\tM(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \\\n+\tM(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \\\n+\t nix_txschq_config) \\\n+\tM(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \\\n+\tM(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \\\n+\tM(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \\\n+\t nix_rss_flowkey_cfg, nix_rss_flowkey_cfg_rsp) \\\n+\tM(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \\\n+\t msg_rsp) \\\n+\tM(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \\\n+\tM(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \\\n+\tM(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \\\n+\tM(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \\\n+\tM(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \\\n+\t nix_mark_format_cfg, nix_mark_format_cfg_rsp) \\\n+\tM(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \\\n+\tM(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \\\n+\t nix_lso_format_cfg_rsp) \\\n+\tM(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \\\n+\t msg_rsp) \\\n+\tM(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \\\n+\t msg_rsp) \\\n+\tM(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \\\n+\t msg_rsp) \\\n+\tM(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \\\n+\t nix_bp_cfg_rsp) \\\n+\tM(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \\\n+\tM(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \\\n+\t nix_get_mac_addr_rsp) \\\n+\tM(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \\\n+\t nix_inline_ipsec_cfg, msg_rsp) \\\n+\tM(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \\\n+\t nix_inline_ipsec_lf_cfg, msg_rsp) \\\n+\tM(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \\\n+\t nix_cn10k_aq_enq_rsp) \\\n+\tM(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info)\n+\n+/* Messages initiated by AF (range 0xC00 - 0xDFF) */\n+#define MBOX_UP_CGX_MESSAGES \\\n+\tM(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \\\n+\tM(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)\n+\n+enum {\n+#define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,\n+\tMBOX_MESSAGES MBOX_UP_CGX_MESSAGES\n+#undef M\n+};\n+\n+/* Mailbox message formats */\n+\n+#define RVU_DEFAULT_PF_FUNC 0xFFFF\n+\n+/* Generic request msg used for those mbox messages which\n+ * don't send any data in the request.\n+ */\n+struct msg_req {\n+\tstruct mbox_msghdr hdr;\n+};\n+\n+/* Generic response msg used a ack or response for those mbox\n+ * messages which does not have a specific rsp msg format.\n+ */\n+struct msg_rsp {\n+\tstruct mbox_msghdr hdr;\n+};\n+\n+/* RVU mailbox error codes\n+ * Range 256 - 300.\n+ */\n+enum rvu_af_status {\n+\tRVU_INVALID_VF_ID = -256,\n+};\n+\n+struct ready_msg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io sclk_freq; /* SCLK frequency */\n+\tuint16_t __io rclk_freq; /* RCLK frequency */\n+};\n+\n+/* Struct to set pkind */\n+struct npc_set_pkind {\n+\tstruct mbox_msghdr hdr;\n+#define ROC_PRIV_FLAGS_DEFAULT BIT_ULL(0)\n+#define ROC_PRIV_FLAGS_EDSA BIT_ULL(1)\n+#define ROC_PRIV_FLAGS_HIGIG BIT_ULL(2)\n+#define ROC_PRIV_FLAGS_LEN_90B BIT_ULL(3)\n+#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)\n+\tuint64_t __io mode;\n+#define PKIND_TX BIT_ULL(0)\n+#define PKIND_RX BIT_ULL(1)\n+\tuint8_t __io dir;\n+\tuint8_t __io pkind; /* valid only in case custom flag */\n+};\n+\n+/* Structure for requesting resource provisioning.\n+ * 'modify' flag to be used when either requesting more\n+ * or to detach partial of a certain resource type.\n+ * Rest of the fields specify how many of what type to\n+ * be attached.\n+ * To request LFs from two blocks of same type this mailbox\n+ * can be sent twice as below:\n+ * struct rsrc_attach *attach;\n+ * .. Allocate memory for message ..\n+ * attach->cptlfs = 3; <3 LFs from CPT0>\n+ * .. Send message ..\n+ * .. Allocate memory for message ..\n+ * attach->modify = 1;\n+ * attach->cpt_blkaddr = BLKADDR_CPT1;\n+ * attach->cptlfs = 2; <2 LFs from CPT1>\n+ * .. Send message ..\n+ */\n+struct rsrc_attach_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io modify : 1;\n+\tuint8_t __io npalf : 1;\n+\tuint8_t __io nixlf : 1;\n+\tuint16_t __io sso;\n+\tuint16_t __io ssow;\n+\tuint16_t __io timlfs;\n+\tuint16_t __io cptlfs;\n+\tuint16_t __io reelfs;\n+\t/* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */\n+\tint __io cpt_blkaddr;\n+\t/* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */\n+\tint __io ree_blkaddr;\n+};\n+\n+/* Structure for relinquishing resources.\n+ * 'partial' flag to be used when relinquishing all resources\n+ * but only of a certain type. If not set, all resources of all\n+ * types provisioned to the RVU function will be detached.\n+ */\n+struct rsrc_detach_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io partial : 1;\n+\tuint8_t __io npalf : 1;\n+\tuint8_t __io nixlf : 1;\n+\tuint8_t __io sso : 1;\n+\tuint8_t __io ssow : 1;\n+\tuint8_t __io timlfs : 1;\n+\tuint8_t __io cptlfs : 1;\n+\tuint8_t __io reelfs : 1;\n+};\n+\n+/* NIX Transmit schedulers */\n+#define NIX_TXSCH_LVL_SMQ 0x0\n+#define NIX_TXSCH_LVL_MDQ 0x0\n+#define NIX_TXSCH_LVL_TL4 0x1\n+#define NIX_TXSCH_LVL_TL3 0x2\n+#define NIX_TXSCH_LVL_TL2 0x3\n+#define NIX_TXSCH_LVL_TL1 0x4\n+#define NIX_TXSCH_LVL_CNT 0x5\n+\n+/*\n+ * Number of resources available to the caller.\n+ * In reply to MBOX_MSG_FREE_RSRC_CNT.\n+ */\n+struct free_rsrcs_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io schq[NIX_TXSCH_LVL_CNT];\n+\tuint16_t __io sso;\n+\tuint16_t __io tim;\n+\tuint16_t __io ssow;\n+\tuint16_t __io cpt;\n+\tuint8_t __io npa;\n+\tuint8_t __io nix;\n+\tuint16_t __io schq_nix1[NIX_TXSCH_LVL_CNT];\n+\tuint8_t __io nix1;\n+\tuint8_t __io cpt1;\n+\tuint8_t __io ree0;\n+\tuint8_t __io ree1;\n+};\n+\n+#define MSIX_VECTOR_INVALID 0xFFFF\n+#define MAX_RVU_BLKLF_CNT 256\n+\n+struct msix_offset_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io npa_msixoff;\n+\tuint16_t __io nix_msixoff;\n+\tuint16_t __io sso;\n+\tuint16_t __io ssow;\n+\tuint16_t __io timlfs;\n+\tuint16_t __io cptlfs;\n+\tuint16_t __io sso_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __io ssow_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __io timlf_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __io cptlf_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __io cpt1_lfs;\n+\tuint16_t __io ree0_lfs;\n+\tuint16_t __io ree1_lfs;\n+\tuint16_t __io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];\n+};\n+\n+struct lmtst_tbl_setup_req {\n+\tstruct mbox_msghdr hdr;\n+\n+\tuint64_t __io dis_sched_early_comp : 1;\n+\tuint64_t __io sched_ena : 1;\n+\tuint64_t __io dis_line_pref : 1;\n+\tuint64_t __io ssow_pf_func : 13;\n+\tuint16_t __io pcifunc;\n+};\n+\n+/* CGX mbox message formats */\n+\n+struct cgx_stats_rsp {\n+\tstruct mbox_msghdr hdr;\n+#define CGX_RX_STATS_COUNT 13\n+#define CGX_TX_STATS_COUNT 18\n+\tuint64_t __io rx_stats[CGX_RX_STATS_COUNT];\n+\tuint64_t __io tx_stats[CGX_TX_STATS_COUNT];\n+};\n+\n+struct rpm_stats_rsp {\n+\tstruct mbox_msghdr hdr;\n+#define RPM_RX_STATS_COUNT 43\n+#define RPM_TX_STATS_COUNT 34\n+\tuint64_t __io rx_stats[RPM_RX_STATS_COUNT];\n+\tuint64_t __io tx_stats[RPM_TX_STATS_COUNT];\n+};\n+\n+struct cgx_fec_stats_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io fec_corr_blks;\n+\tuint64_t __io fec_uncorr_blks;\n+};\n+\n+/* Structure for requesting the operation for\n+ * setting/getting mac address in the CGX interface\n+ */\n+struct cgx_mac_addr_set_or_get {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];\n+};\n+\n+/* Structure for requesting the operation to\n+ * add DMAC filter entry into CGX interface\n+ */\n+struct cgx_mac_addr_add_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];\n+};\n+\n+/* Structure for response against the operation to\n+ * add DMAC filter entry into CGX interface\n+ */\n+struct cgx_mac_addr_add_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io index;\n+};\n+\n+/* Structure for requesting the operation to\n+ * delete DMAC filter entry from CGX interface\n+ */\n+struct cgx_mac_addr_del_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io index;\n+};\n+\n+/* Structure for response against the operation to\n+ * get maximum supported DMAC filter entries\n+ */\n+struct cgx_max_dmac_entries_get_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io max_dmac_filters;\n+};\n+\n+struct cgx_link_user_info {\n+\tuint64_t __io link_up : 1;\n+\tuint64_t __io full_duplex : 1;\n+\tuint64_t __io lmac_type_id : 4;\n+\tuint64_t __io speed : 20; /* speed in Mbps */\n+\tuint64_t __io an : 1;\t /* AN supported or not */\n+\tuint64_t __io fec : 2;\t /* FEC type if enabled else 0 */\n+\tuint64_t __io port : 8;\n+#define LMACTYPE_STR_LEN 16\n+\tchar lmac_type[LMACTYPE_STR_LEN];\n+};\n+\n+struct cgx_link_info_msg {\n+\tstruct mbox_msghdr hdr;\n+\tstruct cgx_link_user_info link_info;\n+};\n+\n+struct cgx_ptp_rx_info_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io ptp_en;\n+};\n+\n+struct cgx_pause_frm_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io set;\n+\t/* set = 1 if the request is to config pause frames */\n+\t/* set = 0 if the request is to fetch pause frames config */\n+\tuint8_t __io rx_pause;\n+\tuint8_t __io tx_pause;\n+};\n+\n+struct sfp_eeprom_s {\n+#define SFP_EEPROM_SIZE 256\n+\tuint16_t __io sff_id;\n+\tuint8_t __io buf[SFP_EEPROM_SIZE];\n+\tuint64_t __io reserved;\n+};\n+\n+enum fec_type {\n+\tROC_FEC_NONE,\n+\tROC_FEC_BASER,\n+\tROC_FEC_RS,\n+};\n+\n+struct phy_s {\n+\tuint64_t __io can_change_mod_type : 1;\n+\tuint64_t __io mod_type : 1;\n+};\n+\n+struct cgx_lmac_fwdata_s {\n+\tuint16_t __io rw_valid;\n+\tuint64_t __io supported_fec;\n+\tuint64_t __io supported_an;\n+\tuint64_t __io supported_link_modes;\n+\t/* Only applicable if AN is supported */\n+\tuint64_t __io advertised_fec;\n+\tuint64_t __io advertised_link_modes;\n+\t/* Only applicable if SFP/QSFP slot is present */\n+\tstruct sfp_eeprom_s sfp_eeprom;\n+\tstruct phy_s phy;\n+#define LMAC_FWDATA_RESERVED_MEM 1023\n+\tuint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM];\n+};\n+\n+struct cgx_fw_data {\n+\tstruct mbox_msghdr hdr;\n+\tstruct cgx_lmac_fwdata_s fwdata;\n+};\n+\n+struct fec_mode {\n+\tstruct mbox_msghdr hdr;\n+\tint __io fec;\n+};\n+\n+struct cgx_set_link_state_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io enable;\n+};\n+\n+struct cgx_phy_mod_type {\n+\tstruct mbox_msghdr hdr;\n+\tint __io mod;\n+};\n+\n+struct cgx_set_link_mode_args {\n+\tuint32_t __io speed;\n+\tuint8_t __io duplex;\n+\tuint8_t __io an;\n+\tuint8_t __io ports;\n+\tuint64_t __io mode;\n+};\n+\n+struct cgx_set_link_mode_req {\n+\tstruct mbox_msghdr hdr;\n+\tstruct cgx_set_link_mode_args args;\n+};\n+\n+struct cgx_set_link_mode_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tint __io status;\n+};\n+\n+/* NPA mbox message formats */\n+\n+/* NPA mailbox error codes\n+ * Range 301 - 400.\n+ */\n+enum npa_af_status {\n+\tNPA_AF_ERR_PARAM = -301,\n+\tNPA_AF_ERR_AQ_FULL = -302,\n+\tNPA_AF_ERR_AQ_ENQUEUE = -303,\n+\tNPA_AF_ERR_AF_LF_INVALID = -304,\n+\tNPA_AF_ERR_AF_LF_ALLOC = -305,\n+\tNPA_AF_ERR_LF_RESET = -306,\n+};\n+\n+#define NPA_AURA_SZ_0\t 0\n+#define NPA_AURA_SZ_128\t 1\n+#define NPA_AURA_SZ_256\t 2\n+#define NPA_AURA_SZ_512\t 3\n+#define NPA_AURA_SZ_1K\t 4\n+#define NPA_AURA_SZ_2K\t 5\n+#define NPA_AURA_SZ_4K\t 6\n+#define NPA_AURA_SZ_8K\t 7\n+#define NPA_AURA_SZ_16K\t 8\n+#define NPA_AURA_SZ_32K\t 9\n+#define NPA_AURA_SZ_64K\t 10\n+#define NPA_AURA_SZ_128K 11\n+#define NPA_AURA_SZ_256K 12\n+#define NPA_AURA_SZ_512K 13\n+#define NPA_AURA_SZ_1M\t 14\n+#define NPA_AURA_SZ_MAX\t 15\n+\n+/* For NPA LF context alloc and init */\n+struct npa_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __io node;\n+\tint __io aura_sz;\t/* No of auras. See NPA_AURA_SZ_* */\n+\tuint32_t __io nr_pools; /* No of pools */\n+\tuint64_t __io way_mask;\n+};\n+\n+struct npa_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io stack_pg_ptrs; /* No of ptrs per stack page */\n+\tuint32_t __io stack_pg_bytes; /* Size of stack page */\n+\tuint16_t __io qints;\t /* NPA_AF_CONST::QINTS */\n+\tuint8_t __io cache_lines; /* Batch Alloc DMA */\n+};\n+\n+/* NPA AQ enqueue msg */\n+struct npa_aq_enq_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io aura_id;\n+\tuint8_t __io ctype;\n+\tuint8_t __io op;\n+\tunion {\n+\t\t/* Valid when op == WRITE/INIT and ctype == AURA.\n+\t\t * LF fills the pool_id in aura.pool_addr. AF will translate\n+\t\t * the pool_id to pool context pointer.\n+\t\t */\n+\t\t__io struct npa_aura_s aura;\n+\t\t/* Valid when op == WRITE/INIT and ctype == POOL */\n+\t\t__io struct npa_pool_s pool;\n+\t};\n+\t/* Mask data when op == WRITE (1=write, 0=don't write) */\n+\tunion {\n+\t\t/* Valid when op == WRITE and ctype == AURA */\n+\t\t__io struct npa_aura_s aura_mask;\n+\t\t/* Valid when op == WRITE and ctype == POOL */\n+\t\t__io struct npa_pool_s pool_mask;\n+\t};\n+};\n+\n+struct npa_aq_enq_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tunion {\n+\t\t/* Valid when op == READ and ctype == AURA */\n+\t\t__io struct npa_aura_s aura;\n+\t\t/* Valid when op == READ and ctype == POOL */\n+\t\t__io struct npa_pool_s pool;\n+\t};\n+};\n+\n+/* Disable all contexts of type 'ctype' */\n+struct hwctx_disable_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io ctype;\n+};\n+\n+/* NIX mbox message formats */\n+\n+/* NIX mailbox error codes\n+ * Range 401 - 500.\n+ */\n+enum nix_af_status {\n+\tNIX_AF_ERR_PARAM = -401,\n+\tNIX_AF_ERR_AQ_FULL = -402,\n+\tNIX_AF_ERR_AQ_ENQUEUE = -403,\n+\tNIX_AF_ERR_AF_LF_INVALID = -404,\n+\tNIX_AF_ERR_AF_LF_ALLOC = -405,\n+\tNIX_AF_ERR_TLX_ALLOC_FAIL = -406,\n+\tNIX_AF_ERR_TLX_INVALID = -407,\n+\tNIX_AF_ERR_RSS_SIZE_INVALID = -408,\n+\tNIX_AF_ERR_RSS_GRPS_INVALID = -409,\n+\tNIX_AF_ERR_FRS_INVALID = -410,\n+\tNIX_AF_ERR_RX_LINK_INVALID = -411,\n+\tNIX_AF_INVAL_TXSCHQ_CFG = -412,\n+\tNIX_AF_SMQ_FLUSH_FAILED = -413,\n+\tNIX_AF_ERR_LF_RESET = -414,\n+\tNIX_AF_ERR_RSS_NOSPC_FIELD = -415,\n+\tNIX_AF_ERR_RSS_NOSPC_ALGO = -416,\n+\tNIX_AF_ERR_MARK_CFG_FAIL = -417,\n+\tNIX_AF_ERR_LSO_CFG_FAIL = -418,\n+\tNIX_AF_INVAL_NPA_PF_FUNC = -419,\n+\tNIX_AF_INVAL_SSO_PF_FUNC = -420,\n+\tNIX_AF_ERR_TX_VTAG_NOSPC = -421,\n+\tNIX_AF_ERR_RX_VTAG_INUSE = -422,\n+\tNIX_AF_ERR_PTP_CONFIG_FAIL = -423,\n+};\n+\n+/* For NIX LF context alloc and init */\n+struct nix_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __io node;\n+\tuint32_t __io rq_cnt; /* No of receive queues */\n+\tuint32_t __io sq_cnt; /* No of send queues */\n+\tuint32_t __io cq_cnt; /* No of completion queues */\n+\tuint8_t __io xqe_sz;\n+\tuint16_t __io rss_sz;\n+\tuint8_t __io rss_grps;\n+\tuint16_t __io npa_func;\n+\t/* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */\n+\tuint16_t __io sso_func;\n+\tuint64_t __io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */\n+\tuint64_t __io way_mask;\n+#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)\n+\tuint64_t flags;\n+};\n+\n+struct nix_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io sqb_size;\n+\tuint16_t __io rx_chan_base;\n+\tuint16_t __io tx_chan_base;\n+\tuint8_t __io rx_chan_cnt; /* Total number of RX channels */\n+\tuint8_t __io tx_chan_cnt; /* Total number of TX channels */\n+\tuint8_t __io lso_tsov4_idx;\n+\tuint8_t __io lso_tsov6_idx;\n+\tuint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];\n+\tuint8_t __io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */\n+\tuint8_t __io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */\n+\tuint16_t __io cints;\t /* NIX_AF_CONST2::CINTS */\n+\tuint16_t __io qints;\t /* NIX_AF_CONST2::QINTS */\n+\tuint8_t __io hw_rx_tstamp_en; /*set if rx timestamping enabled */\n+\tuint8_t __io cgx_links;\t /* No. of CGX links present in HW */\n+\tuint8_t __io lbk_links;\t /* No. of LBK links present in HW */\n+\tuint8_t __io sdp_links;\t /* No. of SDP links present in HW */\n+\tuint8_t tx_link;\t /* Transmit channel link number */\n+};\n+\n+struct nix_lf_free_req {\n+\tstruct mbox_msghdr hdr;\n+#define NIX_LF_DISABLE_FLOWS\t BIT_ULL(0)\n+#define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)\n+\tuint64_t __io flags;\n+};\n+\n+/* CN10x NIX AQ enqueue msg */\n+struct nix_cn10k_aq_enq_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io qidx;\n+\tuint8_t __io ctype;\n+\tuint8_t __io op;\n+\tunion {\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */\n+\t\t__io struct nix_cn10k_rq_ctx_s rq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */\n+\t\t__io struct nix_cn10k_sq_ctx_s sq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */\n+\t\t__io struct nix_cq_ctx_s cq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */\n+\t\t__io struct nix_rsse_s rss;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */\n+\t\t__io struct nix_rx_mce_s mce;\n+\t};\n+\t/* Mask data when op == WRITE (1=write, 0=don't write) */\n+\tunion {\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */\n+\t\t__io struct nix_cn10k_rq_ctx_s rq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */\n+\t\t__io struct nix_cn10k_sq_ctx_s sq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */\n+\t\t__io struct nix_cq_ctx_s cq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */\n+\t\t__io struct nix_rsse_s rss_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */\n+\t\t__io struct nix_rx_mce_s mce_mask;\n+\t};\n+};\n+\n+struct nix_cn10k_aq_enq_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tunion {\n+\t\tstruct nix_cn10k_rq_ctx_s rq;\n+\t\tstruct nix_cn10k_sq_ctx_s sq;\n+\t\tstruct nix_cq_ctx_s cq;\n+\t\tstruct nix_rsse_s rss;\n+\t\tstruct nix_rx_mce_s mce;\n+\t};\n+};\n+\n+/* NIX AQ enqueue msg */\n+struct nix_aq_enq_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io qidx;\n+\tuint8_t __io ctype;\n+\tuint8_t __io op;\n+\tunion {\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */\n+\t\t__io struct nix_rq_ctx_s rq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */\n+\t\t__io struct nix_sq_ctx_s sq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */\n+\t\t__io struct nix_cq_ctx_s cq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */\n+\t\t__io struct nix_rsse_s rss;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */\n+\t\t__io struct nix_rx_mce_s mce;\n+\t};\n+\t/* Mask data when op == WRITE (1=write, 0=don't write) */\n+\tunion {\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */\n+\t\t__io struct nix_rq_ctx_s rq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */\n+\t\t__io struct nix_sq_ctx_s sq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */\n+\t\t__io struct nix_cq_ctx_s cq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */\n+\t\t__io struct nix_rsse_s rss_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */\n+\t\t__io struct nix_rx_mce_s mce_mask;\n+\t};\n+};\n+\n+struct nix_aq_enq_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tunion {\n+\t\t__io struct nix_rq_ctx_s rq;\n+\t\t__io struct nix_sq_ctx_s sq;\n+\t\t__io struct nix_cq_ctx_s cq;\n+\t\t__io struct nix_rsse_s rss;\n+\t\t__io struct nix_rx_mce_s mce;\n+\t};\n+};\n+\n+/* Tx scheduler/shaper mailbox messages */\n+\n+#define MAX_TXSCHQ_PER_FUNC 128\n+\n+struct nix_txsch_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\t/* Scheduler queue count request at each level */\n+\tuint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */\n+\tuint16_t __io schq[NIX_TXSCH_LVL_CNT];\t /* Non-Contig. queues */\n+};\n+\n+struct nix_txsch_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Scheduler queue count allocated at each level */\n+\tuint16_t __io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */\n+\tuint16_t __io schq[NIX_TXSCH_LVL_CNT];\t /* Non-Contig. queues */\n+\t/* Scheduler queue list allocated at each level */\n+\tuint16_t __io schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n+\tuint16_t __io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n+\t/* Traffic aggregation scheduler level */\n+\tuint8_t __io aggr_level;\n+\t/* Aggregation lvl's RR_PRIO config */\n+\tuint8_t __io aggr_lvl_rr_prio;\n+\t/* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */\n+\tuint8_t __io link_cfg_lvl;\n+};\n+\n+struct nix_txsch_free_req {\n+\tstruct mbox_msghdr hdr;\n+#define TXSCHQ_FREE_ALL BIT_ULL(0)\n+\tuint16_t __io flags;\n+\t/* Scheduler queue level to be freed */\n+\tuint16_t __io schq_lvl;\n+\t/* List of scheduler queues to be freed */\n+\tuint16_t __io schq;\n+};\n+\n+struct nix_txschq_config {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */\n+\tuint8_t __io read;\n+#define TXSCHQ_IDX_SHIFT 16\n+#define TXSCHQ_IDX_MASK\t (BIT_ULL(10) - 1)\n+#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)\n+\tuint8_t __io num_regs;\n+#define MAX_REGS_PER_MBOX_MSG 20\n+\tuint64_t __io reg[MAX_REGS_PER_MBOX_MSG];\n+\tuint64_t __io regval[MAX_REGS_PER_MBOX_MSG];\n+\t/* All 0's => overwrite with new value */\n+\tuint64_t __io regval_mask[MAX_REGS_PER_MBOX_MSG];\n+};\n+\n+struct nix_vtag_config {\n+\tstruct mbox_msghdr hdr;\n+\t/* '0' for 4 octet VTAG, '1' for 8 octet VTAG */\n+\tuint8_t __io vtag_size;\n+\t/* cfg_type is '0' for tx vlan cfg\n+\t * cfg_type is '1' for rx vlan cfg\n+\t */\n+\tuint8_t __io cfg_type;\n+\tunion {\n+\t\t/* Valid when cfg_type is '0' */\n+\t\tstruct {\n+\t\t\tuint64_t __io vtag0;\n+\t\t\tuint64_t __io vtag1;\n+\n+\t\t\t/* cfg_vtag0 & cfg_vtag1 fields are valid\n+\t\t\t * when free_vtag0 & free_vtag1 are '0's.\n+\t\t\t */\n+\t\t\t/* cfg_vtag0 = 1 to configure vtag0 */\n+\t\t\tuint8_t __io cfg_vtag0 : 1;\n+\t\t\t/* cfg_vtag1 = 1 to configure vtag1 */\n+\t\t\tuint8_t __io cfg_vtag1 : 1;\n+\n+\t\t\t/* vtag0_idx & vtag1_idx are only valid when\n+\t\t\t * both cfg_vtag0 & cfg_vtag1 are '0's,\n+\t\t\t * these fields are used along with free_vtag0\n+\t\t\t * & free_vtag1 to free the nix lf's tx_vlan\n+\t\t\t * configuration.\n+\t\t\t *\n+\t\t\t * Denotes the indices of tx_vtag def registers\n+\t\t\t * that needs to be cleared and freed.\n+\t\t\t */\n+\t\t\tint __io vtag0_idx;\n+\t\t\tint __io vtag1_idx;\n+\n+\t\t\t/* Free_vtag0 & free_vtag1 fields are valid\n+\t\t\t * when cfg_vtag0 & cfg_vtag1 are '0's.\n+\t\t\t */\n+\t\t\t/* Free_vtag0 = 1 clears vtag0 configuration\n+\t\t\t * vtag0_idx denotes the index to be cleared.\n+\t\t\t */\n+\t\t\tuint8_t __io free_vtag0 : 1;\n+\t\t\t/* Free_vtag1 = 1 clears vtag1 configuration\n+\t\t\t * vtag1_idx denotes the index to be cleared.\n+\t\t\t */\n+\t\t\tuint8_t __io free_vtag1 : 1;\n+\t\t} tx;\n+\n+\t\t/* Valid when cfg_type is '1' */\n+\t\tstruct {\n+\t\t\t/* Rx vtag type index, valid values are in 0..7 range */\n+\t\t\tuint8_t __io vtag_type;\n+\t\t\t/* Rx vtag strip */\n+\t\t\tuint8_t __io strip_vtag : 1;\n+\t\t\t/* Rx vtag capture */\n+\t\t\tuint8_t __io capture_vtag : 1;\n+\t\t} rx;\n+\t};\n+};\n+\n+struct nix_vtag_config_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Indices of tx_vtag def registers used to configure\n+\t * tx vtag0 & vtag1 headers, these indices are valid\n+\t * when nix_vtag_config mbox requested for vtag0 and/\n+\t * or vtag1 configuration.\n+\t */\n+\tint __io vtag0_idx;\n+\tint __io vtag1_idx;\n+};\n+\n+struct nix_rss_flowkey_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tint __io mcam_index;\t /* MCAM entry index to modify */\n+\tuint32_t __io flowkey_cfg; /* Flowkey types selected */\n+#define FLOW_KEY_TYPE_PORT\t BIT(0)\n+#define FLOW_KEY_TYPE_IPV4\t BIT(1)\n+#define FLOW_KEY_TYPE_IPV6\t BIT(2)\n+#define FLOW_KEY_TYPE_TCP\t BIT(3)\n+#define FLOW_KEY_TYPE_UDP\t BIT(4)\n+#define FLOW_KEY_TYPE_SCTP\t BIT(5)\n+#define FLOW_KEY_TYPE_NVGRE\t BIT(6)\n+#define FLOW_KEY_TYPE_VXLAN\t BIT(7)\n+#define FLOW_KEY_TYPE_GENEVE\t BIT(8)\n+#define FLOW_KEY_TYPE_ETH_DMAC\t BIT(9)\n+#define FLOW_KEY_TYPE_IPV6_EXT\t BIT(10)\n+#define FLOW_KEY_TYPE_GTPU\t BIT(11)\n+#define FLOW_KEY_TYPE_INNR_IPV4\t BIT(12)\n+#define FLOW_KEY_TYPE_INNR_IPV6\t BIT(13)\n+#define FLOW_KEY_TYPE_INNR_TCP\t BIT(14)\n+#define FLOW_KEY_TYPE_INNR_UDP\t BIT(15)\n+#define FLOW_KEY_TYPE_INNR_SCTP\t BIT(16)\n+#define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)\n+#define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)\n+#define FLOW_KEY_TYPE_CUSTOM0\t BIT(19)\n+#define FLOW_KEY_TYPE_VLAN\t BIT(20)\n+#define FLOW_KEY_TYPE_L4_DST\t BIT(28)\n+#define FLOW_KEY_TYPE_L4_SRC\t BIT(29)\n+#define FLOW_KEY_TYPE_L3_DST\t BIT(30)\n+#define FLOW_KEY_TYPE_L3_SRC\t BIT(31)\n+\tuint8_t __io group; /* RSS context or group */\n+};\n+\n+struct nix_rss_flowkey_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io alg_idx; /* Selected algo index */\n+};\n+\n+struct nix_set_mac_addr {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];\n+};\n+\n+struct nix_get_mac_addr_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mac_addr[PLT_ETHER_ADDR_LEN];\n+};\n+\n+struct nix_mark_format_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io offset;\n+\tuint8_t __io y_mask;\n+\tuint8_t __io y_val;\n+\tuint8_t __io r_mask;\n+\tuint8_t __io r_val;\n+};\n+\n+struct nix_mark_format_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mark_format_idx;\n+};\n+\n+struct nix_lso_format_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io field_mask;\n+\tuint64_t __io fields[NIX_LSO_FIELD_MAX];\n+};\n+\n+struct nix_lso_format_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io lso_format_idx;\n+};\n+\n+struct nix_rx_mode {\n+\tstruct mbox_msghdr hdr;\n+#define NIX_RX_MODE_UCAST BIT(0)\n+#define NIX_RX_MODE_PROMISC BIT(1)\n+#define NIX_RX_MODE_ALLMULTI BIT(2)\n+\tuint16_t __io mode;\n+};\n+\n+struct nix_rx_cfg {\n+\tstruct mbox_msghdr hdr;\n+#define NIX_RX_OL3_VERIFY BIT(0)\n+#define NIX_RX_OL4_VERIFY BIT(1)\n+\tuint8_t __io len_verify; /* Outer L3/L4 len check */\n+#define NIX_RX_CSUM_OL4_VERIFY BIT(0)\n+\tuint8_t __io csum_verify; /* Outer L4 checksum verification */\n+};\n+\n+struct nix_frs_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io update_smq; /* Update SMQ's min/max lens */\n+\tuint8_t __io update_minlen; /* Set minlen also */\n+\tuint8_t __io sdp_link;\t /* Set SDP RX link */\n+\tuint16_t __io maxlen;\n+\tuint16_t __io minlen;\n+};\n+\n+struct nix_set_vlan_tpid {\n+\tstruct mbox_msghdr hdr;\n+#define NIX_VLAN_TYPE_INNER 0\n+#define NIX_VLAN_TYPE_OUTER 1\n+\tuint8_t __io vlan_type;\n+\tuint16_t __io tpid;\n+};\n+\n+struct nix_bp_cfg_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io chan_base; /* Starting channel number */\n+\tuint8_t __io chan_cnt;\t /* Number of channels */\n+\tuint8_t __io bpid_per_chan;\n+\t/* bpid_per_chan = 0 assigns single bp id for range of channels */\n+\t/* bpid_per_chan = 1 assigns separate bp id for each channel */\n+};\n+\n+/* PF can be mapped to either CGX or LBK interface,\n+ * so maximum 64 channels are possible.\n+ */\n+#define NIX_MAX_CHAN 64\n+struct nix_bp_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Channel and bpid mapping */\n+\tuint16_t __io chan_bpid[NIX_MAX_CHAN];\n+\t/* Number of channel for which bpids are assigned */\n+\tuint8_t __io chan_cnt;\n+};\n+\n+/* Global NIX inline IPSec configuration */\n+struct nix_inline_ipsec_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io cpt_credit;\n+\tstruct {\n+\t\tuint8_t __io egrp;\n+\t\tuint8_t __io opcode;\n+\t} gen_cfg;\n+\tstruct {\n+\t\tuint16_t __io cpt_pf_func;\n+\t\tuint8_t __io cpt_slot;\n+\t} inst_qsel;\n+\tuint8_t __io enable;\n+};\n+\n+/* Per NIX LF inline IPSec configuration */\n+struct nix_inline_ipsec_lf_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io sa_base_addr;\n+\tstruct {\n+\t\tuint32_t __io tag_const;\n+\t\tuint16_t __io lenm1_max;\n+\t\tuint8_t __io sa_pow2_size;\n+\t\tuint8_t __io tt;\n+\t} ipsec_cfg0;\n+\tstruct {\n+\t\tuint32_t __io sa_idx_max;\n+\t\tuint8_t __io sa_idx_w;\n+\t} ipsec_cfg1;\n+\tuint8_t __io enable;\n+};\n+\n+struct nix_hw_info {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io vwqe_delay;\n+\tuint16_t __io rsvd[15];\n+};\n+\n+/* SSO mailbox error codes\n+ * Range 501 - 600.\n+ */\n+enum sso_af_status {\n+\tSSO_AF_ERR_PARAM = -501,\n+\tSSO_AF_ERR_LF_INVALID = -502,\n+\tSSO_AF_ERR_AF_LF_ALLOC = -503,\n+\tSSO_AF_ERR_GRP_EBUSY = -504,\n+\tSSO_AF_INVAL_NPA_PF_FUNC = -505,\n+};\n+\n+struct sso_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __io node;\n+\tuint16_t __io hwgrps;\n+};\n+\n+struct sso_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io xaq_buf_size;\n+\tuint32_t __io xaq_wq_entries;\n+\tuint32_t __io in_unit_entries;\n+\tuint16_t __io hwgrps;\n+};\n+\n+struct sso_lf_free_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __io node;\n+\tuint16_t __io hwgrps;\n+};\n+\n+/* SSOW mailbox error codes\n+ * Range 601 - 700.\n+ */\n+enum ssow_af_status {\n+\tSSOW_AF_ERR_PARAM = -601,\n+\tSSOW_AF_ERR_LF_INVALID = -602,\n+\tSSOW_AF_ERR_AF_LF_ALLOC = -603,\n+};\n+\n+struct ssow_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __io node;\n+\tuint16_t __io hws;\n+};\n+\n+struct ssow_lf_free_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __io node;\n+\tuint16_t __io hws;\n+};\n+\n+struct sso_hw_setconfig {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io npa_aura_id;\n+\tuint16_t __io npa_pf_func;\n+\tuint16_t __io hwgrps;\n+};\n+\n+struct sso_hw_xaq_release {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io hwgrps;\n+};\n+\n+struct sso_info_req {\n+\tstruct mbox_msghdr hdr;\n+\tunion {\n+\t\tuint16_t __io grp;\n+\t\tuint16_t __io hws;\n+\t};\n+};\n+\n+struct sso_grp_priority {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io grp;\n+\tuint8_t __io priority;\n+\tuint8_t __io affinity;\n+\tuint8_t __io weight;\n+};\n+\n+struct sso_grp_qos_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io grp;\n+\tuint32_t __io xaq_limit;\n+\tuint16_t __io taq_thr;\n+\tuint16_t __io iaq_thr;\n+};\n+\n+struct sso_grp_stats {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io grp;\n+\tuint64_t __io ws_pc;\n+\tuint64_t __io ext_pc;\n+\tuint64_t __io wa_pc;\n+\tuint64_t __io ts_pc;\n+\tuint64_t __io ds_pc;\n+\tuint64_t __io dq_pc;\n+\tuint64_t __io aw_status;\n+\tuint64_t __io page_cnt;\n+};\n+\n+struct sso_hws_stats {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io hws;\n+\tuint64_t __io arbitration;\n+};\n+\n+/* CPT mailbox error codes\n+ * Range 901 - 1000.\n+ */\n+enum cpt_af_status {\n+\tCPT_AF_ERR_PARAM = -901,\n+\tCPT_AF_ERR_GRP_INVALID = -902,\n+\tCPT_AF_ERR_LF_INVALID = -903,\n+\tCPT_AF_ERR_ACCESS_DENIED = -904,\n+\tCPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,\n+\tCPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,\n+\tCPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,\n+\tCPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908\n+};\n+\n+/* CPT mbox message formats */\n+\n+struct cpt_rd_wr_reg_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io reg_offset;\n+\tuint64_t __io *ret_val;\n+\tuint64_t __io val;\n+\tuint8_t __io is_write;\n+};\n+\n+struct cpt_set_crypto_grp_req_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io crypto_eng_grp;\n+};\n+\n+struct cpt_lf_alloc_req_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io nix_pf_func;\n+\tuint16_t __io sso_pf_func;\n+\tuint16_t __io eng_grpmsk;\n+\tuint8_t __io blkaddr;\n+};\n+\n+#define CPT_INLINE_INBOUND 0\n+#define CPT_INLINE_OUTBOUND 1\n+\n+struct cpt_inline_ipsec_cfg_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io enable;\n+\tuint8_t __io slot;\n+\tuint8_t __io dir;\n+\tuint8_t __io sso_pf_func_ovrd;\n+\tuint16_t __io sso_pf_func; /* Inbound path SSO_PF_FUNC */\n+\tuint16_t __io nix_pf_func; /* Outbound path NIX_PF_FUNC */\n+};\n+\n+struct cpt_sts_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io blkaddr;\n+};\n+\n+struct cpt_sts_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io inst_req_pc;\n+\tuint64_t __io inst_lat_pc;\n+\tuint64_t __io rd_req_pc;\n+\tuint64_t __io rd_lat_pc;\n+\tuint64_t __io rd_uc_pc;\n+\tuint64_t __io active_cycles_pc;\n+\tuint64_t __io ctx_mis_pc;\n+\tuint64_t __io ctx_hit_pc;\n+\tuint64_t __io ctx_aop_pc;\n+\tuint64_t __io ctx_aop_lat_pc;\n+\tuint64_t __io ctx_ifetch_pc;\n+\tuint64_t __io ctx_ifetch_lat_pc;\n+\tuint64_t __io ctx_ffetch_pc;\n+\tuint64_t __io ctx_ffetch_lat_pc;\n+\tuint64_t __io ctx_wback_pc;\n+\tuint64_t __io ctx_wback_lat_pc;\n+\tuint64_t __io ctx_psh_pc;\n+\tuint64_t __io ctx_psh_lat_pc;\n+\tuint64_t __io ctx_err;\n+\tuint64_t __io ctx_enc_id;\n+\tuint64_t __io ctx_flush_timer;\n+\tuint64_t __io rxc_time;\n+\tuint64_t __io rxc_time_cfg;\n+\tuint64_t __io rxc_active_sts;\n+\tuint64_t __io rxc_zombie_sts;\n+\tuint64_t __io busy_sts_ae;\n+\tuint64_t __io free_sts_ae;\n+\tuint64_t __io busy_sts_se;\n+\tuint64_t __io free_sts_se;\n+\tuint64_t __io busy_sts_ie;\n+\tuint64_t __io free_sts_ie;\n+\tuint64_t __io exe_err_info;\n+\tuint64_t __io cptclk_cnt;\n+\tuint64_t __io diag;\n+\tuint64_t __io rxc_dfrg;\n+\tuint64_t __io x2p_link_cfg0;\n+\tuint64_t __io x2p_link_cfg1;\n+};\n+\n+struct cpt_rxc_time_cfg_req {\n+\tstruct mbox_msghdr hdr;\n+\tint blkaddr;\n+\tuint32_t step;\n+\tuint16_t zombie_thres;\n+\tuint16_t zombie_limit;\n+\tuint16_t active_thres;\n+\tuint16_t active_limit;\n+};\n+\n+struct cpt_rx_inline_lf_cfg_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io sso_pf_func;\n+};\n+\n+enum cpt_eng_type {\n+\tCPT_ENG_TYPE_AE = 1,\n+\tCPT_ENG_TYPE_SE = 2,\n+\tCPT_ENG_TYPE_IE = 3,\n+\tCPT_MAX_ENG_TYPES,\n+};\n+\n+/* CPT HW capabilities */\n+union cpt_eng_caps {\n+\tuint64_t __io u;\n+\tstruct {\n+\t\tuint64_t __io reserved_0_4 : 5;\n+\t\tuint64_t __io mul : 1;\n+\t\tuint64_t __io sha1_sha2 : 1;\n+\t\tuint64_t __io chacha20 : 1;\n+\t\tuint64_t __io zuc_snow3g : 1;\n+\t\tuint64_t __io sha3 : 1;\n+\t\tuint64_t __io aes : 1;\n+\t\tuint64_t __io kasumi : 1;\n+\t\tuint64_t __io des : 1;\n+\t\tuint64_t __io crc : 1;\n+\t\tuint64_t __io reserved_14_63 : 50;\n+\t};\n+};\n+\n+struct cpt_caps_rsp_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io cpt_pf_drv_version;\n+\tuint8_t __io cpt_revision;\n+\tunion cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];\n+};\n+\n+struct cpt_eng_grp_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io eng_type;\n+};\n+\n+struct cpt_eng_grp_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io eng_type;\n+\tuint8_t __io eng_grp_num;\n+};\n+\n+/* NPC mbox message structs */\n+\n+#define NPC_MCAM_ENTRY_INVALID 0xFFFF\n+#define NPC_MCAM_INVALID_MAP 0xFFFF\n+\n+/* NPC mailbox error codes\n+ * Range 701 - 800.\n+ */\n+enum npc_af_status {\n+\tNPC_MCAM_INVALID_REQ = -701,\n+\tNPC_MCAM_ALLOC_DENIED = -702,\n+\tNPC_MCAM_ALLOC_FAILED = -703,\n+\tNPC_MCAM_PERM_DENIED = -704,\n+\tNPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,\n+};\n+\n+struct npc_mcam_alloc_entry_req {\n+\tstruct mbox_msghdr hdr;\n+#define NPC_MAX_NONCONTIG_ENTRIES 256\n+\tuint8_t __io contig; /* Contiguous entries ? */\n+#define NPC_MCAM_ANY_PRIO 0\n+#define NPC_MCAM_LOWER_PRIO 1\n+#define NPC_MCAM_HIGHER_PRIO 2\n+\tuint8_t __io priority; /* Lower or higher w.r.t ref_entry */\n+\tuint16_t __io ref_entry;\n+\tuint16_t __io count; /* Number of entries requested */\n+};\n+\n+struct npc_mcam_alloc_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Entry alloc'ed or start index if contiguous.\n+\t * Invalid in case of non-contiguous.\n+\t */\n+\tuint16_t __io entry;\n+\tuint16_t __io count;\t /* Number of entries allocated */\n+\tuint16_t __io free_count; /* Number of entries available */\n+\tuint16_t __io entry_list[NPC_MAX_NONCONTIG_ENTRIES];\n+};\n+\n+struct npc_mcam_free_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io entry; /* Entry index to be freed */\n+\tuint8_t __io all; /* Free all entries alloc'ed to this PFVF */\n+};\n+\n+struct mcam_entry {\n+#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */\n+\tuint64_t __io kw[NPC_MAX_KWS_IN_KEY];\n+\tuint64_t __io kw_mask[NPC_MAX_KWS_IN_KEY];\n+\tuint64_t __io action;\n+\tuint64_t __io vtag_action;\n+};\n+\n+struct npc_mcam_write_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tstruct mcam_entry entry_data;\n+\tuint16_t __io entry;\t /* MCAM entry to write this match key */\n+\tuint16_t __io cntr;\t /* Counter for this MCAM entry */\n+\tuint8_t __io intf;\t /* Rx or Tx interface */\n+\tuint8_t __io enable_entry; /* Enable this MCAM entry ? */\n+\tuint8_t __io set_cntr;\t /* Set counter for this entry ? */\n+};\n+\n+/* Enable/Disable a given entry */\n+struct npc_mcam_ena_dis_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io entry;\n+};\n+\n+struct npc_mcam_shift_entry_req {\n+\tstruct mbox_msghdr hdr;\n+#define NPC_MCAM_MAX_SHIFTS 64\n+\tuint16_t __io curr_entry[NPC_MCAM_MAX_SHIFTS];\n+\tuint16_t __io new_entry[NPC_MCAM_MAX_SHIFTS];\n+\tuint16_t __io shift_count; /* Number of entries to shift */\n+};\n+\n+struct npc_mcam_shift_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Index in 'curr_entry', not entry itself */\n+\tuint16_t __io failed_entry_idx;\n+};\n+\n+struct npc_mcam_alloc_counter_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io contig; /* Contiguous counters ? */\n+#define NPC_MAX_NONCONTIG_COUNTERS 64\n+\tuint16_t __io count; /* Number of counters requested */\n+};\n+\n+struct npc_mcam_alloc_counter_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Counter alloc'ed or start idx if contiguous.\n+\t * Invalid in case of non-contiguous.\n+\t */\n+\tuint16_t __io cntr;\n+\tuint16_t __io count; /* Number of counters allocated */\n+\tuint16_t __io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];\n+};\n+\n+struct npc_mcam_oper_counter_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io cntr; /* Free a counter or clear/fetch it's stats */\n+};\n+\n+struct npc_mcam_oper_counter_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* valid only while fetching counter's stats */\n+\tuint64_t __io stat;\n+};\n+\n+struct npc_mcam_unmap_counter_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io cntr;\n+\tuint16_t __io entry; /* Entry and counter to be unmapped */\n+\tuint8_t __io all; /* Unmap all entries using this counter ? */\n+};\n+\n+struct npc_mcam_alloc_and_write_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tstruct mcam_entry entry_data;\n+\tuint16_t __io ref_entry;\n+\tuint8_t __io priority;\t /* Lower or higher w.r.t ref_entry */\n+\tuint8_t __io intf;\t /* Rx or Tx interface */\n+\tuint8_t __io enable_entry; /* Enable this MCAM entry ? */\n+\tuint8_t __io alloc_cntr; /* Allocate counter and map ? */\n+};\n+\n+struct npc_mcam_alloc_and_write_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io entry;\n+\tuint16_t __io cntr;\n+};\n+\n+struct npc_get_kex_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */\n+\tuint64_t __io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */\n+#define NPC_MAX_INTF 2\n+#define NPC_MAX_LID 8\n+#define NPC_MAX_LT 16\n+#define NPC_MAX_LD 2\n+#define NPC_MAX_LFL 16\n+\t/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */\n+\tuint64_t __io kex_ld_flags[NPC_MAX_LD];\n+\t/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */\n+\tuint64_t __io intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT]\n+\t\t\t\t [NPC_MAX_LD];\n+\t/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */\n+\tuint64_t __io intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];\n+#define MKEX_NAME_LEN 128\n+\tuint8_t __io mkex_pfl_name[MKEX_NAME_LEN];\n+};\n+\n+enum header_fields {\n+\tNPC_DMAC,\n+\tNPC_SMAC,\n+\tNPC_ETYPE,\n+\tNPC_OUTER_VID,\n+\tNPC_TOS,\n+\tNPC_SIP_IPV4,\n+\tNPC_DIP_IPV4,\n+\tNPC_SIP_IPV6,\n+\tNPC_DIP_IPV6,\n+\tNPC_SPORT_TCP,\n+\tNPC_DPORT_TCP,\n+\tNPC_SPORT_UDP,\n+\tNPC_DPORT_UDP,\n+\tNPC_FDSA_VAL,\n+\tNPC_HEADER_FIELDS_MAX,\n+};\n+\n+struct flow_msg {\n+\tunsigned char __io dmac[6];\n+\tunsigned char __io smac[6];\n+\tuint16_t __io etype;\n+\tuint16_t __io vlan_etype;\n+\tuint16_t __io vlan_tci;\n+\tunion {\n+\t\tuint32_t __io ip4src;\n+\t\tuint32_t __io ip6src[4];\n+\t};\n+\tunion {\n+\t\tuint32_t __io ip4dst;\n+\t\tuint32_t __io ip6dst[4];\n+\t};\n+\tuint8_t __io tos;\n+\tuint8_t __io ip_ver;\n+\tuint8_t __io ip_proto;\n+\tuint8_t __io tc;\n+\tuint16_t __io sport;\n+\tuint16_t __io dport;\n+};\n+\n+struct npc_install_flow_req {\n+\tstruct mbox_msghdr hdr;\n+\tstruct flow_msg packet;\n+\tstruct flow_msg mask;\n+\tuint64_t __io features;\n+\tuint16_t __io entry;\n+\tuint16_t __io channel;\n+\tuint8_t __io intf;\n+\tuint8_t __io set_cntr;\n+\tuint8_t __io default_rule;\n+\t/* Overwrite(0) or append(1) flow to default rule? */\n+\tuint8_t __io append;\n+\tuint16_t __io vf;\n+\t/* action */\n+\tuint32_t __io index;\n+\tuint16_t __io match_id;\n+\tuint8_t __io flow_key_alg;\n+\tuint8_t __io op;\n+\t/* vtag action */\n+\tuint8_t __io vtag0_type;\n+\tuint8_t __io vtag0_valid;\n+\tuint8_t __io vtag1_type;\n+\tuint8_t __io vtag1_valid;\n+\n+\t/* vtag tx action */\n+\tuint16_t __io vtag0_def;\n+\tuint8_t __io vtag0_op;\n+\tuint16_t __io vtag1_def;\n+\tuint8_t __io vtag1_op;\n+};\n+\n+struct npc_install_flow_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Negative if no counter else counter number */\n+\tint __io counter;\n+};\n+\n+struct npc_delete_flow_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io entry;\n+\tuint16_t __io start; /*Disable range of entries */\n+\tuint16_t __io end;\n+\tuint8_t __io all; /* PF + VFs */\n+};\n+\n+struct npc_mcam_read_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\t/* MCAM entry to read */\n+\tuint16_t __io entry;\n+};\n+\n+struct npc_mcam_read_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tstruct mcam_entry entry_data;\n+\tuint8_t __io intf;\n+\tuint8_t __io enable;\n+};\n+\n+struct npc_mcam_read_base_rule_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tstruct mcam_entry entry_data;\n+};\n+\n+/* TIM mailbox error codes\n+ * Range 801 - 900.\n+ */\n+enum tim_af_status {\n+\tTIM_AF_NO_RINGS_LEFT = -801,\n+\tTIM_AF_INVALID_NPA_PF_FUNC = -802,\n+\tTIM_AF_INVALID_SSO_PF_FUNC = -803,\n+\tTIM_AF_RING_STILL_RUNNING = -804,\n+\tTIM_AF_LF_INVALID = -805,\n+\tTIM_AF_CSIZE_NOT_ALIGNED = -806,\n+\tTIM_AF_CSIZE_TOO_SMALL = -807,\n+\tTIM_AF_CSIZE_TOO_BIG = -808,\n+\tTIM_AF_INTERVAL_TOO_SMALL = -809,\n+\tTIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,\n+\tTIM_AF_INVALID_CLOCK_SOURCE = -811,\n+\tTIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,\n+\tTIM_AF_INVALID_BSIZE = -813,\n+\tTIM_AF_INVALID_ENABLE_PERIODIC = -814,\n+\tTIM_AF_INVALID_ENABLE_DONTFREE = -815,\n+\tTIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,\n+\tTIM_AF_RING_ALREADY_DISABLED = -817,\n+};\n+\n+enum tim_clk_srcs {\n+\tTIM_CLK_SRCS_TENNS = 0,\n+\tTIM_CLK_SRCS_GPIO = 1,\n+\tTIM_CLK_SRCS_GTI = 2,\n+\tTIM_CLK_SRCS_PTP = 3,\n+\tTIM_CLK_SRSC_INVALID,\n+};\n+\n+enum tim_gpio_edge {\n+\tTIM_GPIO_NO_EDGE = 0,\n+\tTIM_GPIO_LTOH_TRANS = 1,\n+\tTIM_GPIO_HTOL_TRANS = 2,\n+\tTIM_GPIO_BOTH_TRANS = 3,\n+\tTIM_GPIO_INVALID,\n+};\n+\n+enum ptp_op {\n+\tPTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */\n+\tPTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */\n+};\n+\n+struct ptp_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io op;\n+\tint64_t __io scaled_ppm;\n+\tuint8_t __io is_pmu;\n+};\n+\n+struct ptp_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io clk;\n+\tuint64_t __io tsc;\n+};\n+\n+struct get_hw_cap_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Schq mapping fixed or flexible */\n+\tuint8_t __io nix_fixed_txschq_mapping;\n+\tuint8_t __io nix_shaping; /* Is shaping and coloring supported */\n+};\n+\n+struct ndc_sync_op {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io nix_lf_tx_sync;\n+\tuint8_t __io nix_lf_rx_sync;\n+\tuint8_t __io npa_lf_sync;\n+};\n+\n+struct tim_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io ring;\n+\tuint16_t __io npa_pf_func;\n+\tuint16_t __io sso_pf_func;\n+};\n+\n+struct tim_ring_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io ring;\n+};\n+\n+struct tim_config_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __io ring;\n+\tuint8_t __io bigendian;\n+\tuint8_t __io clocksource;\n+\tuint8_t __io enableperiodic;\n+\tuint8_t __io enabledontfreebuffer;\n+\tuint32_t __io bucketsize;\n+\tuint32_t __io chunksize;\n+\tuint32_t __io interval;\n+\tuint8_t __io gpioedge;\n+};\n+\n+struct tim_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io tenns_clk;\n+};\n+\n+struct tim_enable_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io timestarted;\n+\tuint32_t __io currentbucket;\n+};\n+\n+#endif /* __ROC_MBOX_H__ */\n", "prefixes": [ "v4", "06/52" ] }