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GET /api/patches/90410/?format=api
{ "id": 90410, "url": "http://patches.dpdk.org/api/patches/90410/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-38-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401123817.14348-38-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401123817.14348-38-ndabilpuram@marvell.com", "date": "2021-04-01T12:38:02", "name": "[v3,37/52] common/cnxk: add nix tm support for internal hierarchy", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "6f66f1d78efa25e6016243661fbf180a03ed8039", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-38-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16059, "url": "http://patches.dpdk.org/api/series/16059/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16059", "date": "2021-04-01T12:37:25", "name": "Add Marvell CNXK common driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16059/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90410/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90410/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 27C95A0548;\n\tThu, 1 Apr 2021 14:44:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AB4AF1412A5;\n\tThu, 1 Apr 2021 14:40:30 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 603401412A2\n for <dev@dpdk.org>; Thu, 1 Apr 2021 14:40:29 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 131CPLXo019083 for <dev@dpdk.org>; Thu, 1 Apr 2021 05:40:28 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje4w-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 05:40:28 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 05:40:26 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 05:40:26 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id DDF3F3F7043;\n Thu, 1 Apr 2021 05:40:23 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=AGBURLfxJZaaXU3xqiPGcdjJFBYKiZRwGumYflZUy1Y=;\n b=XHRWOhJU2nMgk2VR5Vg00yRLpQEC5H4GIZsTzNAJWoCS7h3zeGjTDNvi2G9cCdSb3fDa\n vpxxzdvXqBjsCPJZ0IQ+jUIf2k+XvAkFm4YhJ1ZtN/XzRlgyzhYsSzuLXkTpuIEEaj1q\n numNFbuDh4oHh8zBFyYJpiE51Y5bBJxnPKpyRR+byCZgM4wgySDQCYp7IWRzGAJsJsTw\n YA/CHUPdBGk9uKt3pa+TLDiB9kaKRgAOda41nHiXHMAN1aD6Ay9RRyGpuq7ALYEg03IN\n Q4ogbSs3GtOWQ9CTXAy2vhAXaxe+n+yqWyopeGsaOFbC++LK7nzzlpcs6SfRsfug6I/0 3A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Thu, 1 Apr 2021 18:08:02 +0530", "Message-ID": "<20210401123817.14348-38-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401123817.14348-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401123817.14348-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "7UFF_eE0xNpYQb-DjgU_y0xDHoCZNfrX", "X-Proofpoint-ORIG-GUID": "7UFF_eE0xNpYQb-DjgU_y0xDHoCZNfrX", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_05:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 37/52] common/cnxk: add nix tm support for\n internal hierarchy", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support to create internal TM default hierarchy and ratelimit\nhierarchy and API to ratelimit SQ to a given rate. This will be\nused by cnxk ethdev driver's tx queue ratelimit op.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 7 ++\n drivers/common/cnxk/roc_nix_priv.h | 2 +\n drivers/common/cnxk/roc_nix_tm.c | 156 +++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_tm_ops.c | 141 +++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 3 +\n 5 files changed, 309 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 7bf3435..8992ad3 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -330,6 +330,8 @@ enum roc_tm_node_level {\n /*\n * TM runtime hierarchy init API.\n */\n+int __roc_api roc_nix_tm_init(struct roc_nix *roc_nix);\n+void __roc_api roc_nix_tm_fini(struct roc_nix *roc_nix);\n int __roc_api roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable);\n int __roc_api roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq);\n \n@@ -392,6 +394,11 @@ struct roc_nix_tm_shaper_profile *__roc_api roc_nix_tm_shaper_profile_next(\n \tstruct roc_nix *roc_nix, struct roc_nix_tm_shaper_profile *__prev);\n \n /*\n+ * TM ratelimit tree API.\n+ */\n+int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid,\n+\t\t\t\t uint64_t rate);\n+/*\n * TM hierarchy enable/disable API.\n */\n int __roc_api roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix);\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex a40621c..4e1485f 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -326,6 +326,7 @@ int nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,\n int nix_tm_sq_flush_pre(struct roc_nix_sq *sq);\n int nix_tm_sq_flush_post(struct roc_nix_sq *sq);\n int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable);\n+int nix_tm_prepare_default_tree(struct roc_nix *roc_nix);\n int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node);\n int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t enum roc_nix_tm_tree tree, bool free);\n@@ -344,6 +345,7 @@ int nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree);\n int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);\n int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \t\t\t bool rr_quantum_only);\n+int nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix);\n \n /*\n * TM priv utils.\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 762c85a..9b328c9 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -1089,6 +1089,162 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)\n }\n \n int\n+nix_tm_prepare_default_tree(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint32_t nonleaf_id = nix->nb_tx_queues;\n+\tstruct nix_tm_node *node = NULL;\n+\tuint8_t leaf_lvl, lvl, lvl_end;\n+\tuint32_t parent, i;\n+\tint rc = 0;\n+\n+\t/* Add ROOT, SCH1, SCH2, SCH3, [SCH4] nodes */\n+\tparent = ROC_NIX_TM_NODE_ID_INVALID;\n+\t/* With TL1 access we have an extra level */\n+\tlvl_end = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH4 :\n+\t\t\t\t\t\t ROC_TM_LVL_SCH3);\n+\n+\tfor (lvl = ROC_TM_LVL_ROOT; lvl <= lvl_end; lvl++) {\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n+\n+\t\tnode->id = nonleaf_id;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = lvl;\n+\t\tnode->tree = ROC_NIX_TM_DEFAULT;\n+\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tparent = nonleaf_id;\n+\t\tnonleaf_id++;\n+\t}\n+\n+\tparent = nonleaf_id - 1;\n+\tleaf_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_QUEUE :\n+\t\t\t\t\t\t\tROC_TM_LVL_SCH4);\n+\n+\t/* Add leaf nodes */\n+\tfor (i = 0; i < nix->nb_tx_queues; i++) {\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n+\n+\t\tnode->id = i;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = leaf_lvl;\n+\t\tnode->tree = ROC_NIX_TM_DEFAULT;\n+\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t}\n+\n+\treturn 0;\n+error:\n+\tnix_tm_node_free(node);\n+\treturn rc;\n+}\n+\n+int\n+nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint32_t nonleaf_id = nix->nb_tx_queues;\n+\tstruct nix_tm_node *node = NULL;\n+\tuint8_t leaf_lvl, lvl, lvl_end;\n+\tuint32_t parent, i;\n+\tint rc = 0;\n+\n+\t/* Add ROOT, SCH1, SCH2 nodes */\n+\tparent = ROC_NIX_TM_NODE_ID_INVALID;\n+\tlvl_end = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH3 :\n+\t\t\t\t\t\t ROC_TM_LVL_SCH2);\n+\n+\tfor (lvl = ROC_TM_LVL_ROOT; lvl <= lvl_end; lvl++) {\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n+\n+\t\tnode->id = nonleaf_id;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = lvl;\n+\t\tnode->tree = ROC_NIX_TM_RLIMIT;\n+\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tparent = nonleaf_id;\n+\t\tnonleaf_id++;\n+\t}\n+\n+\t/* SMQ is mapped to SCH4 when we have TL1 access and SCH3 otherwise */\n+\tlvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH4 : ROC_TM_LVL_SCH3);\n+\n+\t/* Add per queue SMQ nodes i.e SCH4 / SCH3 */\n+\tfor (i = 0; i < nix->nb_tx_queues; i++) {\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n+\n+\t\tnode->id = nonleaf_id + i;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = lvl;\n+\t\tnode->tree = ROC_NIX_TM_RLIMIT;\n+\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t}\n+\n+\tparent = nonleaf_id;\n+\tleaf_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_QUEUE :\n+\t\t\t\t\t\t\tROC_TM_LVL_SCH4);\n+\n+\t/* Add leaf nodes */\n+\tfor (i = 0; i < nix->nb_tx_queues; i++) {\n+\t\trc = -ENOMEM;\n+\t\tnode = nix_tm_node_alloc();\n+\t\tif (!node)\n+\t\t\tgoto error;\n+\n+\t\tnode->id = i;\n+\t\tnode->parent_id = parent;\n+\t\tnode->priority = 0;\n+\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n+\t\tnode->lvl = leaf_lvl;\n+\t\tnode->tree = ROC_NIX_TM_RLIMIT;\n+\n+\t\trc = nix_tm_node_add(roc_nix, node);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t}\n+\n+\treturn 0;\n+error:\n+\tnix_tm_node_free(node);\n+\treturn rc;\n+}\n+\n+int\n nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask, bool hw_only)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex 6bb0766..d13cc8a 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -543,3 +543,144 @@ roc_nix_tm_hierarchy_enable(struct roc_nix *roc_nix, enum roc_nix_tm_tree tree,\n \tnix->tm_flags |= NIX_TM_HIERARCHY_ENA;\n \treturn 0;\n }\n+\n+int\n+roc_nix_tm_init(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint32_t tree_mask;\n+\tint rc;\n+\n+\tif (nix->tm_flags & NIX_TM_HIERARCHY_ENA) {\n+\t\tplt_err(\"Cannot init while existing hierarchy is enabled\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\t/* Free up all user resources already held */\n+\ttree_mask = NIX_TM_TREE_MASK_ALL;\n+\trc = nix_tm_free_resources(roc_nix, tree_mask, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to freeup all nodes and resources, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Prepare default tree */\n+\trc = nix_tm_prepare_default_tree(roc_nix);\n+\tif (rc) {\n+\t\tplt_err(\"failed to prepare default tm tree, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* Prepare rlimit tree */\n+\trc = nix_tm_prepare_rate_limited_tree(roc_nix);\n+\tif (rc) {\n+\t\tplt_err(\"failed to prepare rlimit tm tree, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_tm_shaper_profile profile;\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_tm_node *node, *parent;\n+\n+\tvolatile uint64_t *reg, *regval;\n+\tstruct nix_txschq_config *req;\n+\tuint16_t flags;\n+\tuint8_t k = 0;\n+\tint rc;\n+\n+\tif (nix->tm_tree != ROC_NIX_TM_RLIMIT ||\n+\t !(nix->tm_flags & NIX_TM_HIERARCHY_ENA))\n+\t\treturn NIX_ERR_TM_INVALID_TREE;\n+\n+\tnode = nix_tm_node_search(nix, qid, ROC_NIX_TM_RLIMIT);\n+\n+\t/* check if we found a valid leaf node */\n+\tif (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||\n+\t node->parent->hw_id == NIX_TM_HW_ID_INVALID)\n+\t\treturn NIX_ERR_TM_INVALID_NODE;\n+\n+\tparent = node->parent;\n+\tflags = parent->flags;\n+\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq->lvl = NIX_TXSCH_LVL_MDQ;\n+\treg = req->reg;\n+\tregval = req->regval;\n+\n+\tif (rate == 0) {\n+\t\tk += nix_tm_sw_xoff_prep(parent, true, ®[k], ®val[k]);\n+\t\tflags &= ~NIX_TM_NODE_ENABLED;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (!(flags & NIX_TM_NODE_ENABLED)) {\n+\t\tk += nix_tm_sw_xoff_prep(parent, false, ®[k], ®val[k]);\n+\t\tflags |= NIX_TM_NODE_ENABLED;\n+\t}\n+\n+\t/* Use only PIR for rate limit */\n+\tmemset(&profile, 0, sizeof(profile));\n+\tprofile.peak.rate = rate;\n+\t/* Minimum burst of ~4us Bytes of Tx */\n+\tprofile.peak.size = PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix),\n+\t\t\t\t (4ul * rate) / ((uint64_t)1E6 * 8));\n+\tif (!nix->tm_rate_min || nix->tm_rate_min > rate)\n+\t\tnix->tm_rate_min = rate;\n+\n+\tk += nix_tm_shaper_reg_prep(parent, &profile, ®[k], ®val[k]);\n+exit:\n+\treq->num_regs = k;\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tparent->flags = flags;\n+\treturn 0;\n+}\n+\n+void\n+roc_nix_tm_fini(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_txsch_free_req *req;\n+\tuint32_t tree_mask;\n+\tuint8_t hw_lvl;\n+\tint rc;\n+\n+\t/* Xmit is assumed to be disabled */\n+\t/* Free up resources already held */\n+\ttree_mask = NIX_TM_TREE_MASK_ALL;\n+\trc = nix_tm_free_resources(roc_nix, tree_mask, false);\n+\tif (rc)\n+\t\tplt_err(\"Failed to freeup existing nodes or rsrcs, rc=%d\", rc);\n+\n+\t/* Free all other hw resources */\n+\treq = mbox_alloc_msg_nix_txsch_free(mbox);\n+\tif (req == NULL)\n+\t\treturn;\n+\n+\treq->flags = TXSCHQ_FREE_ALL;\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tplt_err(\"Failed to freeup all res, rc=%d\", rc);\n+\n+\tfor (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\tplt_bitmap_reset(nix->schq_bmp[hw_lvl]);\n+\t\tplt_bitmap_reset(nix->schq_contig_bmp[hw_lvl]);\n+\t\tnix->contig_rsvd[hw_lvl] = 0;\n+\t\tnix->discontig_rsvd[hw_lvl] = 0;\n+\t}\n+\n+\t/* Clear shaper profiles */\n+\tnix_tm_clear_shaper_profiles(nix);\n+\tnix->tm_tree = 0;\n+\tnix->tm_flags &= ~NIX_TM_HIERARCHY_ENA;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 9c860ff..854c3c1 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -104,9 +104,11 @@ INTERNAL {\n \troc_nix_xstats_names_get;\n \troc_nix_switch_hdr_set;\n \troc_nix_eeprom_info_get;\n+\troc_nix_tm_fini;\n \troc_nix_tm_free_resources;\n \troc_nix_tm_hierarchy_disable;\n \troc_nix_tm_hierarchy_enable;\n+\troc_nix_tm_init;\n \troc_nix_tm_node_add;\n \troc_nix_tm_node_delete;\n \troc_nix_tm_node_get;\n@@ -114,6 +116,7 @@ INTERNAL {\n \troc_nix_tm_node_name_get;\n \troc_nix_tm_node_next;\n \troc_nix_tm_node_pkt_mode_update;\n+\troc_nix_tm_rlimit_sq;\n \troc_nix_tm_shaper_profile_add;\n \troc_nix_tm_shaper_profile_delete;\n \troc_nix_tm_shaper_profile_get;\n", "prefixes": [ "v3", "37/52" ] }