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GET /api/patches/9033/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 9033,
    "url": "http://patches.dpdk.org/api/patches/9033/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1448183993-6374-1-git-send-email-jingjing.wu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1448183993-6374-1-git-send-email-jingjing.wu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1448183993-6374-1-git-send-email-jingjing.wu@intel.com",
    "date": "2015-11-22T09:19:53",
    "name": "[dpdk-dev] i40e: fix BW info update if no dcb enabled",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e86f163f9f766702d232d3a65ff2d0a05f672a54",
    "submitter": {
        "id": 47,
        "url": "http://patches.dpdk.org/api/people/47/?format=api",
        "name": "Jingjing Wu",
        "email": "jingjing.wu@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1448183993-6374-1-git-send-email-jingjing.wu@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/9033/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/9033/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id AF10F8DAC;\n\tSun, 22 Nov 2015 10:20:24 +0100 (CET)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id E48118DA8\n\tfor <dev@dpdk.org>; Sun, 22 Nov 2015 10:20:21 +0100 (CET)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga101.jf.intel.com with ESMTP; 22 Nov 2015 01:20:02 -0800",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga002.jf.intel.com with ESMTP; 22 Nov 2015 01:20:01 -0800",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id tAM9Jx8e006785;\n\tSun, 22 Nov 2015 17:19:59 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid tAM9Jvji006410; Sun, 22 Nov 2015 17:19:59 +0800",
            "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id tAM9Jvdv006406; \n\tSun, 22 Nov 2015 17:19:57 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.20,331,1444719600\"; d=\"scan'208\";a=\"856882666\"",
        "From": "Jingjing Wu <jingjing.wu@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Sun, 22 Nov 2015 17:19:53 +0800",
        "Message-Id": "<1448183993-6374-1-git-send-email-jingjing.wu@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "Subject": "[dpdk-dev] [PATCH] i40e: fix BW info update if no dcb enabled",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "If DCB is not enabled, the BW info is not stored for VSI. This\npatch fixes this issue by merging functions i40e_vsi_dump_bw_config\nand i40e_vsi_get_bw_info together.\n\nFixes: c8b9a3e3fe1b (i40e: support DCB mode)\n\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 112 +++++++++++++----------------------------\n drivers/net/i40e/i40e_ethdev.h |  12 ++---\n 2 files changed, 40 insertions(+), 84 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 2c51a0b..d7d7a08 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -3789,14 +3789,22 @@ i40e_update_default_filter_setting(struct i40e_vsi *vsi)\n \treturn i40e_vsi_add_mac(vsi, &filter);\n }\n \n+#define I40E_3_BIT_MASK     0x7\n+/*\n+ * i40e_vsi_get_bw_config - Query VSI BW Information\n+ * @vsi: the VSI to be queried\n+ *\n+ * Returns 0 on success, negative value on failure\n+ */\n static int\n-i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)\n+i40e_vsi_get_bw_config(struct i40e_vsi *vsi)\n {\n \tstruct i40e_aqc_query_vsi_bw_config_resp bw_config;\n \tstruct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;\n \tstruct i40e_hw *hw = &vsi->adapter->hw;\n \ti40e_status ret;\n \tint i;\n+\tuint32_t bw_max;\n \n \tmemset(&bw_config, 0, sizeof(bw_config));\n \tret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);\n@@ -3815,17 +3823,29 @@ i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)\n \t\treturn ret;\n \t}\n \n-\t/* Not store the info yet, just print out */\n-\tPMD_DRV_LOG(INFO, \"VSI bw limit:%u\", bw_config.port_bw_limit);\n-\tPMD_DRV_LOG(INFO, \"VSI max_bw:%u\", bw_config.max_bw);\n+\t/* store and print out BW info */\n+\tvsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);\n+\tvsi->bw_info.bw_max = bw_config.max_bw;\n+\tPMD_DRV_LOG(DEBUG, \"VSI bw limit:%u\", bw_config.port_bw_limit);\n+\tPMD_DRV_LOG(DEBUG, \"VSI max_bw:%u\", bw_config.max_bw);\n+\tbw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |\n+\t\t    (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<\n+\t\t     I40E_16_BIT_WIDTH);\n \tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tPMD_DRV_LOG(INFO, \"\\tVSI TC%u:share credits %u\", i,\n-\t\t\t    ets_sla_config.share_credits[i]);\n-\t\tPMD_DRV_LOG(INFO, \"\\tVSI TC%u:credits %u\", i,\n-\t\t\t    rte_le_to_cpu_16(ets_sla_config.credits[i]));\n-\t\tPMD_DRV_LOG(INFO, \"\\tVSI TC%u: max credits: %u\", i,\n-\t\t\t    rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>\n-\t\t\t    (i * 4));\n+\t\tvsi->bw_info.bw_ets_share_credits[i] =\n+\t\t\t\tets_sla_config.share_credits[i];\n+\t\tvsi->bw_info.bw_ets_credits[i] =\n+\t\t\t\trte_le_to_cpu_16(ets_sla_config.credits[i]);\n+\t\t/* 4 bits per TC, 4th bit is reserved */\n+\t\tvsi->bw_info.bw_ets_max[i] =\n+\t\t\t(uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &\n+\t\t\t\t  I40E_3_BIT_MASK);\n+\t\tPMD_DRV_LOG(DEBUG, \"\\tVSI TC%u:share credits %u\", i,\n+\t\t\t    vsi->bw_info.bw_ets_share_credits[i]);\n+\t\tPMD_DRV_LOG(DEBUG, \"\\tVSI TC%u:credits %u\", i,\n+\t\t\t    vsi->bw_info.bw_ets_credits[i]);\n+\t\tPMD_DRV_LOG(DEBUG, \"\\tVSI TC%u: max credits: %u\", i,\n+\t\t\t    vsi->bw_info.bw_ets_max[i]);\n \t}\n \n \treturn 0;\n@@ -4154,7 +4174,7 @@ i40e_vsi_setup(struct i40e_pf *pf,\n \t}\n \n \t/* Get VSI BW information */\n-\ti40e_vsi_dump_bw_config(vsi);\n+\ti40e_vsi_get_bw_config(vsi);\n \treturn vsi;\n fail_msix_alloc:\n \ti40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);\n@@ -8081,70 +8101,6 @@ i40e_parse_dcb_configure(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n-/*\n- * i40e_vsi_get_bw_info - Query VSI BW Information\n- * @vsi: the VSI being queried\n- *\n- * Returns 0 on success, negative value on failure\n- */\n-static enum i40e_status_code\n-i40e_vsi_get_bw_info(struct i40e_vsi *vsi)\n-{\n-\tstruct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};\n-\tstruct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};\n-\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n-\tenum i40e_status_code ret;\n-\tint i;\n-\tuint32_t tc_bw_max;\n-\n-\t/* Get the VSI level BW configuration */\n-\tret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);\n-\tif (ret) {\n-\t\tPMD_INIT_LOG(ERR,\n-\t\t\t \"couldn't get PF vsi bw config, err %s aq_err %s\\n\",\n-\t\t\t i40e_stat_str(hw, ret),\n-\t\t\t i40e_aq_str(hw, hw->aq.asq_last_status));\n-\t\treturn ret;\n-\t}\n-\n-\t/* Get the VSI level BW configuration per TC */\n-\tret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,\n-\t\t\t\t\t\t  NULL);\n-\tif (ret) {\n-\t\tPMD_INIT_LOG(ERR,\n-\t\t\t \"couldn't get PF vsi ets bw config, err %s aq_err %s\\n\",\n-\t\t\t i40e_stat_str(hw, ret),\n-\t\t\t i40e_aq_str(hw, hw->aq.asq_last_status));\n-\t\treturn ret;\n-\t}\n-\n-\tif (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {\n-\t\tPMD_INIT_LOG(WARNING,\n-\t\t\t \"Enabled TCs mismatch from querying VSI BW info\"\n-\t\t\t \" 0x%08x 0x%08x\\n\", bw_config.tc_valid_bits,\n-\t\t\t bw_ets_config.tc_valid_bits);\n-\t\t/* Still continuing */\n-\t}\n-\n-\tvsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);\n-\tvsi->bw_info.bw_max_quanta = bw_config.max_bw;\n-\ttc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |\n-\t\t    (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);\n-\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tvsi->bw_info.bw_ets_share_credits[i] =\n-\t\t\t\tbw_ets_config.share_credits[i];\n-\t\tvsi->bw_info.bw_ets_limit_credits[i] =\n-\t\t\t\trte_le_to_cpu_16(bw_ets_config.credits[i]);\n-\t\t/* 3 bits out of 4 for each TC */\n-\t\tvsi->bw_info.bw_ets_max_quanta[i] =\n-\t\t\t(uint8_t)((tc_bw_max >> (i * 4)) & 0x7);\n-\t\tPMD_INIT_LOG(DEBUG,\n-\t\t\t \"%s: vsi seid = %d, TC = %d, qset = 0x%x\\n\",\n-\t\t\t __func__, vsi->seid, i, bw_config.qs_handles[i]);\n-\t}\n-\n-\treturn ret;\n-}\n \n static enum i40e_status_code\n i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,\n@@ -8278,8 +8234,8 @@ i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)\n \tvsi->info.mapping_flags = ctxt.info.mapping_flags;\n \tvsi->info.valid_sections = 0;\n \n-\t/* Update current VSI BW information */\n-\tret = i40e_vsi_get_bw_info(vsi);\n+\t/* query and update current VSI BW information */\n+\tret = i40e_vsi_get_bw_config(vsi);\n \tif (ret) {\n \t\tPMD_INIT_LOG(ERR,\n \t\t\t \"Failed updating vsi bw info, err %s aq_err %s\",\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex be705f7..1f9792b 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -219,14 +219,14 @@ struct i40e_macvlan_filter {\n /* Bandwidth limit information */\n struct i40e_bw_info {\n \tuint16_t bw_limit;      /* BW Limit (0 = disabled) */\n-\tuint8_t  bw_max_quanta; /* Max Quanta when BW limit is enabled */\n+\tuint8_t  bw_max;        /* Max BW limit if enabled */\n \n-\t/* Relative TC credits across VSIs */\n+\t/* Relative VSI credits within same TC with respect to other VSIs */\n \tuint8_t  bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];\n-\t/* TC BW limit credits within VSI */\n-\tuint8_t  bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];\n-\t/* TC BW limit max quanta within VSI */\n-\tuint8_t  bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];\n+\t/* Bandwidth limit per TC */\n+\tuint8_t  bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];\n+\t/* Max bandwidth limit per TC */\n+\tuint8_t  bw_ets_max[I40E_MAX_TRAFFIC_CLASS];\n };\n \n /*\n",
    "prefixes": [
        "dpdk-dev"
    ]
}