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{
    "id": 90172,
    "url": "http://patches.dpdk.org/api/patches/90172/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210331073632.1443011-5-lizh@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210331073632.1443011-5-lizh@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210331073632.1443011-5-lizh@nvidia.com",
    "date": "2021-03-31T07:36:22",
    "name": "[04/13] net/mlx5: use mask for meter register setting",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "26325ce6d2f1920417ec4832838c62fcdcb7de4b",
    "submitter": {
        "id": 1967,
        "url": "http://patches.dpdk.org/api/people/1967/?format=api",
        "name": "Li Zhang",
        "email": "lizh@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210331073632.1443011-5-lizh@nvidia.com/mbox/",
    "series": [
        {
            "id": 15998,
            "url": "http://patches.dpdk.org/api/series/15998/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15998",
            "date": "2021-03-31T07:36:18",
            "name": "Add ASO meter support in MLX5 PMD",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/15998/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/90172/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/90172/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6BDACA034F;\n\tWed, 31 Mar 2021 09:36:55 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E7747140DF1;\n\tWed, 31 Mar 2021 09:36:47 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 8614A140DF9\n for <dev@dpdk.org>; Wed, 31 Mar 2021 09:36:46 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n lizh@nvidia.com)\n with SMTP; 31 Mar 2021 10:36:41 +0300",
            "from nvidia.com (c-235-17-1-009.mtl.labs.mlnx [10.235.17.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12V7adwC001778;\n Wed, 31 Mar 2021 10:36:41 +0300"
        ],
        "From": "Li Zhang <lizh@nvidia.com>",
        "To": "dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n matan@nvidia.com, shahafs@nvidia.com",
        "Cc": "dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com, roniba@nvidia.com,\n Shun Hao <shunh@nvidia.com>",
        "Date": "Wed, 31 Mar 2021 10:36:22 +0300",
        "Message-Id": "<20210331073632.1443011-5-lizh@nvidia.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20210331073632.1443011-1-lizh@nvidia.com>",
        "References": "<20210331073632.1443011-1-lizh@nvidia.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 04/13] net/mlx5: use mask for meter register\n setting",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Shun Hao <shunh@nvidia.com>\n\nASO meter feature may require to locate the flow\ncontext tag action after the ASO action.\nWhen color register is shared by meter_id/flow_id, it's like:\nBits[0-7] A meter color value set by the HW.\nBits[8-31] A flow id and meter id set by SW.\n\nCurrently the tag action for meter writes all the bits\nof the meter register, so it will potentially overwrite\nmeter color when ASO meter action is before the tag action.\n\nSet only 24-MSB-bits of meter register in the meter tag action.\n\nSigned-off-by: Shun Hao <shunh@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c    | 27 +++++++++++++++++----------\n drivers/net/mlx5/mlx5_flow.h    |  2 ++\n drivers/net/mlx5/mlx5_flow_dv.c |  2 ++\n 3 files changed, 21 insertions(+), 10 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex cffd6129e8..a4bed659f2 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -4274,9 +4274,11 @@ flow_hairpin_split(struct rte_eth_dev *dev,\n \trte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action));\n \tactions_rx++;\n \tset_tag = (void *)actions_rx;\n-\tset_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL);\n+\t*set_tag = (struct mlx5_rte_flow_action_set_tag) {\n+\t\t.id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL),\n+\t\t.data = flow_id,\n+\t};\n \tMLX5_ASSERT(set_tag->id > REG_NON);\n-\tset_tag->data = flow_id;\n \ttag_action->conf = set_tag;\n \t/* Create Tx item list. */\n \trte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action));\n@@ -4511,6 +4513,13 @@ flow_meter_split_prep(struct rte_eth_dev *dev,\n \tset_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre;\n \ttag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items;\n \ttag_item_mask = tag_item_spec + 1;\n+\t/* Both flow_id and meter_id share the same register. */\n+\t*set_tag = (struct mlx5_rte_flow_action_set_tag) {\n+\t\t.id = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 0, error),\n+\t\t.offset = mtr_id_offset,\n+\t\t.length = mtr_reg_bits,\n+\t\t.data = fm->idx,\n+\t};\n \t/*\n \t * The color Reg bits used by flow_id are growing from\n \t * msb to lsb, so must do bit reverse for flow_id val in RegC.\n@@ -4518,12 +4527,8 @@ flow_meter_split_prep(struct rte_eth_dev *dev,\n \tfor (shift = 0; shift < flow_id_bits; shift++)\n \t\tflow_id_val = (flow_id_val << 1) |\n \t\t\t      (((tag_id - 1) >> shift) & 0x1);\n-\t/* Both flow_id and meter_id share the same register. */\n-\tset_tag->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 0, error);\n-\tset_tag->data =\n-\t\t(fm->idx | (flow_id_val << (mtr_reg_bits - flow_id_bits)))\n-\t\t<< mtr_id_offset;\n-\ttag_item_spec->id = set_tag->id;\n+\tset_tag->data |= flow_id_val << (mtr_reg_bits - flow_id_bits);\n+\ttag_item_spec->id = set_tag->id << mtr_id_offset;\n \ttag_item_spec->data = set_tag->data;\n \ttag_item_mask->data = UINT32_MAX << mtr_id_offset;\n \ttag_action->type = (enum rte_flow_action_type)\n@@ -4911,10 +4916,12 @@ flow_sample_split_prep(struct rte_eth_dev *dev,\n \t\tret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n-\t\tset_tag->id = ret;\n \t\tmlx5_ipool_malloc(priv->sh->ipool\n \t\t\t\t  [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id);\n-\t\tset_tag->data = tag_id;\n+\t\t*set_tag = (struct mlx5_rte_flow_action_set_tag) {\n+\t\t\t.id = ret,\n+\t\t\t.data = tag_id,\n+\t\t};\n \t\t/* Prepare the suffix subflow items. */\n \t\ttag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM);\n \t\ttag_spec->data = tag_id;\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 76870b8061..e7f0906209 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -55,6 +55,8 @@ struct mlx5_rte_flow_item_tag {\n /* Modify selected register. */\n struct mlx5_rte_flow_action_set_tag {\n \tenum modify_reg id;\n+\tuint8_t offset;\n+\tuint8_t length;\n \tuint32_t data;\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex d5c8f32038..30fec09987 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -964,6 +964,8 @@ flow_dv_convert_action_set_reg\n \tactions[i] = (struct mlx5_modification_cmd) {\n \t\t.action_type = MLX5_MODIFICATION_TYPE_SET,\n \t\t.field = reg_to_field[conf->id],\n+\t\t.offset = conf->offset,\n+\t\t.length = conf->length,\n \t};\n \tactions[i].data0 = rte_cpu_to_be_32(actions[i].data0);\n \tactions[i].data1 = rte_cpu_to_be_32(conf->data);\n",
    "prefixes": [
        "04/13"
    ]
}