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GET /api/patches/89284/?format=api
{ "id": 89284, "url": "http://patches.dpdk.org/api/patches/89284/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210316221857.2254-8-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210316221857.2254-8-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210316221857.2254-8-timothy.mcdaniel@intel.com", "date": "2021-03-16T22:18:39", "name": "[07/25] event/dlb2: add DLB v2.5 support to create ldb port", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "82d63605baf8ab03b31f7a9580f25842b0d79e71", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210316221857.2254-8-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 15709, "url": "http://patches.dpdk.org/api/series/15709/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15709", "date": "2021-03-16T22:18:32", "name": "Add Support for DLB v2.5", "version": 1, "mbox": "http://patches.dpdk.org/series/15709/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/89284/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/89284/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C6A38A054F;\n\tTue, 16 Mar 2021 23:20:49 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8D750242A68;\n\tTue, 16 Mar 2021 23:20:04 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 8562B242A91\n for <dev@dpdk.org>; Tue, 16 Mar 2021 23:20:00 +0100 (CET)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Mar 2021 15:19:52 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga005.fm.intel.com with ESMTP; 16 Mar 2021 15:19:51 -0700" ], "IronPort-SDR": [ "\n HWiKWmhRT5B3VCi+GDhu/r66ut37Em34P5Mz+HHjdTdNxuY2vjcdlYR4oWIbB1TFiRLQlVPLcG\n Uh1ff0l6vaIg==", "\n sYy3Yxevi/rv2EODvWISg2NEFhDMBMEQeQrgdLLmEtG2/wVBkh8545/xbzqUH30QUp2McCl9nA\n bGpTQQFn2Jzg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9925\"; a=\"253359242\"", "E=Sophos;i=\"5.81,254,1610438400\"; d=\"scan'208\";a=\"253359242\"", "E=Sophos;i=\"5.81,254,1610438400\"; d=\"scan'208\";a=\"605440220\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, harry.van.haaren@intel.com, mdr@ashroe.eu,\n nhorman@tuxdriver.com, nikhil.rao@intel.com, erik.g.carrillo@intel.com,\n abhinandan.gujjar@intel.com, pbhagavatula@marvell.com,\n hemant.agrawal@nxp.com, mattias.ronnblom@ericsson.com,\n peter.mccarthy@intel.com", "Date": "Tue, 16 Mar 2021 17:18:39 -0500", "Message-Id": "<20210316221857.2254-8-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20210316221857.2254-1-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-1-timothy.mcdaniel@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 07/25] event/dlb2: add DLB v2.5 support to create\n ldb port", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update create ldb port low level code to account for new\nregister map and hardware access macros.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_resource.c | 490 ------------------\n .../event/dlb2/pf/base/dlb2_resource_new.c | 471 +++++++++++++++++\n 2 files changed, 471 insertions(+), 490 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 5a8251ee0..d6ff7f6d9 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -1217,496 +1217,6 @@ int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,\n \treturn 0;\n }\n \n-static void dlb2_ldb_port_configure_pp(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_ldb_port *port,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tunion dlb2_sys_ldb_pp2vas r0 = { {0} };\n-\tunion dlb2_sys_ldb_pp_v r4 = { {0} };\n-\n-\tr0.field.vas = domain->id.phys_id;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_PP2VAS(port->id.phys_id), r0.val);\n-\n-\tif (vdev_req) {\n-\t\tunion dlb2_sys_vf_ldb_vpp2pp r1 = { {0} };\n-\t\tunion dlb2_sys_ldb_pp2vdev r2 = { {0} };\n-\t\tunion dlb2_sys_vf_ldb_vpp_v r3 = { {0} };\n-\t\tunsigned int offs;\n-\t\tu32 virt_id;\n-\n-\t\t/*\n-\t\t * DLB uses producer port address bits 17:12 to determine the\n-\t\t * producer port ID. In Scalable IOV mode, PP accesses come\n-\t\t * through the PF MMIO window for the physical producer port,\n-\t\t * so for translation purposes the virtual and physical port\n-\t\t * IDs are equal.\n-\t\t */\n-\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n-\t\t\tvirt_id = port->id.virt_id;\n-\t\telse\n-\t\t\tvirt_id = port->id.phys_id;\n-\n-\t\tr1.field.pp = port->id.phys_id;\n-\n-\t\toffs = vdev_id * DLB2_MAX_NUM_LDB_PORTS + virt_id;\n-\n-\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP2PP(offs), r1.val);\n-\n-\t\tr2.field.vdev = vdev_id;\n-\n-\t\tDLB2_CSR_WR(hw,\n-\t\t\t DLB2_SYS_LDB_PP2VDEV(port->id.phys_id),\n-\t\t\t r2.val);\n-\n-\t\tr3.field.vpp_v = 1;\n-\n-\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP_V(offs), r3.val);\n-\t}\n-\n-\tr4.field.pp_v = 1;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_SYS_LDB_PP_V(port->id.phys_id),\n-\t\t r4.val);\n-}\n-\n-static int dlb2_ldb_port_configure_cq(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_ldb_port *port,\n-\t\t\t\t uintptr_t cq_dma_base,\n-\t\t\t\t struct dlb2_create_ldb_port_args *args,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tunion dlb2_sys_ldb_cq_addr_l r0 = { {0} };\n-\tunion dlb2_sys_ldb_cq_addr_u r1 = { {0} };\n-\tunion dlb2_sys_ldb_cq2vf_pf_ro r2 = { {0} };\n-\tunion dlb2_chp_ldb_cq_tkn_depth_sel r3 = { {0} };\n-\tunion dlb2_lsp_cq_ldb_tkn_depth_sel r4 = { {0} };\n-\tunion dlb2_chp_hist_list_lim r5 = { {0} };\n-\tunion dlb2_chp_hist_list_base r6 = { {0} };\n-\tunion dlb2_lsp_cq_ldb_infl_lim r7 = { {0} };\n-\tunion dlb2_chp_hist_list_push_ptr r8 = { {0} };\n-\tunion dlb2_chp_hist_list_pop_ptr r9 = { {0} };\n-\tunion dlb2_sys_ldb_cq_at r10 = { {0} };\n-\tunion dlb2_sys_ldb_cq_pasid r11 = { {0} };\n-\tunion dlb2_chp_ldb_cq2vas r12 = { {0} };\n-\tunion dlb2_lsp_cq2priov r13 = { {0} };\n-\n-\t/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */\n-\tr0.field.addr_l = cq_dma_base >> 6;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_L(port->id.phys_id), r0.val);\n-\n-\tr1.field.addr_u = cq_dma_base >> 32;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_U(port->id.phys_id), r1.val);\n-\n-\t/*\n-\t * 'ro' == relaxed ordering. This setting allows DLB2 to write\n-\t * cache lines out-of-order (but QEs within a cache line are always\n-\t * updated in-order).\n-\t */\n-\tr2.field.vf = vdev_id;\n-\tr2.field.is_pf = !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV);\n-\tr2.field.ro = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ2VF_PF_RO(port->id.phys_id), r2.val);\n-\n-\tif (args->cq_depth <= 8) {\n-\t\tr3.field.token_depth_select = 1;\n-\t} else if (args->cq_depth == 16) {\n-\t\tr3.field.token_depth_select = 2;\n-\t} else if (args->cq_depth == 32) {\n-\t\tr3.field.token_depth_select = 3;\n-\t} else if (args->cq_depth == 64) {\n-\t\tr3.field.token_depth_select = 4;\n-\t} else if (args->cq_depth == 128) {\n-\t\tr3.field.token_depth_select = 5;\n-\t} else if (args->cq_depth == 256) {\n-\t\tr3.field.token_depth_select = 6;\n-\t} else if (args->cq_depth == 512) {\n-\t\tr3.field.token_depth_select = 7;\n-\t} else if (args->cq_depth == 1024) {\n-\t\tr3.field.token_depth_select = 8;\n-\t} else {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: invalid CQ depth\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(port->id.phys_id),\n-\t\t r3.val);\n-\n-\t/*\n-\t * To support CQs with depth less than 8, program the token count\n-\t * register with a non-zero initial value. Operations such as domain\n-\t * reset must take this initial value into account when quiescing the\n-\t * CQ.\n-\t */\n-\tport->init_tkn_cnt = 0;\n-\n-\tif (args->cq_depth < 8) {\n-\t\tunion dlb2_lsp_cq_ldb_tkn_cnt r14 = { {0} };\n-\n-\t\tport->init_tkn_cnt = 8 - args->cq_depth;\n-\n-\t\tr14.field.token_count = port->init_tkn_cnt;\n-\n-\t\tDLB2_CSR_WR(hw,\n-\t\t\t DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id),\n-\t\t\t r14.val);\n-\t} else {\n-\t\tDLB2_CSR_WR(hw,\n-\t\t\t DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id),\n-\t\t\t DLB2_LSP_CQ_LDB_TKN_CNT_RST);\n-\t}\n-\n-\tr4.field.token_depth_select = r3.field.token_depth_select;\n-\tr4.field.ignore_depth = 0;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(port->id.phys_id),\n-\t\t r4.val);\n-\n-\t/* Reset the CQ write pointer */\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_CHP_LDB_CQ_WPTR(port->id.phys_id),\n-\t\t DLB2_CHP_LDB_CQ_WPTR_RST);\n-\n-\tr5.field.limit = port->hist_list_entry_limit - 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_LIM(port->id.phys_id), r5.val);\n-\n-\tr6.field.base = port->hist_list_entry_base;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_BASE(port->id.phys_id), r6.val);\n-\n-\t/*\n-\t * The inflight limit sets a cap on the number of QEs for which this CQ\n-\t * can owe completions at one time.\n-\t */\n-\tr7.field.limit = args->cq_history_list_size;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_INFL_LIM(port->id.phys_id), r7.val);\n-\n-\tr8.field.push_ptr = r6.field.base;\n-\tr8.field.generation = 0;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_CHP_HIST_LIST_PUSH_PTR(port->id.phys_id),\n-\t\t r8.val);\n-\n-\tr9.field.pop_ptr = r6.field.base;\n-\tr9.field.generation = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_POP_PTR(port->id.phys_id), r9.val);\n-\n-\t/*\n-\t * Address translation (AT) settings: 0: untranslated, 2: translated\n-\t * (see ATS spec regarding Address Type field for more details)\n-\t */\n-\tr10.field.cq_at = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_AT(port->id.phys_id), r10.val);\n-\n-\tif (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {\n-\t\tr11.field.pasid = hw->pasid[vdev_id];\n-\t\tr11.field.fmt2 = 1;\n-\t}\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_SYS_LDB_CQ_PASID(port->id.phys_id),\n-\t\t r11.val);\n-\n-\tr12.field.cq2vas = domain->id.phys_id;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_LDB_CQ2VAS(port->id.phys_id), r12.val);\n-\n-\t/* Disable the port's QID mappings */\n-\tr13.field.v = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(port->id.phys_id), r13.val);\n-\n-\treturn 0;\n-}\n-\n-static int dlb2_configure_ldb_port(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_ldb_port *port,\n-\t\t\t\t uintptr_t cq_dma_base,\n-\t\t\t\t struct dlb2_create_ldb_port_args *args,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tint ret, i;\n-\n-\tport->hist_list_entry_base = domain->hist_list_entry_base +\n-\t\t\t\t domain->hist_list_entry_offset;\n-\tport->hist_list_entry_limit = port->hist_list_entry_base +\n-\t\t\t\t args->cq_history_list_size;\n-\n-\tdomain->hist_list_entry_offset += args->cq_history_list_size;\n-\tdomain->avail_hist_list_entries -= args->cq_history_list_size;\n-\n-\tret = dlb2_ldb_port_configure_cq(hw,\n-\t\t\t\t\t domain,\n-\t\t\t\t\t port,\n-\t\t\t\t\t cq_dma_base,\n-\t\t\t\t\t args,\n-\t\t\t\t\t vdev_req,\n-\t\t\t\t\t vdev_id);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tdlb2_ldb_port_configure_pp(hw,\n-\t\t\t\t domain,\n-\t\t\t\t port,\n-\t\t\t\t vdev_req,\n-\t\t\t\t vdev_id);\n-\n-\tdlb2_ldb_port_cq_enable(hw, port);\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++)\n-\t\tport->qid_map[i].state = DLB2_QUEUE_UNMAPPED;\n-\tport->num_mappings = 0;\n-\n-\tport->enabled = true;\n-\n-\tport->configured = true;\n-\n-\treturn 0;\n-}\n-\n-static void\n-dlb2_log_create_ldb_port_args(struct dlb2_hw *hw,\n-\t\t\t u32 domain_id,\n-\t\t\t uintptr_t cq_dma_base,\n-\t\t\t struct dlb2_create_ldb_port_args *args,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n-{\n-\tDLB2_HW_DBG(hw, \"DLB2 create load-balanced port arguments:\\n\");\n-\tif (vdev_req)\n-\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n-\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\",\n-\t\t domain_id);\n-\tDLB2_HW_DBG(hw, \"\\tCQ depth: %d\\n\",\n-\t\t args->cq_depth);\n-\tDLB2_HW_DBG(hw, \"\\tCQ hist list size: %d\\n\",\n-\t\t args->cq_history_list_size);\n-\tDLB2_HW_DBG(hw, \"\\tCQ base address: 0x%lx\\n\",\n-\t\t cq_dma_base);\n-\tDLB2_HW_DBG(hw, \"\\tCoS ID: %u\\n\", args->cos_id);\n-\tDLB2_HW_DBG(hw, \"\\tStrict CoS allocation: %u\\n\",\n-\t\t args->cos_strict);\n-}\n-\n-static int\n-dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw,\n-\t\t\t\t u32 domain_id,\n-\t\t\t\t uintptr_t cq_dma_base,\n-\t\t\t\t struct dlb2_create_ldb_port_args *args,\n-\t\t\t\t struct dlb2_cmd_response *resp,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tstruct dlb2_hw_domain *domain;\n-\tint i;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n-\n-\tif (domain == NULL) {\n-\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!domain->configured) {\n-\t\tresp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (domain->started) {\n-\t\tresp->status = DLB2_ST_DOMAIN_STARTED;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (args->cos_id >= DLB2_NUM_COS_DOMAINS) {\n-\t\tresp->status = DLB2_ST_INVALID_COS_ID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (args->cos_strict) {\n-\t\tif (dlb2_list_empty(&domain->avail_ldb_ports[args->cos_id])) {\n-\t\t\tresp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else {\n-\t\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\t\tif (!dlb2_list_empty(&domain->avail_ldb_ports[i]))\n-\t\t\t\tbreak;\n-\t\t}\n-\n-\t\tif (i == DLB2_NUM_COS_DOMAINS) {\n-\t\t\tresp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/* Check cache-line alignment */\n-\tif ((cq_dma_base & 0x3F) != 0) {\n-\t\tresp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (args->cq_depth != 1 &&\n-\t args->cq_depth != 2 &&\n-\t args->cq_depth != 4 &&\n-\t args->cq_depth != 8 &&\n-\t args->cq_depth != 16 &&\n-\t args->cq_depth != 32 &&\n-\t args->cq_depth != 64 &&\n-\t args->cq_depth != 128 &&\n-\t args->cq_depth != 256 &&\n-\t args->cq_depth != 512 &&\n-\t args->cq_depth != 1024) {\n-\t\tresp->status = DLB2_ST_INVALID_CQ_DEPTH;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* The history list size must be >= 1 */\n-\tif (!args->cq_history_list_size) {\n-\t\tresp->status = DLB2_ST_INVALID_HIST_LIST_DEPTH;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (args->cq_history_list_size > domain->avail_hist_list_entries) {\n-\t\tresp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-\n-/**\n- * dlb2_hw_create_ldb_port() - Allocate and initialize a load-balanced port and\n- *\tits resources.\n- * @hw:\tContains the current state of the DLB2 hardware.\n- * @domain_id: Domain ID\n- * @args: User-provided arguments.\n- * @cq_dma_base: Base DMA address for consumer queue memory\n- * @resp: Response to user.\n- * @vdev_req: Request came from a virtual device.\n- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.\n- *\n- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to\n- * satisfy a request, resp->status will be set accordingly.\n- */\n-int dlb2_hw_create_ldb_port(struct dlb2_hw *hw,\n-\t\t\t u32 domain_id,\n-\t\t\t struct dlb2_create_ldb_port_args *args,\n-\t\t\t uintptr_t cq_dma_base,\n-\t\t\t struct dlb2_cmd_response *resp,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n-{\n-\tstruct dlb2_hw_domain *domain;\n-\tstruct dlb2_ldb_port *port;\n-\tint ret, cos_id, i;\n-\n-\tdlb2_log_create_ldb_port_args(hw,\n-\t\t\t\t domain_id,\n-\t\t\t\t cq_dma_base,\n-\t\t\t\t args,\n-\t\t\t\t vdev_req,\n-\t\t\t\t vdev_id);\n-\n-\t/*\n-\t * Verify that hardware resources are available before attempting to\n-\t * satisfy the request. This simplifies the error unwinding code.\n-\t */\n-\tret = dlb2_verify_create_ldb_port_args(hw,\n-\t\t\t\t\t domain_id,\n-\t\t\t\t\t cq_dma_base,\n-\t\t\t\t\t args,\n-\t\t\t\t\t resp,\n-\t\t\t\t\t vdev_req,\n-\t\t\t\t\t vdev_id);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n-\tif (domain == NULL) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: domain not found\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tif (args->cos_strict) {\n-\t\tcos_id = args->cos_id;\n-\n-\t\tport = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[cos_id],\n-\t\t\t\t\t typeof(*port));\n-\t} else {\n-\t\tint idx;\n-\n-\t\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\t\tidx = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS;\n-\n-\t\t\tport = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[idx],\n-\t\t\t\t\t\t typeof(*port));\n-\t\t\tif (port)\n-\t\t\t\tbreak;\n-\t\t}\n-\n-\t\tcos_id = idx;\n-\t}\n-\n-\tif (port == NULL) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: no available ldb ports\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tif (port->configured) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s()] Internal error: avail_ldb_ports contains configured ports.\\n\",\n-\t\t\t __func__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tret = dlb2_configure_ldb_port(hw,\n-\t\t\t\t domain,\n-\t\t\t\t port,\n-\t\t\t\t cq_dma_base,\n-\t\t\t\t args,\n-\t\t\t\t vdev_req,\n-\t\t\t\t vdev_id);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\t/*\n-\t * Configuration succeeded, so move the resource from the 'avail' to\n-\t * the 'used' list.\n-\t */\n-\tdlb2_list_del(&domain->avail_ldb_ports[cos_id], &port->domain_list);\n-\n-\tdlb2_list_add(&domain->used_ldb_ports[cos_id], &port->domain_list);\n-\n-\tresp->status = 0;\n-\tresp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;\n-\n-\treturn 0;\n-}\n-\n static void\n dlb2_log_create_dir_port_args(struct dlb2_hw *hw,\n \t\t\t u32 domain_id,\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 811cf79c6..31afdc5f9 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -3973,3 +3973,474 @@ int dlb2_hw_create_ldb_queue(struct dlb2_hw *hw,\n \n \treturn 0;\n }\n+\n+static void dlb2_ldb_port_configure_pp(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tu32 reg = 0;\n+\n+\tDLB2_BITS_SET(reg, domain->id.phys_id, DLB2_SYS_LDB_PP2VAS_VAS);\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_PP2VAS(port->id.phys_id), reg);\n+\n+\tif (vdev_req) {\n+\t\tunsigned int offs;\n+\t\tu32 virt_id;\n+\n+\t\t/*\n+\t\t * DLB uses producer port address bits 17:12 to determine the\n+\t\t * producer port ID. In Scalable IOV mode, PP accesses come\n+\t\t * through the PF MMIO window for the physical producer port,\n+\t\t * so for translation purposes the virtual and physical port\n+\t\t * IDs are equal.\n+\t\t */\n+\t\tif (hw->virt_mode == DLB2_VIRT_SRIOV)\n+\t\t\tvirt_id = port->id.virt_id;\n+\t\telse\n+\t\t\tvirt_id = port->id.phys_id;\n+\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, port->id.phys_id, DLB2_SYS_VF_LDB_VPP2PP_PP);\n+\t\toffs = vdev_id * DLB2_MAX_NUM_LDB_PORTS + virt_id;\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP2PP(offs), reg);\n+\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, vdev_id, DLB2_SYS_LDB_PP2VDEV_VDEV);\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_PP2VDEV(port->id.phys_id), reg);\n+\n+\t\treg = 0;\n+\t\tDLB2_BIT_SET(reg, DLB2_SYS_VF_LDB_VPP_V_VPP_V);\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP_V(offs), reg);\n+\t}\n+\n+\treg = 0;\n+\tDLB2_BIT_SET(reg, DLB2_SYS_LDB_PP_V_PP_V);\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_PP_V(port->id.phys_id), reg);\n+}\n+\n+static int dlb2_ldb_port_configure_cq(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t uintptr_t cq_dma_base,\n+\t\t\t\t struct dlb2_create_ldb_port_args *args,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tu32 hl_base = 0;\n+\tu32 reg = 0;\n+\tu32 ds = 0;\n+\n+\t/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */\n+\tDLB2_BITS_SET(reg, cq_dma_base >> 6, DLB2_SYS_LDB_CQ_ADDR_L_ADDR_L);\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_L(port->id.phys_id), reg);\n+\n+\treg = cq_dma_base >> 32;\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_U(port->id.phys_id), reg);\n+\n+\t/*\n+\t * 'ro' == relaxed ordering. This setting allows DLB2 to write\n+\t * cache lines out-of-order (but QEs within a cache line are always\n+\t * updated in-order).\n+\t */\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, vdev_id, DLB2_SYS_LDB_CQ2VF_PF_RO_VF);\n+\tDLB2_BITS_SET(reg,\n+\t\t !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV),\n+\t\t DLB2_SYS_LDB_CQ2VF_PF_RO_IS_PF);\n+\tDLB2_BIT_SET(reg, DLB2_SYS_LDB_CQ2VF_PF_RO_RO);\n+\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ2VF_PF_RO(port->id.phys_id), reg);\n+\n+\tport->cq_depth = args->cq_depth;\n+\n+\tif (args->cq_depth <= 8) {\n+\t\tds = 1;\n+\t} else if (args->cq_depth == 16) {\n+\t\tds = 2;\n+\t} else if (args->cq_depth == 32) {\n+\t\tds = 3;\n+\t} else if (args->cq_depth == 64) {\n+\t\tds = 4;\n+\t} else if (args->cq_depth == 128) {\n+\t\tds = 5;\n+\t} else if (args->cq_depth == 256) {\n+\t\tds = 6;\n+\t} else if (args->cq_depth == 512) {\n+\t\tds = 7;\n+\t} else if (args->cq_depth == 1024) {\n+\t\tds = 8;\n+\t} else {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: invalid CQ depth\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, ds,\n+\t\t DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(hw->ver, port->id.phys_id),\n+\t\t reg);\n+\n+\t/*\n+\t * To support CQs with depth less than 8, program the token count\n+\t * register with a non-zero initial value. Operations such as domain\n+\t * reset must take this initial value into account when quiescing the\n+\t * CQ.\n+\t */\n+\tport->init_tkn_cnt = 0;\n+\n+\tif (args->cq_depth < 8) {\n+\t\treg = 0;\n+\t\tport->init_tkn_cnt = 8 - args->cq_depth;\n+\n+\t\tDLB2_BITS_SET(reg,\n+\t\t\t port->init_tkn_cnt,\n+\t\t\t DLB2_LSP_CQ_LDB_TKN_CNT_TOKEN_COUNT);\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_CQ_LDB_TKN_CNT(hw->ver, port->id.phys_id),\n+\t\t\t reg);\n+\t} else {\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_CQ_LDB_TKN_CNT(hw->ver, port->id.phys_id),\n+\t\t\t DLB2_LSP_CQ_LDB_TKN_CNT_RST);\n+\t}\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, ds,\n+\t\t DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL_TOKEN_DEPTH_SELECT_V2);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(hw->ver, port->id.phys_id),\n+\t\t reg);\n+\n+\t/* Reset the CQ write pointer */\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_LDB_CQ_WPTR(hw->ver, port->id.phys_id),\n+\t\t DLB2_CHP_LDB_CQ_WPTR_RST);\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg,\n+\t\t port->hist_list_entry_limit - 1,\n+\t\t DLB2_CHP_HIST_LIST_LIM_LIMIT);\n+\tDLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_LIM(hw->ver, port->id.phys_id), reg);\n+\n+\tDLB2_BITS_SET(hl_base, port->hist_list_entry_base,\n+\t\t DLB2_CHP_HIST_LIST_BASE_BASE);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_HIST_LIST_BASE(hw->ver, port->id.phys_id),\n+\t\t hl_base);\n+\n+\t/*\n+\t * The inflight limit sets a cap on the number of QEs for which this CQ\n+\t * can owe completions at one time.\n+\t */\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, args->cq_history_list_size,\n+\t\t DLB2_LSP_CQ_LDB_INFL_LIM_LIMIT);\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_INFL_LIM(hw->ver, port->id.phys_id),\n+\t\t reg);\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, DLB2_BITS_GET(hl_base, DLB2_CHP_HIST_LIST_BASE_BASE),\n+\t\t DLB2_CHP_HIST_LIST_PUSH_PTR_PUSH_PTR);\n+\tDLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_PUSH_PTR(hw->ver, port->id.phys_id),\n+\t\t reg);\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, DLB2_BITS_GET(hl_base, DLB2_CHP_HIST_LIST_BASE_BASE),\n+\t\t DLB2_CHP_HIST_LIST_POP_PTR_POP_PTR);\n+\tDLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_POP_PTR(hw->ver, port->id.phys_id),\n+\t\t reg);\n+\n+\t/*\n+\t * Address translation (AT) settings: 0: untranslated, 2: translated\n+\t * (see ATS spec regarding Address Type field for more details)\n+\t */\n+\n+\tif (hw->ver == DLB2_HW_V2) {\n+\t\treg = 0;\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_AT(port->id.phys_id), reg);\n+\t}\n+\n+\tif (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, hw->pasid[vdev_id],\n+\t\t\t DLB2_SYS_LDB_CQ_PASID_PASID);\n+\t\tDLB2_BIT_SET(reg, DLB2_SYS_LDB_CQ_PASID_FMT2);\n+\t}\n+\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_PASID(hw->ver, port->id.phys_id), reg);\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, domain->id.phys_id, DLB2_CHP_LDB_CQ2VAS_CQ2VAS);\n+\tDLB2_CSR_WR(hw, DLB2_CHP_LDB_CQ2VAS(hw->ver, port->id.phys_id), reg);\n+\n+\t/* Disable the port's QID mappings */\n+\treg = 0;\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(hw->ver, port->id.phys_id), reg);\n+\n+\treturn 0;\n+}\n+\n+static bool\n+dlb2_cq_depth_is_valid(u32 depth)\n+{\n+\tif (depth != 1 && depth != 2 &&\n+\t depth != 4 && depth != 8 &&\n+\t depth != 16 && depth != 32 &&\n+\t depth != 64 && depth != 128 &&\n+\t depth != 256 && depth != 512 &&\n+\t depth != 1024)\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+static int dlb2_configure_ldb_port(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_ldb_port *port,\n+\t\t\t\t uintptr_t cq_dma_base,\n+\t\t\t\t struct dlb2_create_ldb_port_args *args,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tint ret, i;\n+\n+\tport->hist_list_entry_base = domain->hist_list_entry_base +\n+\t\t\t\t domain->hist_list_entry_offset;\n+\tport->hist_list_entry_limit = port->hist_list_entry_base +\n+\t\t\t\t args->cq_history_list_size;\n+\n+\tdomain->hist_list_entry_offset += args->cq_history_list_size;\n+\tdomain->avail_hist_list_entries -= args->cq_history_list_size;\n+\n+\tret = dlb2_ldb_port_configure_cq(hw,\n+\t\t\t\t\t domain,\n+\t\t\t\t\t port,\n+\t\t\t\t\t cq_dma_base,\n+\t\t\t\t\t args,\n+\t\t\t\t\t vdev_req,\n+\t\t\t\t\t vdev_id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdlb2_ldb_port_configure_pp(hw,\n+\t\t\t\t domain,\n+\t\t\t\t port,\n+\t\t\t\t vdev_req,\n+\t\t\t\t vdev_id);\n+\n+\tdlb2_ldb_port_cq_enable(hw, port);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++)\n+\t\tport->qid_map[i].state = DLB2_QUEUE_UNMAPPED;\n+\tport->num_mappings = 0;\n+\n+\tport->enabled = true;\n+\n+\tport->configured = true;\n+\n+\treturn 0;\n+}\n+\n+static void\n+dlb2_log_create_ldb_port_args(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t uintptr_t cq_dma_base,\n+\t\t\t struct dlb2_create_ldb_port_args *args,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tDLB2_HW_DBG(hw, \"DLB2 create load-balanced port arguments:\\n\");\n+\tif (vdev_req)\n+\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n+\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\",\n+\t\t domain_id);\n+\tDLB2_HW_DBG(hw, \"\\tCQ depth: %d\\n\",\n+\t\t args->cq_depth);\n+\tDLB2_HW_DBG(hw, \"\\tCQ hist list size: %d\\n\",\n+\t\t args->cq_history_list_size);\n+\tDLB2_HW_DBG(hw, \"\\tCQ base address: 0x%lx\\n\",\n+\t\t cq_dma_base);\n+\tDLB2_HW_DBG(hw, \"\\tCoS ID: %u\\n\", args->cos_id);\n+\tDLB2_HW_DBG(hw, \"\\tStrict CoS allocation: %u\\n\",\n+\t\t args->cos_strict);\n+}\n+\n+static int\n+dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw,\n+\t\t\t\t u32 domain_id,\n+\t\t\t\t uintptr_t cq_dma_base,\n+\t\t\t\t struct dlb2_create_ldb_port_args *args,\n+\t\t\t\t struct dlb2_cmd_response *resp,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id,\n+\t\t\t\t struct dlb2_hw_domain **out_domain,\n+\t\t\t\t struct dlb2_ldb_port **out_port,\n+\t\t\t\t int *out_cos_id)\n+{\n+\tstruct dlb2_hw_domain *domain;\n+\tstruct dlb2_ldb_port *port;\n+\tint i, id;\n+\n+\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n+\n+\tif (!domain) {\n+\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!domain->configured) {\n+\t\tresp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (domain->started) {\n+\t\tresp->status = DLB2_ST_DOMAIN_STARTED;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (args->cos_id >= DLB2_NUM_COS_DOMAINS) {\n+\t\tresp->status = DLB2_ST_INVALID_COS_ID;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (args->cos_strict) {\n+\t\tid = args->cos_id;\n+\t\tport = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[id],\n+\t\t\t\t\t typeof(*port));\n+\t} else {\n+\t\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\t\tid = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS;\n+\n+\t\t\tport = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[id],\n+\t\t\t\t\t\t typeof(*port));\n+\t\t\tif (port)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!port) {\n+\t\tresp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Check cache-line alignment */\n+\tif ((cq_dma_base & 0x3F) != 0) {\n+\t\tresp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!dlb2_cq_depth_is_valid(args->cq_depth)) {\n+\t\tresp->status = DLB2_ST_INVALID_CQ_DEPTH;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* The history list size must be >= 1 */\n+\tif (!args->cq_history_list_size) {\n+\t\tresp->status = DLB2_ST_INVALID_HIST_LIST_DEPTH;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (args->cq_history_list_size > domain->avail_hist_list_entries) {\n+\t\tresp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*out_domain = domain;\n+\t*out_port = port;\n+\t*out_cos_id = id;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * dlb2_hw_create_ldb_port() - create a load-balanced port\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: port creation arguments.\n+ * @cq_dma_base: base address of the CQ memory. This can be a PA or an IOVA.\n+ * @resp: response structure.\n+ * @vdev_req: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_req is true, this contains the vdev's ID.\n+ *\n+ * This function creates a load-balanced port.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the port ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_req is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, a credit setting is invalid, a\n+ *\t pointer address is not properly aligned, the domain is not\n+ *\t configured, or the domain has already been started.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_ldb_port(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t struct dlb2_create_ldb_port_args *args,\n+\t\t\t uintptr_t cq_dma_base,\n+\t\t\t struct dlb2_cmd_response *resp,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_hw_domain *domain;\n+\tstruct dlb2_ldb_port *port;\n+\tint ret, cos_id;\n+\n+\tdlb2_log_create_ldb_port_args(hw,\n+\t\t\t\t domain_id,\n+\t\t\t\t cq_dma_base,\n+\t\t\t\t args,\n+\t\t\t\t vdev_req,\n+\t\t\t\t vdev_id);\n+\n+\t/*\n+\t * Verify that hardware resources are available before attempting to\n+\t * satisfy the request. This simplifies the error unwinding code.\n+\t */\n+\tret = dlb2_verify_create_ldb_port_args(hw,\n+\t\t\t\t\t domain_id,\n+\t\t\t\t\t cq_dma_base,\n+\t\t\t\t\t args,\n+\t\t\t\t\t resp,\n+\t\t\t\t\t vdev_req,\n+\t\t\t\t\t vdev_id,\n+\t\t\t\t\t &domain,\n+\t\t\t\t\t &port,\n+\t\t\t\t\t &cos_id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dlb2_configure_ldb_port(hw,\n+\t\t\t\t domain,\n+\t\t\t\t port,\n+\t\t\t\t cq_dma_base,\n+\t\t\t\t args,\n+\t\t\t\t vdev_req,\n+\t\t\t\t vdev_id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * Configuration succeeded, so move the resource from the 'avail' to\n+\t * the 'used' list.\n+\t */\n+\tdlb2_list_del(&domain->avail_ldb_ports[cos_id], &port->domain_list);\n+\n+\tdlb2_list_add(&domain->used_ldb_ports[cos_id], &port->domain_list);\n+\n+\tresp->status = 0;\n+\tresp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;\n+\n+\treturn 0;\n+}\n", "prefixes": [ "07/25" ] }