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GET /api/patches/89107/?format=api
{ "id": 89107, "url": "http://patches.dpdk.org/api/patches/89107/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210315090150.69239-1-murphyx.yang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210315090150.69239-1-murphyx.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210315090150.69239-1-murphyx.yang@intel.com", "date": "2021-03-15T09:01:50", "name": "[RFC] net/i40e: change the timing of FDIR input set configuration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f51712f7901f38ec81b4259c502e24d85b885dc1", "submitter": { "id": 1986, "url": "http://patches.dpdk.org/api/people/1986/?format=api", "name": "Murphy Yang", "email": "murphyx.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210315090150.69239-1-murphyx.yang@intel.com/mbox/", "series": [ { "id": 15652, "url": "http://patches.dpdk.org/api/series/15652/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15652", "date": "2021-03-15T09:01:50", "name": "[RFC] net/i40e: change the timing of FDIR input set configuration", "version": 1, "mbox": "http://patches.dpdk.org/series/15652/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/89107/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/89107/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 01613A054F;\n\tMon, 15 Mar 2021 10:08:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A6DF92425E6;\n\tMon, 15 Mar 2021 10:08:52 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 0794C4003C\n for <dev@dpdk.org>; Mon, 15 Mar 2021 10:08:50 +0100 (CET)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Mar 2021 02:08:49 -0700", "from unknown (HELO intel-npg-odc-srv02.cd.intel.com)\n ([10.240.178.186])\n by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Mar 2021 02:08:47 -0700" ], "IronPort-SDR": [ "\n 5Vd3SAv0g3trTV/TQzG6H+HLR9O6wWHtL/AvMozCqtt6eZHqVs1BpYyZVg1iok0SjVV7zFFJIM\n PwllXlbttxeg==", "\n tHwAf4K8G036szVC46Fz9zBshVbuM7zN65x+kVJ/v8S2LgfgpAvheLP6hMK8VuvgJQ143RwpSc\n fav4zZXEG2vw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9923\"; a=\"168328557\"", "E=Sophos;i=\"5.81,249,1610438400\"; d=\"scan'208\";a=\"168328557\"", "E=Sophos;i=\"5.81,249,1610438400\"; d=\"scan'208\";a=\"411771515\"" ], "From": "Murphy Yang <murphyx.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qiming.yang@intel.com, jia.guo@intel.com, beilei.xing@intel.com,\n stevex.yang@intel.com, robinx.zhang@intel.com,\n Murphy Yang <murphyx.yang@intel.com>", "Date": "Mon, 15 Mar 2021 09:01:50 +0000", "Message-Id": "<20210315090150.69239-1-murphyx.yang@intel.com>", "X-Mailer": "git-send-email 2.17.1", "Subject": "[dpdk-dev] [RFC] net/i40e: change the timing of FDIR input set\n configuration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The configuration of FDIR input set should not be set\nduring flow validate. It should be set when flow create.\n\nSigned-off-by: Murphy Yang <murphyx.yang@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.h | 1 +\n drivers/net/i40e/i40e_fdir.c | 88 +++++++++++++++++++++++++++++++\n drivers/net/i40e/i40e_flow.c | 95 +++-------------------------------\n 3 files changed, 96 insertions(+), 88 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 1e8f5d3a87..c6ec071f44 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -631,6 +631,7 @@ struct i40e_fdir_flow_ext {\n \tuint8_t raw_id;\n \tuint8_t is_vf; /* 1 for VF, 0 for port dev */\n \tuint16_t dst_id; /* VF ID, available when is_vf is 1*/\n+\tuint64_t input_set;\n \tbool inner_ip; /* If there is inner ip */\n \tenum i40e_fdir_ip_type iip_type; /* ip type for inner ip */\n \tenum i40e_fdir_ip_type oip_type; /* ip type for outer ip */\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex c572d003cb..af0c00de04 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -1588,6 +1588,83 @@ i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,\n \tpf->fdir.flex_mask_flag[pctype] = 1;\n }\n \n+static int\n+i40e_flow_set_fdir_inset(struct i40e_pf *pf,\n+\t\t\t enum i40e_filter_pctype pctype,\n+\t\t\t uint64_t input_set)\n+{\n+\tuint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint64_t inset_reg = 0;\n+\tint i, num;\n+\n+\t/* Check if the input set is valid */\n+\tif (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,\n+\t\t\t\t input_set) != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid input set\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Check if the configuration is conflicted */\n+\tif (pf->fdir.inset_flag[pctype] &&\n+\t memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))\n+\t\treturn -1;\n+\n+\tif (pf->fdir.inset_flag[pctype] &&\n+\t !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))\n+\t\treturn 0;\n+\n+\tnum = i40e_generate_inset_mask_reg(input_set, mask_reg,\n+\t\t\t\t\t I40E_INSET_MASK_NUM_REG);\n+\tif (num < 0)\n+\t\treturn -EINVAL;\n+\n+\tif (pf->support_multi_driver) {\n+\t\tfor (i = 0; i < num; i++)\n+\t\t\tif (i40e_read_rx_ctl(hw,\n+\t\t\t\t\tI40E_GLQF_FD_MSK(i, pctype)) !=\n+\t\t\t\t\tmask_reg[i]) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not\"\n+\t\t\t\t\t\t\" supported with\"\n+\t\t\t\t\t\t\" `support-multi-driver`\"\n+\t\t\t\t\t\t\" enabled!\");\n+\t\t\t\treturn -EPERM;\n+\t\t\t}\n+\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n+\t\t\tif (i40e_read_rx_ctl(hw,\n+\t\t\t\t\tI40E_GLQF_FD_MSK(i, pctype)) != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not\"\n+\t\t\t\t\t\t\" supported with\"\n+\t\t\t\t\t\t\" `support-multi-driver`\"\n+\t\t\t\t\t\t\" enabled!\");\n+\t\t\t\treturn -EPERM;\n+\t\t\t}\n+\n+\t} else {\n+\t\tfor (i = 0; i < num; i++)\n+\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n+\t\t\t\tmask_reg[i]);\n+\t\t/*clear unused mask registers of the pctype */\n+\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n+\t\t\ti40e_check_write_reg(hw,\n+\t\t\t\t\tI40E_GLQF_FD_MSK(i, pctype), 0);\n+\t}\n+\n+\tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n+\n+\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),\n+\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n+\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n+\t\t\t (uint32_t)((inset_reg >>\n+\t\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n+\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\tpf->fdir.input_set[pctype] = input_set;\n+\tpf->fdir.inset_flag[pctype] = 1;\n+\treturn 0;\n+}\n+\n static inline unsigned char *\n i40e_find_available_buffer(struct rte_eth_dev *dev)\n {\n@@ -1686,6 +1763,17 @@ i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,\n \n \tif (add) {\n \t\tif (filter->input.flow_ext.is_flex_flow) {\n+\t\t\tret = i40e_flow_set_fdir_inset(pf, pctype,\n+\t\t\t\t\tfilter->input.flow_ext.input_set);\n+\t\t\tif (ret == -1) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Conflict with the\"\n+\t\t\t\t\t \" first rule's input set.\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t} else if (ret == -EINVAL) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Invalid pattern mask.\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\n \t\t\tfor (i = 0; i < filter->input.flow_ext.raw_id; i++) {\n \t\t\t\tlayer_idx = filter->input.flow_ext.layer_idx;\n \t\t\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\ndiff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c\nindex 3e514d5f38..d1d14c5ae3 100644\n--- a/drivers/net/i40e/i40e_flow.c\n+++ b/drivers/net/i40e/i40e_flow.c\n@@ -2243,83 +2243,6 @@ i40e_flow_check_raw_item(const struct rte_flow_item *item,\n \treturn 0;\n }\n \n-static int\n-i40e_flow_set_fdir_inset(struct i40e_pf *pf,\n-\t\t\t enum i40e_filter_pctype pctype,\n-\t\t\t uint64_t input_set)\n-{\n-\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n-\tuint64_t inset_reg = 0;\n-\tuint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};\n-\tint i, num;\n-\n-\t/* Check if the input set is valid */\n-\tif (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,\n-\t\t\t\t input_set) != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"Invalid input set\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Check if the configuration is conflicted */\n-\tif (pf->fdir.inset_flag[pctype] &&\n-\t memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))\n-\t\treturn -1;\n-\n-\tif (pf->fdir.inset_flag[pctype] &&\n-\t !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))\n-\t\treturn 0;\n-\n-\tnum = i40e_generate_inset_mask_reg(input_set, mask_reg,\n-\t\t\t\t\t I40E_INSET_MASK_NUM_REG);\n-\tif (num < 0)\n-\t\treturn -EINVAL;\n-\n-\tif (pf->support_multi_driver) {\n-\t\tfor (i = 0; i < num; i++)\n-\t\t\tif (i40e_read_rx_ctl(hw,\n-\t\t\t\t\tI40E_GLQF_FD_MSK(i, pctype)) !=\n-\t\t\t\t\tmask_reg[i]) {\n-\t\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not\"\n-\t\t\t\t\t\t\" supported with\"\n-\t\t\t\t\t\t\" `support-multi-driver`\"\n-\t\t\t\t\t\t\" enabled!\");\n-\t\t\t\treturn -EPERM;\n-\t\t\t}\n-\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\t\tif (i40e_read_rx_ctl(hw,\n-\t\t\t\t\tI40E_GLQF_FD_MSK(i, pctype)) != 0) {\n-\t\t\t\tPMD_DRV_LOG(ERR, \"Input set setting is not\"\n-\t\t\t\t\t\t\" supported with\"\n-\t\t\t\t\t\t\" `support-multi-driver`\"\n-\t\t\t\t\t\t\" enabled!\");\n-\t\t\t\treturn -EPERM;\n-\t\t\t}\n-\n-\t} else {\n-\t\tfor (i = 0; i < num; i++)\n-\t\t\ti40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),\n-\t\t\t\tmask_reg[i]);\n-\t\t/*clear unused mask registers of the pctype */\n-\t\tfor (i = num; i < I40E_INSET_MASK_NUM_REG; i++)\n-\t\t\ti40e_check_write_reg(hw,\n-\t\t\t\t\tI40E_GLQF_FD_MSK(i, pctype), 0);\n-\t}\n-\n-\tinset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);\n-\n-\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),\n-\t\t\t (uint32_t)(inset_reg & UINT32_MAX));\n-\ti40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n-\t\t\t (uint32_t)((inset_reg >>\n-\t\t\t\t\t I40E_32_BIT_WIDTH) & UINT32_MAX));\n-\n-\tI40E_WRITE_FLUSH(hw);\n-\n-\tpf->fdir.input_set[pctype] = input_set;\n-\tpf->fdir.inset_flag[pctype] = 1;\n-\treturn 0;\n-}\n-\n static uint8_t\n i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,\n \t\t\t\tenum rte_flow_item_type item_type,\n@@ -3212,18 +3135,14 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \n \t/* If customized pctype is not used, set fdir configuration.*/\n \tif (!filter->input.flow_ext.customized_pctype) {\n-\t\tret = i40e_flow_set_fdir_inset(pf, pctype, input_set);\n-\t\tif (ret == -1) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n-\t\t\t\t\t \"Conflict with the first rule's input set.\");\n-\t\t\treturn -rte_errno;\n-\t\t} else if (ret == -EINVAL) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n-\t\t\t\t\t \"Invalid pattern mask.\");\n-\t\t\treturn -rte_errno;\n+\t\t/* Check if the input set is valid */\n+\t\tif (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,\n+\t\t\t\t\t\tinput_set) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid input set\");\n+\t\t\treturn -EINVAL;\n \t\t}\n+\n+\t\tfilter->input.flow_ext.input_set = input_set;\n \t}\n \n \tfilter->input.pctype = pctype;\n", "prefixes": [ "RFC" ] }