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GET /api/patches/88973/?format=api
{ "id": 88973, "url": "http://patches.dpdk.org/api/patches/88973/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1615512441-17495-1-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1615512441-17495-1-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1615512441-17495-1-git-send-email-wenzhuo.lu@intel.com", "date": "2021-03-12T01:27:21", "name": "[3/3] net/i40e: fix segment fault in AVX512", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "83b56942006a2f7fcfdd4ef88ec63bf2ac930ad4", "submitter": { "id": 258, "url": "http://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1615512441-17495-1-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 15621, "url": "http://patches.dpdk.org/api/series/15621/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15621", "date": "2021-03-12T01:26:57", "name": "[1/3] net/iavf: fix segment fault in AVX512", "version": 1, "mbox": "http://patches.dpdk.org/series/15621/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88973/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88973/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 261BBA0564;\n\tFri, 12 Mar 2021 02:27:42 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 12A94160800;\n\tFri, 12 Mar 2021 02:27:42 +0100 (CET)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id CF8CC160819;\n Fri, 12 Mar 2021 02:27:40 +0100 (CET)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Mar 2021 17:27:34 -0800", "from dpdk-wenzhuo-haswell.sh.intel.com ([10.67.111.137])\n by fmsmga007.fm.intel.com with ESMTP; 11 Mar 2021 17:27:32 -0800" ], "IronPort-SDR": [ "\n 74FaD5YN/qr+BDTs2UV/0qmuUuiIJTFUZ2zhWxoRS5Wddz/CI25Joxk5JJ0g3AEcapD0f0RGmv\n zMV+O01F2bVA==", "\n PpNQxQK8FME39N3GYU3U550IFE3nOnTSfa8qXAKgyiND3+26GCOMwbgXOH98GhKIwL46terbly\n LOFyvXNexdeA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9920\"; a=\"176358968\"", "E=Sophos;i=\"5.81,241,1610438400\"; d=\"scan'208\";a=\"176358968\"", "E=Sophos;i=\"5.81,241,1610438400\"; d=\"scan'208\";a=\"377550697\"" ], "X-ExtLoop1": "1", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>,\n\tstable@dpdk.org", "Date": "Fri, 12 Mar 2021 09:27:21 +0800", "Message-Id": "<1615512441-17495-1-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "Subject": "[dpdk-dev] [PATCH 3/3] net/i40e: fix segment fault in AVX512", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Fix segment fault when failing to get the memory from the pool.\n\nFixes: e6a6a138919f (\"net/i40e: add AVX512 vector path\")\nCc: stable@dpdk.org\n\nReported-by: David Coyle <David.Coyle@intel.com>\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/i40e/i40e_rxtx_vec_avx512.c | 128 ++++++++++++++++++++++++++++++++\n 1 file changed, 128 insertions(+)", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx_vec_avx512.c b/drivers/net/i40e/i40e_rxtx_vec_avx512.c\nindex 862c916..36521da 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_avx512.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_avx512.c\n@@ -32,6 +32,9 @@\n \n \trxdp = rxq->rx_ring + rxq->rxrearm_start;\n \n+\tif (!cache)\n+\t\tgoto normal;\n+\n \t/* We need to pull 'n' more MBUFs into the software ring from mempool\n \t * We inline the mempool function here, so we can vectorize the copy\n \t * from the cache into the shadow ring.\n@@ -132,7 +135,132 @@\n #endif\n \t\trxep += 8, rxdp += 8, cache->len -= 8;\n \t}\n+\tgoto done;\n+\n+normal:\n+\t/* Pull 'n' more MBUFs into the software ring */\n+\tif (rte_mempool_get_bulk(rxq->mp,\n+\t\t\t\t (void *)rxep,\n+\t\t\t\t RTE_I40E_RXQ_REARM_THRESH) < 0) {\n+\t\tif (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=\n+\t\t rxq->nb_rx_desc) {\n+\t\t\t__m128i dma_addr0;\n+\n+\t\t\tdma_addr0 = _mm_setzero_si128();\n+\t\t\tfor (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {\n+\t\t\t\trxep[i].mbuf = &rxq->fake_mbuf;\n+\t\t\t\t_mm_store_si128((__m128i *)&rxdp[i].read,\n+\t\t\t\t\t\tdma_addr0);\n+\t\t\t}\n+\t\t}\n+\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n+\t\t\tRTE_I40E_RXQ_REARM_THRESH;\n+\t\treturn;\n+\t}\n+\n+#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n+\tstruct rte_mbuf *mb0, *mb1;\n+\t__m128i dma_addr0, dma_addr1;\n+\t__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,\n+\t\t\tRTE_PKTMBUF_HEADROOM);\n+\t/* Initialize the mbufs in vector, process 4 mbufs in one loop */\n+\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {\n+\t\t__m128i vaddr0, vaddr1;\n+\n+\t\tmb0 = rxep[0].mbuf;\n+\t\tmb1 = rxep[1].mbuf;\n+\n+\t\t/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n+\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n+\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n+\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n+\n+\t\t/* convert pa to dma_addr hdr/data */\n+\t\tdma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);\n+\t\tdma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);\n+\n+\t\t/* add headroom to pa values */\n+\t\tdma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\n+\t\tdma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\n+\n+\t\t/* flush desc with pa dma_addr */\n+\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\n+\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\n+\t}\n+#else\n+\tstruct rte_mbuf *mb0, *mb1, *mb2, *mb3;\n+\tstruct rte_mbuf *mb4, *mb5, *mb6, *mb7;\n+\t__m512i dma_addr0_3, dma_addr4_7;\n+\t__m512i hdr_room = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);\n+\t/* Initialize the mbufs in vector, process 4 mbufs in one loop */\n+\tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH;\n+\t\t\ti += 8, rxep += 8, rxdp += 8) {\n+\t\t__m128i vaddr0, vaddr1, vaddr2, vaddr3;\n+\t\t__m128i vaddr4, vaddr5, vaddr6, vaddr7;\n+\t\t__m256i vaddr0_1, vaddr2_3;\n+\t\t__m256i vaddr4_5, vaddr6_7;\n+\t\t__m512i vaddr0_3, vaddr4_7;\n+\n+\t\tmb0 = rxep[0].mbuf;\n+\t\tmb1 = rxep[1].mbuf;\n+\t\tmb2 = rxep[2].mbuf;\n+\t\tmb3 = rxep[3].mbuf;\n+\t\tmb4 = rxep[4].mbuf;\n+\t\tmb5 = rxep[5].mbuf;\n+\t\tmb6 = rxep[6].mbuf;\n+\t\tmb7 = rxep[7].mbuf;\n+\n+\t\t/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */\n+\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=\n+\t\t\t\toffsetof(struct rte_mbuf, buf_addr) + 8);\n+\t\tvaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);\n+\t\tvaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);\n+\t\tvaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);\n+\t\tvaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);\n+\t\tvaddr4 = _mm_loadu_si128((__m128i *)&mb4->buf_addr);\n+\t\tvaddr5 = _mm_loadu_si128((__m128i *)&mb5->buf_addr);\n+\t\tvaddr6 = _mm_loadu_si128((__m128i *)&mb6->buf_addr);\n+\t\tvaddr7 = _mm_loadu_si128((__m128i *)&mb7->buf_addr);\n+\n+\t\t/**\n+\t\t * merge 0 & 1, by casting 0 to 256-bit and inserting 1\n+\t\t * into the high lanes. Similarly for 2 & 3\n+\t\t */\n+\t\tvaddr0_1 =\n+\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),\n+\t\t\t\t\t\tvaddr1, 1);\n+\t\tvaddr2_3 =\n+\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),\n+\t\t\t\t\t\tvaddr3, 1);\n+\t\tvaddr4_5 =\n+\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr4),\n+\t\t\t\t\t\tvaddr5, 1);\n+\t\tvaddr6_7 =\n+\t\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr6),\n+\t\t\t\t\t\tvaddr7, 1);\n+\t\tvaddr0_3 =\n+\t\t\t_mm512_inserti64x4(_mm512_castsi256_si512(vaddr0_1),\n+\t\t\t\t\t\tvaddr2_3, 1);\n+\t\tvaddr4_7 =\n+\t\t\t_mm512_inserti64x4(_mm512_castsi256_si512(vaddr4_5),\n+\t\t\t\t\t\tvaddr6_7, 1);\n+\n+\t\t/* convert pa to dma_addr hdr/data */\n+\t\tdma_addr0_3 = _mm512_unpackhi_epi64(vaddr0_3, vaddr0_3);\n+\t\tdma_addr4_7 = _mm512_unpackhi_epi64(vaddr4_7, vaddr4_7);\n+\n+\t\t/* add headroom to pa values */\n+\t\tdma_addr0_3 = _mm512_add_epi64(dma_addr0_3, hdr_room);\n+\t\tdma_addr4_7 = _mm512_add_epi64(dma_addr4_7, hdr_room);\n+\n+\t\t/* flush desc with pa dma_addr */\n+\t\t_mm512_store_si512((__m512i *)&rxdp->read, dma_addr0_3);\n+\t\t_mm512_store_si512((__m512i *)&(rxdp + 4)->read, dma_addr4_7);\n+\t}\n+#endif\n \n+done:\n \trxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;\n \tif (rxq->rxrearm_start >= rxq->nb_rx_desc)\n \t\trxq->rxrearm_start = 0;\n", "prefixes": [ "3/3" ] }