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GET /api/patches/8884/?format=api
{ "id": 8884, "url": "http://patches.dpdk.org/api/patches/8884/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1447332938-201120-4-git-send-email-pablo.de.lara.guarch@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1447332938-201120-4-git-send-email-pablo.de.lara.guarch@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1447332938-201120-4-git-send-email-pablo.de.lara.guarch@intel.com", "date": "2015-11-12T12:55:33", "name": "[dpdk-dev,v6,3/8] ixgbe: add additional ieee1588 support functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "28e6f719275619b8b5a7a006f3fbbdb905b1ed5c", "submitter": { "id": 9, "url": "http://patches.dpdk.org/api/people/9/?format=api", "name": "De Lara Guarch, Pablo", "email": "pablo.de.lara.guarch@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1447332938-201120-4-git-send-email-pablo.de.lara.guarch@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/8884/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/8884/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 977B49216;\n\tThu, 12 Nov 2015 13:56:01 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 377CD91CC\n\tfor <dev@dpdk.org>; Thu, 12 Nov 2015 13:55:59 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga102.fm.intel.com with ESMTP; 12 Nov 2015 04:55:58 -0800", "from sie-lab-214-214.ir.intel.com (HELO\n\tsie-lab-214-174.ir.intel.com) ([10.237.214.214])\n\tby fmsmga001.fm.intel.com with ESMTP; 12 Nov 2015 04:55:54 -0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,281,1444719600\"; d=\"scan'208\";a=\"835527500\"", "From": "Pablo de Lara <pablo.de.lara.guarch@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 12 Nov 2015 12:55:33 +0000", "Message-Id": "<1447332938-201120-4-git-send-email-pablo.de.lara.guarch@intel.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1447332938-201120-1-git-send-email-pablo.de.lara.guarch@intel.com>", "References": "<1446732366-10044-1-git-send-email-danielx.t.mrzyglod@intel.com>\n\t<1447332938-201120-1-git-send-email-pablo.de.lara.guarch@intel.com>", "Subject": "[dpdk-dev] [PATCH v6 3/8] ixgbe: add additional ieee1588 support\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>\n\nAdd additional functions to support the existing IEEE1588\nfunctionality and to enable getting, setting and adjusting\nthe device time.\n\nSigned-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>\nSigned-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>\nReviewed-by: John McNamara <john.mcnamara@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.c | 187 ++++++++++++++++++++++++++++++++++++---\n drivers/net/ixgbe/ixgbe_ethdev.h | 2 +\n 2 files changed, 178 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\nindex 0b0bbcf..91a903d 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.c\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.c\n@@ -126,10 +126,17 @@\n #define IXGBE_HKEY_MAX_INDEX 10\n \n /* Additional timesync values. */\n-#define IXGBE_TIMINCA_16NS_SHIFT 24\n-#define IXGBE_TIMINCA_INCVALUE 16000000\n-#define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \\\n-\t\t\t\t | IXGBE_TIMINCA_INCVALUE)\n+#define NSEC_PER_SEC 1000000000L\n+#define IXGBE_INCVAL_10GB 0x66666666\n+#define IXGBE_INCVAL_1GB 0x40000000\n+#define IXGBE_INCVAL_100 0x50000000\n+#define IXGBE_INCVAL_SHIFT_10GB 28\n+#define IXGBE_INCVAL_SHIFT_1GB 24\n+#define IXGBE_INCVAL_SHIFT_100 21\n+#define IXGBE_INCVAL_SHIFT_82599 7\n+#define IXGBE_INCPER_SHIFT_82599 24\n+\n+#define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffff\n \n static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);\n static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);\n@@ -325,6 +332,11 @@ static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t uint32_t flags);\n static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t struct timespec *timestamp);\n+static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);\n+static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,\n+\t\t\t\t struct timespec *timestamp);\n+static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,\n+\t\t\t\t const struct timespec *timestamp);\n \n /*\n * Define VF Stats MACRO for Non \"cleared on read\" register\n@@ -480,6 +492,9 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {\n \t.get_eeprom = ixgbe_get_eeprom,\n \t.set_eeprom = ixgbe_set_eeprom,\n \t.get_dcb_info = ixgbe_dev_get_dcb_info,\n+\t.timesync_adjust_time = ixgbe_timesync_adjust_time,\n+\t.timesync_read_time = ixgbe_timesync_read_time,\n+\t.timesync_write_time = ixgbe_timesync_write_time,\n };\n \n /*\n@@ -5608,20 +5623,147 @@ ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n \t\t\t\t\t ixgbe_dev_addr_list_itr, TRUE);\n }\n \n+static uint64_t\n+ixgbe_read_cyclecounter(void *arg)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *) arg;\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint64_t systime_cycles = 0;\n+\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_X550:\n+\t\t/* SYSTIMEL stores ns and SYSTIMEH stores seconds. */\n+\t\tsystime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);\n+\t\tsystime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)\n+\t\t\t\t* NSEC_PER_SEC;\n+\t\tbreak;\n+\tdefault:\n+\t\tsystime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);\n+\t\tsystime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)\n+\t\t\t\t<< 32;\n+\t}\n+\n+\treturn systime_cycles;\n+}\n+\n+static void\n+ixgbe_start_cyclecounter(struct rte_eth_dev *dev)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\tstruct rte_eth_link link;\n+\tuint32_t incval = 0;\n+\tuint32_t shift = 0;\n+\n+\t/* Get current link speed. */\n+\tmemset(&link, 0, sizeof(link));\n+\tixgbe_dev_link_update(dev, 1);\n+\trte_ixgbe_dev_atomic_read_link_status(dev, &link);\n+\n+\tswitch (link.link_speed) {\n+\tcase ETH_LINK_SPEED_100:\n+\t\tincval = IXGBE_INCVAL_100;\n+\t\tshift = IXGBE_INCVAL_SHIFT_100;\n+\t\tbreak;\n+\tcase ETH_LINK_SPEED_1000:\n+\t\tincval = IXGBE_INCVAL_1GB;\n+\t\tshift = IXGBE_INCVAL_SHIFT_1GB;\n+\t\tbreak;\n+\tcase ETH_LINK_SPEED_10000:\n+\tdefault:\n+\t\tincval = IXGBE_INCVAL_10GB;\n+\t\tshift = IXGBE_INCVAL_SHIFT_10GB;\n+\t\tbreak;\n+\t}\n+\n+\tswitch (hw->mac.type) {\n+\tcase ixgbe_mac_X550:\n+\t\t/* Independent of link speed. */\n+\t\tincval = 1;\n+\t\t/* Cycles read will be interpreted as ns. */\n+\t\tshift = 0;\n+\t\t/* Fall-through */\n+\tcase ixgbe_mac_X540:\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);\n+\t\tbreak;\n+\tcase ixgbe_mac_82599EB:\n+\t\tincval >>= IXGBE_INCVAL_SHIFT_82599;\n+\t\tshift -= IXGBE_INCVAL_SHIFT_82599;\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_TIMINCA,\n+\t\t\t\t(1 << IXGBE_INCPER_SHIFT_82599) | incval);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Not supported. */\n+\t\treturn;\n+\t}\n+\n+\tmemset(&adapter->tc, 0, sizeof(struct rte_timecounter));\n+\tadapter->tc.read = ixgbe_read_cyclecounter;\n+\tadapter->tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;\n+\tadapter->tc.cc_shift = shift;\n+\tadapter->tc.arg = dev;\n+}\n+\n+static int\n+ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)\n+{\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n+\tadapter->tc.nsec += delta;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)\n+{\n+\tuint64_t ns;\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n+\tns = rte_timespec_to_ns(ts);\n+\t/* Reset the timecounter. */\n+\trte_timecounter_init(&adapter->tc, ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tuint64_t ns;\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n+\tns = rte_timecounter_read(&adapter->tc);\n+\t*ts = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n static int\n ixgbe_timesync_enable(struct rte_eth_dev *dev)\n {\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n \tuint32_t tsync_ctl;\n \tuint32_t tsauxc;\n+\tuint64_t ns;\n+\tstruct timespec zerotime = {0, 0};\n \n \t/* Enable system time for platforms where it isn't on by default. */\n \ttsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);\n \ttsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;\n-\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);\n \n-\t/* Start incrementing the register used to timestamp PTP packets. */\n-\tIXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);\n+\t/* Set 0.0 epoch time to initialize timecounter. */\n+\tns = rte_timespec_to_ns(&zerotime);\n+\tixgbe_start_cyclecounter(dev);\n+\trte_timecounter_init(&adapter->tc, ns);\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);\n \n \t/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n \tIXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),\n@@ -5639,6 +5781,8 @@ ixgbe_timesync_enable(struct rte_eth_dev *dev)\n \ttsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;\n \tIXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);\n \n+\tIXGBE_WRITE_FLUSH(hw);\n+\n \treturn 0;\n }\n \n@@ -5673,9 +5817,13 @@ ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t uint32_t flags __rte_unused)\n {\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n \tuint32_t tsync_rxctl;\n \tuint32_t rx_stmpl;\n \tuint32_t rx_stmph;\n+\tuint64_t regival = 0;\n \n \ttsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);\n \tif ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)\n@@ -5683,9 +5831,16 @@ ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \n \trx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);\n \trx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);\n+\trte_timecounter_read(&adapter->tc);\n+\n+\tif (hw->mac.type == ixgbe_mac_X550)\n+\t\tregival = (uint64_t)((uint64_t)rx_stmph * NSEC_PER_SEC\n+\t\t\t+ rx_stmpl);\n+\telse\n+\t\tregival = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n \n-\ttimestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n-\ttimestamp->tv_nsec = 0;\n+\tregival = rte_timecounter_cycles_to_ns_time(&adapter->tc, regival);\n+\t*timestamp = rte_ns_to_timespec(regival);\n \n \treturn 0;\n }\n@@ -5695,9 +5850,13 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t struct timespec *timestamp)\n {\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n \tuint32_t tsync_txctl;\n \tuint32_t tx_stmpl;\n \tuint32_t tx_stmph;\n+\tuint64_t regival = 0;\n \n \ttsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);\n \tif ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)\n@@ -5705,9 +5864,15 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \n \ttx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);\n \ttx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);\n+\trte_timecounter_read(&adapter->tc);\n \n-\ttimestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n-\ttimestamp->tv_nsec = 0;\n+\tif (hw->mac.type == ixgbe_mac_X550)\n+\t\tregival = (uint64_t)((uint64_t)tx_stmph * NSEC_PER_SEC\n+\t\t\t+ tx_stmpl);\n+\telse\n+\t\tregival = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n+\tregival = rte_timecounter_cycles_to_ns_time(&adapter->tc, regival);\n+\t*timestamp = rte_ns_to_timespec(regival);\n \n \treturn 0;\n }\ndiff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h\nindex 1856c42..0e309a2 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.h\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.h\n@@ -37,6 +37,7 @@\n #include \"base/ixgbe_dcb_82599.h\"\n #include \"base/ixgbe_dcb_82598.h\"\n #include \"ixgbe_bypass.h\"\n+#include <rte_time.h>\n \n /* need update link, bit flag */\n #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)\n@@ -282,6 +283,7 @@ struct ixgbe_adapter {\n \n \tbool rx_bulk_alloc_allowed;\n \tbool rx_vec_allowed;\n+\tstruct rte_timecounter tc;\n };\n \n #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\\\n", "prefixes": [ "dpdk-dev", "v6", "3/8" ] }