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GET /api/patches/88674/?format=api
{ "id": 88674, "url": "http://patches.dpdk.org/api/patches/88674/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-35-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306162942.6845-35-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306162942.6845-35-pbhagavatula@marvell.com", "date": "2021-03-06T16:29:39", "name": "[34/36] event/cnxk: add Rx adapter fastpath ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ca0fb4bf94dca02972f50a8c573c9681aca512a9", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-35-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 15516, "url": "http://patches.dpdk.org/api/series/15516/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15516", "date": "2021-03-06T16:29:05", "name": "Marvell CNXK Event device Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15516/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88674/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/88674/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C5E6DA0548;\n\tSat, 6 Mar 2021 17:35:48 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E992622A51C;\n\tSat, 6 Mar 2021 17:32:01 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 2FB6F22A3F0\n for <dev@dpdk.org>; Sat, 6 Mar 2021 17:32:00 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126GQjLS009184 for <dev@dpdk.org>; Sat, 6 Mar 2021 08:31:59 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 374a4w08rp-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 08:31:59 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:31:56 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 08:31:56 -0800", "from BG-LT7430.marvell.com (unknown [10.193.68.121])\n by maili.marvell.com (Postfix) with ESMTP id 230833F7043;\n Sat, 6 Mar 2021 08:31:54 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=n39rSj0YBWggqMajkyOby3xRho4CilZtmgD4yTxEhnk=;\n b=WVjPCQezNiF9bPzLRTHI3qBjJvxYCUXFcM4Vrkl+bgNUn4ZRiNTCt2NNJZ5MRJpDdSx/\n lEBaudYFu82+0UhHjk/1kHXwo1hOA1rpnTzknd5qyIKUkfZfi3qiTD9c6ojMq1aPK++i\n ph3tXGxVrCiYjrIqYXVG/3TrW7RRnUomHXKfnEL+9C+XOsBUKabNkBh6QtxdarC7yNXY\n 5JFsRB+c0t2pOvchCmwc6+kSCSQ7oz8zV/oDhQSH6jBuCngyN4a9osHw3/v98NKWqANA\n Bgg2+vW89QDVbMVHJjcEmMKASI5RA+Bcn6thNipvB9v/35JODudMXT/Gj/NjT0Lz1zmU FA==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<ndabilpuram@marvell.com>, <dev@dpdk.org>", "Date": "Sat, 6 Mar 2021 21:59:39 +0530", "Message-ID": "<20210306162942.6845-35-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 34/36] event/cnxk: add Rx adapter fastpath ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd support for event eth Rx adapter fastpath operations.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 115 ++++++++-\n drivers/event/cnxk/cn10k_worker.c | 164 +++++++++----\n drivers/event/cnxk/cn10k_worker.h | 91 +++++--\n drivers/event/cnxk/cn9k_eventdev.c | 254 ++++++++++++++++++-\n drivers/event/cnxk/cn9k_worker.c | 364 +++++++++++++++++++---------\n drivers/event/cnxk/cn9k_worker.h | 158 +++++++++---\n drivers/event/cnxk/meson.build | 8 +\n 7 files changed, 932 insertions(+), 222 deletions(-)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 72175e16f..70c6fedae 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -247,17 +247,120 @@ static void\n cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tconst event_dequeue_t sso_hws_deq[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_tmo_deq[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_tmo_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_tmo_deq_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_tmo_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_deq_seg[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_tmo_deq_seg[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_tmo_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_tmo_deq_seg_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn10k_sso_hws_tmo_deq_seg_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n \n \tevent_dev->enqueue = cn10k_sso_hws_enq;\n \tevent_dev->enqueue_burst = cn10k_sso_hws_enq_burst;\n \tevent_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;\n \tevent_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;\n-\n-\tevent_dev->dequeue = cn10k_sso_hws_deq;\n-\tevent_dev->dequeue_burst = cn10k_sso_hws_deq_burst;\n-\tif (dev->is_timeout_deq) {\n-\t\tevent_dev->dequeue = cn10k_sso_hws_tmo_deq;\n-\t\tevent_dev->dequeue_burst = cn10k_sso_hws_tmo_deq_burst;\n+\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n+\t\tevent_dev->dequeue = sso_hws_deq_seg\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_seg_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_tmo_deq_seg\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_tmo_deq_seg_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n+\t} else {\n+\t\tevent_dev->dequeue = sso_hws_deq\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_tmo_deq\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_tmo_deq_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n \t}\n }\n \ndiff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c\nindex 57b0714bb..46f72cf20 100644\n--- a/drivers/event/cnxk/cn10k_worker.c\n+++ b/drivers/event/cnxk/cn10k_worker.c\n@@ -60,56 +60,118 @@ cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \treturn 1;\n }\n \n-uint16_t __rte_hot\n-cn10k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn10k_sso_hws *ws = port;\n-\n-\tRTE_SET_USED(timeout_ticks);\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->tag_wqe_op);\n-\t\treturn 1;\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+ \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_wqe_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+ \\\n+\t\treturn cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn10k_sso_hws_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_wqe_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+ \\\n+\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+ \\\n+\t\treturn ret; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn10k_sso_hws_tmo_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+ \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_wqe_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+ \\\n+\t\treturn cn10k_sso_hws_get_work( \\\n+\t\t\tws, ev, flags | NIX_RX_MULTI_SEG_F, ws->lookup_mem); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn10k_sso_hws_deq_seg_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn10k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_wqe_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+ \\\n+\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn10k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+ \\\n+\t\treturn ret; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn10k_sso_hws_tmo_deq_seg_##name(port, ev, \\\n+\t\t\t\t\t\t\ttimeout_ticks); \\\n \t}\n \n-\treturn cn10k_sso_hws_get_work(ws, ev);\n-}\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_deq_burst(void *port, struct rte_event ev[], uint16_t nb_events,\n-\t\t\tuint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn10k_sso_hws_deq(port, ev, timeout_ticks);\n-}\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_tmo_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn10k_sso_hws *ws = port;\n-\tuint16_t ret = 1;\n-\tuint64_t iter;\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->tag_wqe_op);\n-\t\treturn ret;\n-\t}\n-\n-\tret = cn10k_sso_hws_get_work(ws, ev);\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++)\n-\t\tret = cn10k_sso_hws_get_work(ws, ev);\n-\n-\treturn ret;\n-}\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t uint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn10k_sso_hws_tmo_deq(port, ev, timeout_ticks);\n-}\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex d418e80aa..9521a5c94 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -83,20 +83,40 @@ cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,\n \t\tcn10k_sso_hws_fwd_group(ws, ev, grp);\n }\n \n+static __rte_always_inline void\n+cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n+\t\t const uint32_t tag, const uint32_t flags,\n+\t\t const void *const lookup_mem)\n+{\n+\tunion mbuf_initializer mbuf_init = {\n+\t\t.fields = {.data_off = RTE_PKTMBUF_HEADROOM,\n+\t\t\t .refcnt = 1,\n+\t\t\t .nb_segs = 1,\n+\t\t\t .port = port_id},\n+\t};\n+\n+\tcn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,\n+\t\t\t (struct rte_mbuf *)mbuf, lookup_mem,\n+\t\t\t mbuf_init.value, flags);\n+}\n+\n static __rte_always_inline uint16_t\n-cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev)\n+cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,\n+\t\t const uint32_t flags, void *lookup_mem)\n {\n \tunion {\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t mbuf;\n \n \tgw.get_work = ws->gw_wdata;\n #if defined(RTE_ARCH_ARM64) && !defined(__clang__)\n \tasm volatile(\n \t\tPLT_CPU_FEATURE_PREAMBLE\n \t\t\"caspl %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\\n\"\n-\t\t: [wdata] \"+r\"(gw.get_work)\n+\t\t\"sub %[mbuf], %H[wdata], #0x80\t\t\t\t\\n\"\n+\t\t: [wdata] \"+r\"(gw.get_work), [mbuf] \"=&r\"(mbuf)\n \t\t: [gw_loc] \"r\"(ws->getwrk_op)\n \t\t: \"memory\");\n #else\n@@ -104,11 +124,25 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \tdo {\n \t\troc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op);\n \t} while (gw.u64[0] & BIT_ULL(63));\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n+\t\t\t\t\t lookup_mem);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -123,6 +157,7 @@ cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t mbuf;\n \n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n@@ -133,19 +168,34 @@ cn10k_sso_hws_get_work_empty(struct cn10k_sso_hws *ws, struct rte_event *ev)\n \t\t \"\t\tldp %[tag], %[wqp], [%[tag_loc]]\t\\n\"\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\t\\n\"\n \t\t \"done%=:\tdmb ld\t\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->tag_wqe_op)\n \t\t : \"memory\");\n #else\n \tdo {\n \t\troc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op);\n \t} while (gw.u64[0] & BIT_ULL(63));\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn10k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, 0, NULL);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -164,16 +214,29 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,\n \t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t uint16_t nb_events);\n \n-uint16_t __rte_hot cn10k_sso_hws_deq(void *port, struct rte_event *ev,\n-\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn10k_sso_hws_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn10k_sso_hws_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn10k_sso_hws_tmo_deq_burst(void *port,\n-\t\t\t\t\t struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn10k_sso_hws_tmo_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks);\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n \n #endif\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 4aa577bd5..e4383dca1 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -252,17 +252,179 @@ static void\n cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\t/* Single WS modes */\n+\tconst event_dequeue_t sso_hws_deq[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_tmo_deq[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_tmo_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_tmo_deq_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_tmo_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_deq_seg[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_tmo_deq_seg[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_tmo_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_tmo_deq_seg_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_tmo_deq_seg_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\t/* Dual WS modes */\n+\tconst event_dequeue_t sso_hws_dual_deq[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_dual_deq_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_dual_tmo_deq[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_tmo_deq_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_dual_tmo_deq_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_tmo_deq_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_dual_deq_seg_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_dual_tmo_deq_seg[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_tmo_deq_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_dual_tmo_deq_seg_burst[2][2][2][2] =\n+\t\t{\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\t[f3][f2][f1][f0] = cn9k_sso_hws_dual_tmo_deq_seg_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t\t};\n \n \tevent_dev->enqueue = cn9k_sso_hws_enq;\n \tevent_dev->enqueue_burst = cn9k_sso_hws_enq_burst;\n \tevent_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;\n \tevent_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;\n-\n-\tevent_dev->dequeue = cn9k_sso_hws_deq;\n-\tevent_dev->dequeue_burst = cn9k_sso_hws_deq_burst;\n-\tif (dev->deq_tmo_ns) {\n-\t\tevent_dev->dequeue = cn9k_sso_hws_tmo_deq;\n-\t\tevent_dev->dequeue_burst = cn9k_sso_hws_tmo_deq_burst;\n+\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n+\t\tevent_dev->dequeue = sso_hws_deq_seg\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_seg_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_tmo_deq_seg\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_tmo_deq_seg_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n+\t} else {\n+\t\tevent_dev->dequeue = sso_hws_deq\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tevent_dev->dequeue_burst = sso_hws_deq_burst\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue = sso_hws_tmo_deq\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_tmo_deq_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t}\n \t}\n \n \tif (dev->dual_ws) {\n@@ -272,14 +434,82 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\tevent_dev->enqueue_forward_burst =\n \t\t\tcn9k_sso_hws_dual_enq_fwd_burst;\n \n-\t\tevent_dev->dequeue = cn9k_sso_hws_dual_deq;\n-\t\tevent_dev->dequeue_burst = cn9k_sso_hws_dual_deq_burst;\n-\t\tif (dev->deq_tmo_ns) {\n-\t\t\tevent_dev->dequeue = cn9k_sso_hws_dual_tmo_deq;\n-\t\t\tevent_dev->dequeue_burst =\n-\t\t\t\tcn9k_sso_hws_dual_tmo_deq_burst;\n+\t\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n+\t\t\tevent_dev->dequeue = sso_hws_dual_deq_seg\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_dual_deq_seg_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tif (dev->is_timeout_deq) {\n+\t\t\t\tevent_dev->dequeue = sso_hws_dual_tmo_deq_seg\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t\tevent_dev->dequeue_burst =\n+\t\t\t\t\tsso_hws_dual_tmo_deq_seg_burst\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t}\n+\t\t} else {\n+\t\t\tevent_dev->dequeue = sso_hws_dual_deq\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tevent_dev->dequeue_burst = sso_hws_dual_deq_burst\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\tif (dev->is_timeout_deq) {\n+\t\t\t\tevent_dev->dequeue = sso_hws_dual_tmo_deq\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t\tevent_dev->dequeue_burst =\n+\t\t\t\t\tsso_hws_dual_tmo_deq_burst\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t\t\t\t\t[!!(dev->rx_offloads &\n+\t\t\t\t\t\t NIX_RX_OFFLOAD_RSS_F)];\n+\t\t\t}\n \t\t}\n \t}\n+\n+\trte_mb();\n }\n \n static void *\ndiff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c\nindex 41ffd88a0..fb572c7c9 100644\n--- a/drivers/event/cnxk/cn9k_worker.c\n+++ b/drivers/event/cnxk/cn9k_worker.c\n@@ -60,59 +60,121 @@ cn9k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \treturn 1;\n }\n \n-uint16_t __rte_hot\n-cn9k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws *ws = port;\n-\n-\tRTE_SET_USED(timeout_ticks);\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->tag_op);\n-\t\treturn 1;\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+ \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+ \\\n+\t\treturn cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+ \\\n+\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+ \\\n+\t\treturn ret; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_tmo_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+ \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+ \\\n+\t\treturn cn9k_sso_hws_get_work( \\\n+\t\t\tws, ev, flags | NIX_RX_MULTI_SEG_F, ws->lookup_mem); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_deq_seg_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+ \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+ \\\n+\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, ws->lookup_mem); \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) \\\n+\t\t\tret = cn9k_sso_hws_get_work(ws, ev, flags, \\\n+\t\t\t\t\t\t ws->lookup_mem); \\\n+ \\\n+\t\treturn ret; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_tmo_deq_seg_##name(port, ev, \\\n+\t\t\t\t\t\t timeout_ticks); \\\n \t}\n \n-\treturn cn9k_sso_hws_get_work(ws, ev);\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_deq_burst(void *port, struct rte_event ev[], uint16_t nb_events,\n-\t\t uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_deq(port, ev, timeout_ticks);\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_tmo_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws *ws = port;\n-\tuint16_t ret = 1;\n-\tuint64_t iter;\n-\n-\tif (ws->swtag_req) {\n-\t\tws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(ws->tag_op);\n-\t\treturn ret;\n-\t}\n-\n-\tret = cn9k_sso_hws_get_work(ws, ev);\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++)\n-\t\tret = cn9k_sso_hws_get_work(ws, ev);\n-\n-\treturn ret;\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t uint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_tmo_deq(port, ev, timeout_ticks);\n-}\n+NIX_RX_FASTPATH_MODES\n+#undef R\n \n /* Dual ws ops. */\n \n@@ -172,65 +234,145 @@ cn9k_sso_hws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],\n \treturn 1;\n }\n \n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws_dual *dws = port;\n-\tuint16_t gw;\n-\n-\tRTE_SET_USED(timeout_ticks);\n-\tif (dws->swtag_req) {\n-\t\tdws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(dws->ws_state[!dws->vws].tag_op);\n-\t\treturn 1;\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t gw; \\\n+ \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+ \\\n+\t\tgw = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], \\\n+\t\t\t\t\t\t&dws->ws_state[!dws->vws], ev, \\\n+\t\t\t\t\t\tflags, dws->lookup_mem); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\treturn gw; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_dual_deq_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+ \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+ \\\n+\t\tret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], \\\n+\t\t\t\t\t\t &dws->ws_state[!dws->vws], \\\n+\t\t\t\t\t\t ev, flags, dws->lookup_mem); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \\\n+\t\t\tret = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t\t&dws->ws_state[dws->vws], \\\n+\t\t\t\t&dws->ws_state[!dws->vws], ev, flags, \\\n+\t\t\t\tdws->lookup_mem); \\\n+\t\t\tdws->vws = !dws->vws; \\\n+\t\t} \\\n+ \\\n+\t\treturn ret; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_dual_tmo_deq_##name(port, ev, \\\n+\t\t\t\t\t\t\ttimeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t gw; \\\n+ \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+ \\\n+\t\tgw = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], \\\n+\t\t\t\t\t\t&dws->ws_state[!dws->vws], ev, \\\n+\t\t\t\t\t\tflags, dws->lookup_mem); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\treturn gw; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_dual_deq_seg_##name(port, ev, \\\n+\t\t\t\t\t\t\ttimeout_ticks); \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t ret = 1; \\\n+\t\tuint64_t iter; \\\n+ \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn ret; \\\n+\t\t} \\\n+ \\\n+\t\tret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], \\\n+\t\t\t\t\t\t &dws->ws_state[!dws->vws], \\\n+\t\t\t\t\t\t ev, flags, dws->lookup_mem); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \\\n+\t\t\tret = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t\t&dws->ws_state[dws->vws], \\\n+\t\t\t\t&dws->ws_state[!dws->vws], ev, flags, \\\n+\t\t\t\tdws->lookup_mem); \\\n+\t\t\tdws->vws = !dws->vws; \\\n+\t\t} \\\n+ \\\n+\t\treturn ret; \\\n+\t} \\\n+ \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+ \\\n+\t\treturn cn9k_sso_hws_dual_tmo_deq_seg_##name(port, ev, \\\n+\t\t\t\t\t\t\t timeout_ticks); \\\n \t}\n \n-\tgw = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws],\n-\t\t\t\t\t&dws->ws_state[!dws->vws], ev);\n-\tdws->vws = !dws->vws;\n-\treturn gw;\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t uint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_dual_deq(port, ev, timeout_ticks);\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t uint64_t timeout_ticks)\n-{\n-\tstruct cn9k_sso_hws_dual *dws = port;\n-\tuint16_t ret = 1;\n-\tuint64_t iter;\n-\n-\tif (dws->swtag_req) {\n-\t\tdws->swtag_req = 0;\n-\t\tcnxk_sso_hws_swtag_wait(dws->ws_state[!dws->vws].tag_op);\n-\t\treturn ret;\n-\t}\n-\n-\tret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws],\n-\t\t\t\t\t &dws->ws_state[!dws->vws], ev);\n-\tdws->vws = !dws->vws;\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++) {\n-\t\tret = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws],\n-\t\t\t\t\t\t &dws->ws_state[!dws->vws], ev);\n-\t\tdws->vws = !dws->vws;\n-\t}\n-\n-\treturn ret;\n-}\n-\n-uint16_t __rte_hot\n-cn9k_sso_hws_dual_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\tuint16_t nb_events, uint64_t timeout_ticks)\n-{\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn9k_sso_hws_dual_tmo_deq(port, ev, timeout_ticks);\n-}\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex b5af5ecf4..bbdca3c95 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -128,17 +128,38 @@ cn9k_sso_hws_dual_forward_event(struct cn9k_sso_hws_dual *dws,\n \t}\n }\n \n+static __rte_always_inline void\n+cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,\n+\t\t const uint32_t tag, const uint32_t flags,\n+\t\t const void *const lookup_mem)\n+{\n+\tunion mbuf_initializer mbuf_init = {\n+\t\t.fields = {.data_off = RTE_PKTMBUF_HEADROOM,\n+\t\t\t .refcnt = 1,\n+\t\t\t .nb_segs = 1,\n+\t\t\t .port = port_id},\n+\t};\n+\n+\tcn9k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,\n+\t\t\t (struct rte_mbuf *)mbuf, lookup_mem,\n+\t\t\t mbuf_init.value, flags);\n+}\n+\n static __rte_always_inline uint16_t\n cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n \t\t\t struct cn9k_sso_hws_state *ws_pair,\n-\t\t\t struct rte_event *ev)\n+\t\t\t struct rte_event *ev, const uint32_t flags,\n+\t\t\t const void *const lookup_mem)\n {\n \tconst uint64_t set_gw = BIT_ULL(16) | 1;\n \tunion {\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t mbuf;\n \n+\tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n+\t\trte_prefetch_non_temporal(lookup_mem);\n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n \t\t \"rty%=:\t\t\t\t\t\\n\"\n@@ -147,7 +168,10 @@ cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n \t\t \"done%=:\tstr %[gw], [%[pong]]\t\t\\n\"\n \t\t \"\t\tdmb ld\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n+\t\t \"\t\tprfm pldl1keep, [%[mbuf]]\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op),\n \t\t [gw] \"r\"(set_gw), [pong] \"r\"(ws_pair->getwrk_op));\n #else\n@@ -156,12 +180,26 @@ cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n \t\tgw.u64[0] = plt_read64(ws->tag_op);\n \tgw.u64[1] = plt_read64(ws->wqp_op);\n \tplt_write64(set_gw, ws_pair->getwrk_op);\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n+\t\t\t\t\t lookup_mem);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -169,16 +207,21 @@ cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n }\n \n static __rte_always_inline uint16_t\n-cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev)\n+cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,\n+\t\t const uint32_t flags, const void *const lookup_mem)\n {\n \tunion {\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t mbuf;\n \n \tplt_write64(BIT_ULL(16) | /* wait for work. */\n \t\t\t 1,\t /* Use Mask set 0. */\n \t\t ws->getwrk_op);\n+\n+\tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n+\t\trte_prefetch_non_temporal(lookup_mem);\n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n \t\t \"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n@@ -190,7 +233,10 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev)\n \t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n \t\t \"done%=:\tdmb ld\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n+\t\t \"\t\tprfm pldl1keep, [%[mbuf]]\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op));\n #else\n \tgw.u64[0] = plt_read64(ws->tag_op);\n@@ -198,12 +244,26 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev)\n \t\tgw.u64[0] = plt_read64(ws->tag_op);\n \n \tgw.u64[1] = plt_read64(ws->wqp_op);\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, flags,\n+\t\t\t\t\t lookup_mem);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -218,6 +278,7 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n \t\t__uint128_t get_work;\n \t\tuint64_t u64[2];\n \t} gw;\n+\tuint64_t mbuf;\n \n #ifdef RTE_ARCH_ARM64\n \tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n@@ -230,7 +291,9 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n \t\t \"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n \t\t \"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n \t\t \"done%=:\tdmb ld\t\t\t\t\\n\"\n-\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1])\n+\t\t \"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n+\t\t : [tag] \"=&r\"(gw.u64[0]), [wqp] \"=&r\"(gw.u64[1]),\n+\t\t [mbuf] \"=&r\"(mbuf)\n \t\t : [tag_loc] \"r\"(ws->tag_op), [wqp_loc] \"r\"(ws->wqp_op));\n #else\n \tgw.u64[0] = plt_read64(ws->tag_op);\n@@ -238,12 +301,25 @@ cn9k_sso_hws_get_work_empty(struct cn9k_sso_hws_state *ws, struct rte_event *ev)\n \t\tgw.u64[0] = plt_read64(ws->tag_op);\n \n \tgw.u64[1] = plt_read64(ws->wqp_op);\n+\tmbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf));\n #endif\n \n \tgw.u64[0] = (gw.u64[0] & (0x3ull << 32)) << 6 |\n \t\t (gw.u64[0] & (0x3FFull << 36)) << 4 |\n \t\t (gw.u64[0] & 0xffffffff);\n \n+\tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n+\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n+\n+\t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n+\t\t\tcn9k_wqe_to_mbuf(gw.u64[1], mbuf, port,\n+\t\t\t\t\t gw.u64[0] & 0xFFFFF, 0, NULL);\n+\t\t\tgw.u64[1] = mbuf;\n+\t\t}\n+\t}\n+\n \tev->event = gw.u64[0];\n \tev->u64 = gw.u64[1];\n \n@@ -274,28 +350,54 @@ uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,\n \t\t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t\t uint16_t nb_events);\n \n-uint16_t __rte_hot cn9k_sso_hws_deq(void *port, struct rte_event *ev,\n-\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\tuint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_tmo_deq_burst(void *port, struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-\n-uint16_t __rte_hot cn9k_sso_hws_dual_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst(void *port,\n-\t\t\t\t\t struct rte_event ev[],\n-\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq(void *port, struct rte_event *ev,\n-\t\t\t\t\t uint64_t timeout_ticks);\n-uint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_burst(void *port,\n-\t\t\t\t\t\t struct rte_event ev[],\n-\t\t\t\t\t\t uint16_t nb_events,\n-\t\t\t\t\t\t uint64_t timeout_ticks);\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_tmo_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks);\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n+\n+#define R(name, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_tmo_deq_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks);\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n \n #endif\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex b40e39397..533ad853a 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -8,6 +8,14 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n \tsubdir_done()\n endif\n \n+extra_flags = ['-Wno-strict-aliasing']\n+foreach flag: extra_flags\n+\tif cc.has_argument(flag)\n+\t\tcflags += flag\n+\tendif\n+endforeach\n+\n+\n sources = files('cn10k_worker.c',\n \t\t'cn10k_eventdev.c',\n \t\t'cn9k_worker.c',\n", "prefixes": [ "34/36" ] }