Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/88658/?format=api
{ "id": 88658, "url": "http://patches.dpdk.org/api/patches/88658/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-17-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306162942.6845-17-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306162942.6845-17-pbhagavatula@marvell.com", "date": "2021-03-06T16:29:21", "name": "[16/36] event/cnxk: add device start function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8f3c6cac4267a613bd4b1bb1fa96ef14f001b6c1", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-17-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 15516, "url": "http://patches.dpdk.org/api/series/15516/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15516", "date": "2021-03-06T16:29:05", "name": "Marvell CNXK Event device Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15516/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88658/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88658/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4B449A0548;\n\tSat, 6 Mar 2021 17:32:57 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 888BD22A4C0;\n\tSat, 6 Mar 2021 17:31:08 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 23AF522A4B0\n for <dev@dpdk.org>; Sat, 6 Mar 2021 17:31:06 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126GPn0I026043 for <dev@dpdk.org>; Sat, 6 Mar 2021 08:31:06 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3747yurewu-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 08:31:06 -0800", "from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:31:04 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:31:04 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 08:31:03 -0800", "from BG-LT7430.marvell.com (unknown [10.193.68.121])\n by maili.marvell.com (Postfix) with ESMTP id 217E73F7048;\n Sat, 6 Mar 2021 08:31:01 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=5sFtVM18PaE9W8xyu7hpVgEisY/CPMk+DyvCJBZHPok=;\n b=ES/uj1oZoF9iQLI9O+aRdi0dh/NJEV4x7m22hHqKCL0ntN3R3a3zYRU/FMDFvWUISEi2\n 5PKmNe64XbRV/2oYCi4w1VvPp2PX33qh/egOzSS+REZNArjhq2Jt5tq4dlPuXThUSbhL\n OJ4gmffAUTsNUe3lHxAKiZq5Wuj7qeWI4zYKbGiq367yJxuFr6c/UT0W0ZS3m3uOmdZo\n s8RvWjluDHN8VNmyY7Zglwki4/vGI21Izz4zD5p1VwfjUsjIxfZhAMlIu0zKCXYlD3S1\n ihtB5ZWIy07RrZIKhMkWFi0kaqWq0sqv7G0h3IK7IbsMpqHYbBZrEszPKYfxk6yBVdSi gw==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<ndabilpuram@marvell.com>, <dev@dpdk.org>", "Date": "Sat, 6 Mar 2021 21:59:21 +0530", "Message-ID": "<20210306162942.6845-17-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 16/36] event/cnxk: add device start function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nAdd eventdev start function along with few cleanup API's to maintain\nsanity.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 127 ++++++++++++++++++++++++++++\n drivers/event/cnxk/cn9k_eventdev.c | 113 +++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.c | 64 ++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h | 7 ++\n 4 files changed, 311 insertions(+)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex a9948e1b2..0de44ed43 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -112,6 +112,117 @@ cn10k_sso_hws_release(void *arg, void *hws)\n \tmemset(ws, 0, sizeof(*ws));\n }\n \n+static void\n+cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,\n+\t\t\t cnxk_handle_event_t fn, void *arg)\n+{\n+\tstruct cn10k_sso_hws *ws = hws;\n+\tuint64_t cq_ds_cnt = 1;\n+\tuint64_t aq_cnt = 1;\n+\tuint64_t ds_cnt = 1;\n+\tstruct rte_event ev;\n+\tuint64_t val, req;\n+\n+\tplt_write64(0, base + SSO_LF_GGRP_QCTL);\n+\n+\treq = queue_id;\t /* GGRP ID */\n+\treq |= BIT_ULL(18); /* Grouped */\n+\treq |= BIT_ULL(16); /* WAIT */\n+\n+\taq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);\n+\tds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);\n+\tcq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);\n+\tcq_ds_cnt &= 0x3FFF3FFF0000;\n+\n+\twhile (aq_cnt || cq_ds_cnt || ds_cnt) {\n+\t\tplt_write64(req, ws->getwrk_op);\n+\t\tcn10k_sso_hws_get_work_empty(ws, &ev);\n+\t\tif (fn != NULL && ev.u64 != 0)\n+\t\t\tfn(arg, ev);\n+\t\tif (ev.sched_type != SSO_TT_EMPTY)\n+\t\t\tcnxk_sso_hws_swtag_flush(ws->tag_wqe_op,\n+\t\t\t\t\t\t ws->swtag_flush_op);\n+\t\tdo {\n+\t\t\tval = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);\n+\t\t} while (val & BIT_ULL(56));\n+\t\taq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);\n+\t\tds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);\n+\t\tcq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);\n+\t\t/* Extract cq and ds count */\n+\t\tcq_ds_cnt &= 0x3FFF3FFF0000;\n+\t}\n+\n+\tplt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);\n+\trte_mb();\n+}\n+\n+static void\n+cn10k_sso_hws_reset(void *arg, void *hws)\n+{\n+\tstruct cnxk_sso_evdev *dev = arg;\n+\tstruct cn10k_sso_hws *ws = hws;\n+\tuintptr_t base = ws->base;\n+\tuint64_t pend_state;\n+\tunion {\n+\t\t__uint128_t wdata;\n+\t\tuint64_t u64[2];\n+\t} gw;\n+\tuint8_t pend_tt;\n+\n+\t/* Wait till getwork/swtp/waitw/desched completes. */\n+\tdo {\n+\t\tpend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);\n+\t} while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |\n+\t\t\t BIT_ULL(56) | BIT_ULL(54)));\n+\tpend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));\n+\tif (pend_tt != SSO_TT_EMPTY) { /* Work was pending */\n+\t\tif (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)\n+\t\t\tcnxk_sso_hws_swtag_untag(base +\n+\t\t\t\t\t\t SSOW_LF_GWS_OP_SWTAG_UNTAG);\n+\t\tplt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);\n+\t}\n+\n+\t/* Wait for desched to complete. */\n+\tdo {\n+\t\tpend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);\n+\t} while (pend_state & BIT_ULL(58));\n+\n+\tswitch (dev->gw_mode) {\n+\tcase CN10K_GW_MODE_PREF:\n+\t\twhile (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))\n+\t\t\t;\n+\t\tbreak;\n+\tcase CN10K_GW_MODE_PREF_WFE:\n+\t\twhile (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &\n+\t\t SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)\n+\t\t\tcontinue;\n+\t\tplt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);\n+\t\tbreak;\n+\tcase CN10K_GW_MODE_NONE:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=\n+\t SSO_TT_EMPTY) {\n+\t\tplt_write64(BIT_ULL(16) | 1, ws->getwrk_op);\n+\t\tdo {\n+\t\t\troc_load_pair(gw.u64[0], gw.u64[1], ws->tag_wqe_op);\n+\t\t} while (gw.u64[0] & BIT_ULL(63));\n+\t\tpend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));\n+\t\tif (pend_tt != SSO_TT_EMPTY) { /* Work was pending */\n+\t\t\tif (pend_tt == SSO_TT_ATOMIC ||\n+\t\t\t pend_tt == SSO_TT_ORDERED)\n+\t\t\t\tcnxk_sso_hws_swtag_untag(\n+\t\t\t\t\tbase + SSOW_LF_GWS_OP_SWTAG_UNTAG);\n+\t\t\tplt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);\n+\t\t}\n+\t}\n+\n+\tplt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);\n+\trte_mb();\n+}\n+\n static void\n cn10k_sso_set_rsrc(void *arg)\n {\n@@ -263,6 +374,20 @@ cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n \treturn (int)nb_unlinks;\n }\n \n+static int\n+cn10k_sso_start(struct rte_eventdev *event_dev)\n+{\n+\tint rc;\n+\n+\trc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,\n+\t\t\t cn10k_sso_hws_flush_events);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\tcn10k_sso_fp_fns_set(event_dev);\n+\n+\treturn rc;\n+}\n+\n static struct rte_eventdev_ops cn10k_sso_dev_ops = {\n \t.dev_infos_get = cn10k_sso_info_get,\n \t.dev_configure = cn10k_sso_dev_configure,\n@@ -275,6 +400,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = {\n \t.port_link = cn10k_sso_port_link,\n \t.port_unlink = cn10k_sso_port_unlink,\n \t.timeout_ticks = cnxk_sso_timeout_ticks,\n+\n+\t.dev_start = cn10k_sso_start,\n };\n \n static int\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 8100140fc..39f29b687 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -126,6 +126,102 @@ cn9k_sso_hws_release(void *arg, void *hws)\n \t}\n }\n \n+static void\n+cn9k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,\n+\t\t\t cnxk_handle_event_t fn, void *arg)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);\n+\tstruct cn9k_sso_hws_dual *dws;\n+\tstruct cn9k_sso_hws_state *st;\n+\tstruct cn9k_sso_hws *ws;\n+\tuint64_t cq_ds_cnt = 1;\n+\tuint64_t aq_cnt = 1;\n+\tuint64_t ds_cnt = 1;\n+\tstruct rte_event ev;\n+\tuintptr_t ws_base;\n+\tuint64_t val, req;\n+\n+\tplt_write64(0, base + SSO_LF_GGRP_QCTL);\n+\n+\treq = queue_id;\t /* GGRP ID */\n+\treq |= BIT_ULL(18); /* Grouped */\n+\treq |= BIT_ULL(16); /* WAIT */\n+\n+\taq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);\n+\tds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);\n+\tcq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);\n+\tcq_ds_cnt &= 0x3FFF3FFF0000;\n+\n+\tif (dev->dual_ws) {\n+\t\tdws = hws;\n+\t\tst = &dws->ws_state[0];\n+\t\tws_base = dws->base[0];\n+\t} else {\n+\t\tws = hws;\n+\t\tst = (struct cn9k_sso_hws_state *)ws;\n+\t\tws_base = ws->base;\n+\t}\n+\n+\twhile (aq_cnt || cq_ds_cnt || ds_cnt) {\n+\t\tplt_write64(req, st->getwrk_op);\n+\t\tcn9k_sso_hws_get_work_empty(st, &ev);\n+\t\tif (fn != NULL && ev.u64 != 0)\n+\t\t\tfn(arg, ev);\n+\t\tif (ev.sched_type != SSO_TT_EMPTY)\n+\t\t\tcnxk_sso_hws_swtag_flush(st->tag_op,\n+\t\t\t\t\t\t st->swtag_flush_op);\n+\t\tdo {\n+\t\t\tval = plt_read64(ws_base + SSOW_LF_GWS_PENDSTATE);\n+\t\t} while (val & BIT_ULL(56));\n+\t\taq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);\n+\t\tds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);\n+\t\tcq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);\n+\t\t/* Extract cq and ds count */\n+\t\tcq_ds_cnt &= 0x3FFF3FFF0000;\n+\t}\n+\n+\tplt_write64(0, ws_base + SSOW_LF_GWS_OP_GWC_INVAL);\n+}\n+\n+static void\n+cn9k_sso_hws_reset(void *arg, void *hws)\n+{\n+\tstruct cnxk_sso_evdev *dev = arg;\n+\tstruct cn9k_sso_hws_dual *dws;\n+\tstruct cn9k_sso_hws *ws;\n+\tuint64_t pend_state;\n+\tuint8_t pend_tt;\n+\tuintptr_t base;\n+\tuint64_t tag;\n+\tuint8_t i;\n+\n+\tdws = hws;\n+\tws = hws;\n+\tfor (i = 0; i < (dev->dual_ws ? CN9K_DUAL_WS_NB_WS : 1); i++) {\n+\t\tbase = dev->dual_ws ? dws->base[i] : ws->base;\n+\t\t/* Wait till getwork/swtp/waitw/desched completes. */\n+\t\tdo {\n+\t\t\tpend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);\n+\t\t} while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |\n+\t\t\t\t BIT_ULL(56)));\n+\n+\t\ttag = plt_read64(base + SSOW_LF_GWS_TAG);\n+\t\tpend_tt = (tag >> 32) & 0x3;\n+\t\tif (pend_tt != SSO_TT_EMPTY) { /* Work was pending */\n+\t\t\tif (pend_tt == SSO_TT_ATOMIC ||\n+\t\t\t pend_tt == SSO_TT_ORDERED)\n+\t\t\t\tcnxk_sso_hws_swtag_untag(\n+\t\t\t\t\tbase + SSOW_LF_GWS_OP_SWTAG_UNTAG);\n+\t\t\tplt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);\n+\t\t}\n+\n+\t\t/* Wait for desched to complete. */\n+\t\tdo {\n+\t\t\tpend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);\n+\t\t} while (pend_state & BIT_ULL(58));\n+\t}\n+}\n+\n static void\n cn9k_sso_set_rsrc(void *arg)\n {\n@@ -352,6 +448,21 @@ cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n \treturn (int)nb_unlinks;\n }\n \n+static int\n+cn9k_sso_start(struct rte_eventdev *event_dev)\n+{\n+\tint rc;\n+\n+\trc = cnxk_sso_start(event_dev, cn9k_sso_hws_reset,\n+\t\t\t cn9k_sso_hws_flush_events);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\tcn9k_sso_fp_fns_set(event_dev);\n+\n+\treturn rc;\n+}\n+\n static struct rte_eventdev_ops cn9k_sso_dev_ops = {\n \t.dev_infos_get = cn9k_sso_info_get,\n \t.dev_configure = cn9k_sso_dev_configure,\n@@ -364,6 +475,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = {\n \t.port_link = cn9k_sso_port_link,\n \t.port_unlink = cn9k_sso_port_unlink,\n \t.timeout_ticks = cnxk_sso_timeout_ticks,\n+\n+\t.dev_start = cn9k_sso_start,\n };\n \n static int\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 0e2cc3681..0059b0eca 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -326,6 +326,70 @@ cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,\n \treturn 0;\n }\n \n+static void\n+cnxk_handle_event(void *arg, struct rte_event event)\n+{\n+\tstruct rte_eventdev *event_dev = arg;\n+\n+\tif (event_dev->dev_ops->dev_stop_flush != NULL)\n+\t\tevent_dev->dev_ops->dev_stop_flush(\n+\t\t\tevent_dev->data->dev_id, event,\n+\t\t\tevent_dev->data->dev_stop_flush_arg);\n+}\n+\n+static void\n+cnxk_sso_cleanup(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn,\n+\t\t cnxk_sso_hws_flush_t flush_fn, uint8_t enable)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tuintptr_t hwgrp_base;\n+\tuint16_t i;\n+\tvoid *ws;\n+\n+\tfor (i = 0; i < dev->nb_event_ports; i++) {\n+\t\tws = event_dev->data->ports[i];\n+\t\treset_fn(dev, ws);\n+\t}\n+\n+\trte_mb();\n+\tws = event_dev->data->ports[0];\n+\n+\tfor (i = 0; i < dev->nb_event_queues; i++) {\n+\t\t/* Consume all the events through HWS0 */\n+\t\thwgrp_base = roc_sso_hwgrp_base_get(&dev->sso, i);\n+\t\tflush_fn(ws, i, hwgrp_base, cnxk_handle_event, event_dev);\n+\t\t/* Enable/Disable SSO GGRP */\n+\t\tplt_write64(enable, hwgrp_base + SSO_LF_GGRP_QCTL);\n+\t}\n+}\n+\n+int\n+cnxk_sso_start(struct rte_eventdev *event_dev, cnxk_sso_hws_reset_t reset_fn,\n+\t cnxk_sso_hws_flush_t flush_fn)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tstruct roc_sso_hwgrp_qos qos[dev->qos_queue_cnt];\n+\tint i, rc;\n+\n+\tplt_sso_dbg();\n+\tfor (i = 0; i < dev->qos_queue_cnt; i++) {\n+\t\tqos->hwgrp = dev->qos_parse_data[i].queue;\n+\t\tqos->iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;\n+\t\tqos->taq_prcnt = dev->qos_parse_data[i].taq_prcnt;\n+\t\tqos->xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;\n+\t}\n+\trc = roc_sso_hwgrp_qos_config(&dev->sso, qos, dev->qos_queue_cnt,\n+\t\t\t\t dev->xae_cnt);\n+\tif (rc < 0) {\n+\t\tplt_sso_dbg(\"failed to configure HWGRP QoS rc = %d\", rc);\n+\t\treturn -EINVAL;\n+\t}\n+\tcnxk_sso_cleanup(event_dev, reset_fn, flush_fn, true);\n+\trte_mb();\n+\n+\treturn 0;\n+}\n+\n static void\n parse_queue_param(char *value, void *opaque)\n {\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex ac55d0ccb..6ead171c0 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -48,6 +48,10 @@ typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);\n typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);\n typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map,\n \t\t\t uint16_t nb_link);\n+typedef void (*cnxk_handle_event_t)(void *arg, struct rte_event ev);\n+typedef void (*cnxk_sso_hws_reset_t)(void *arg, void *ws);\n+typedef void (*cnxk_sso_hws_flush_t)(void *ws, uint8_t queue_id, uintptr_t base,\n+\t\t\t\t cnxk_handle_event_t fn, void *arg);\n \n struct cnxk_sso_qos {\n \tuint16_t queue;\n@@ -198,5 +202,8 @@ int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n \t\t\tcnxk_sso_hws_setup_t hws_setup_fn);\n int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,\n \t\t\t uint64_t *tmo_ticks);\n+int cnxk_sso_start(struct rte_eventdev *event_dev,\n+\t\t cnxk_sso_hws_reset_t reset_fn,\n+\t\t cnxk_sso_hws_flush_t flush_fn);\n \n #endif /* __CNXK_EVENTDEV_H__ */\n", "prefixes": [ "16/36" ] }