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GET /api/patches/88638/?format=api
{ "id": 88638, "url": "http://patches.dpdk.org/api/patches/88638/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-42-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306153404.10781-42-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306153404.10781-42-ndabilpuram@marvell.com", "date": "2021-03-06T15:34:01", "name": "[41/44] net/cnxk: add initial version of rte flow support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "28077c1e33eb2e429f183709ce5d6794ae81b05c", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-42-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15515, "url": "http://patches.dpdk.org/api/series/15515/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15515", "date": "2021-03-06T15:33:20", "name": "Marvell CNXK Ethdev Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15515/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88638/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88638/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 98FEDA0548;\n\tSat, 6 Mar 2021 16:40:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D139622A417;\n\tSat, 6 Mar 2021 16:36:26 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C294422A485\n for <dev@dpdk.org>; Sat, 6 Mar 2021 16:36:24 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126FVt9Q029362 for <dev@dpdk.org>; Sat, 6 Mar 2021 07:36:24 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3747yurcew-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 07:36:23 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:36:22 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:36:21 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 07:36:21 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 648E23F7040;\n Sat, 6 Mar 2021 07:36:19 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=EVdyY7SA+Z01FZenwvJRJ4Pvm8KoOHiEWKe/cH+mkz8=;\n b=Tkecpv01LfodsYbCLamEpEEdbmIl49u7MFi7dmJYVFZNGFCyOBFSmWeL61LxOf6kQpF3\n gPctEawKL5dOfJ3bxsY+jVl5+bXCE8ax9hGDotHiABHbPUr3Aw21v3zKV10BL+hCMgqj\n /BTZYjqUH2fvGcT+6ao1ZHby0+IcGM17wMG+Ct23owLgOOCyIyY4nXITAXBfYk98JFq5\n LRjrPIGvHyZXGS+099cNf668VI5zJDWPK1MEQT0rN0ndSo5hznuMtVV0DLnUEy8u4paA\n 9CQx+GSS4vBLFAd6d9ByCm1LkmABz/nr1fiI4133U86AJB86omMZlO1bm8sMRa6RW3fH KA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Sat, 6 Mar 2021 21:04:01 +0530", "Message-ID": "<20210306153404.10781-42-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 41/44] net/cnxk: add initial version of rte flow\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdding initial version of rte_flow support for cnxk family device.\nSupported rte_flow ops are flow_validate, flow_create, flow_crstroy,\nflow_flush, flow_query, flow_isolate.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 118 ++++++++++++++\n doc/guides/nics/features/cnxk.ini | 1 +\n doc/guides/nics/features/cnxk_vec.ini | 1 +\n doc/guides/nics/features/cnxk_vf.ini | 1 +\n drivers/net/cnxk/cnxk_rte_flow.c | 280 ++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_rte_flow.h | 69 +++++++++\n drivers/net/cnxk/meson.build | 1 +\n 7 files changed, 471 insertions(+)\n create mode 100644 drivers/net/cnxk/cnxk_rte_flow.c\n create mode 100644 drivers/net/cnxk/cnxk_rte_flow.h", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex c2a6fbb..87401f0 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -24,6 +24,7 @@ Features of the CNXK Ethdev PMD are:\n - Multiple queues for TX and RX\n - Receiver Side Scaling (RSS)\n - MAC filtering\n+- Generic flow API\n - Inner and Outer Checksum offload\n - Port hardware statistics\n - Link state information\n@@ -222,3 +223,120 @@ Debugging Options\n +---+------------+-------------------------------------------------------+\n | 2 | NPC | --log-level='pmd\\.net.cnxk\\.flow,8' |\n +---+------------+-------------------------------------------------------+\n+\n+RTE Flow Support\n+----------------\n+\n+The OCTEON CN9K/CN10K SoC family NIC has support for the following patterns and\n+actions.\n+\n+Patterns:\n+\n+.. _table_cnxk_supported_flow_item_types:\n+\n+.. table:: Item types\n+\n+ +----+--------------------------------+\n+ | # | Pattern Type |\n+ +====+================================+\n+ | 1 | RTE_FLOW_ITEM_TYPE_ETH |\n+ +----+--------------------------------+\n+ | 2 | RTE_FLOW_ITEM_TYPE_VLAN |\n+ +----+--------------------------------+\n+ | 3 | RTE_FLOW_ITEM_TYPE_E_TAG |\n+ +----+--------------------------------+\n+ | 4 | RTE_FLOW_ITEM_TYPE_IPV4 |\n+ +----+--------------------------------+\n+ | 5 | RTE_FLOW_ITEM_TYPE_IPV6 |\n+ +----+--------------------------------+\n+ | 6 | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4|\n+ +----+--------------------------------+\n+ | 7 | RTE_FLOW_ITEM_TYPE_MPLS |\n+ +----+--------------------------------+\n+ | 8 | RTE_FLOW_ITEM_TYPE_ICMP |\n+ +----+--------------------------------+\n+ | 9 | RTE_FLOW_ITEM_TYPE_UDP |\n+ +----+--------------------------------+\n+ | 10 | RTE_FLOW_ITEM_TYPE_TCP |\n+ +----+--------------------------------+\n+ | 11 | RTE_FLOW_ITEM_TYPE_SCTP |\n+ +----+--------------------------------+\n+ | 12 | RTE_FLOW_ITEM_TYPE_ESP |\n+ +----+--------------------------------+\n+ | 13 | RTE_FLOW_ITEM_TYPE_GRE |\n+ +----+--------------------------------+\n+ | 14 | RTE_FLOW_ITEM_TYPE_NVGRE |\n+ +----+--------------------------------+\n+ | 15 | RTE_FLOW_ITEM_TYPE_VXLAN |\n+ +----+--------------------------------+\n+ | 16 | RTE_FLOW_ITEM_TYPE_GTPC |\n+ +----+--------------------------------+\n+ | 17 | RTE_FLOW_ITEM_TYPE_GTPU |\n+ +----+--------------------------------+\n+ | 18 | RTE_FLOW_ITEM_TYPE_GENEVE |\n+ +----+--------------------------------+\n+ | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE |\n+ +----+--------------------------------+\n+ | 20 | RTE_FLOW_ITEM_TYPE_IPV6_EXT |\n+ +----+--------------------------------+\n+ | 21 | RTE_FLOW_ITEM_TYPE_VOID |\n+ +----+--------------------------------+\n+ | 22 | RTE_FLOW_ITEM_TYPE_ANY |\n+ +----+--------------------------------+\n+ | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY |\n+ +----+--------------------------------+\n+ | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2 |\n+ +----+--------------------------------+\n+\n+.. note::\n+\n+ ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing\n+ bits in the GRE header are equal to 0.\n+\n+Actions:\n+\n+.. _table_cnxk_supported_ingress_action_types:\n+\n+.. table:: Ingress action types\n+\n+ +----+-----------------------------------------+\n+ | # | Action Type |\n+ +====+=========================================+\n+ | 1 | RTE_FLOW_ACTION_TYPE_VOID |\n+ +----+-----------------------------------------+\n+ | 2 | RTE_FLOW_ACTION_TYPE_MARK |\n+ +----+-----------------------------------------+\n+ | 3 | RTE_FLOW_ACTION_TYPE_FLAG |\n+ +----+-----------------------------------------+\n+ | 4 | RTE_FLOW_ACTION_TYPE_COUNT |\n+ +----+-----------------------------------------+\n+ | 5 | RTE_FLOW_ACTION_TYPE_DROP |\n+ +----+-----------------------------------------+\n+ | 6 | RTE_FLOW_ACTION_TYPE_QUEUE |\n+ +----+-----------------------------------------+\n+ | 7 | RTE_FLOW_ACTION_TYPE_RSS |\n+ +----+-----------------------------------------+\n+ | 8 | RTE_FLOW_ACTION_TYPE_PF |\n+ +----+-----------------------------------------+\n+ | 9 | RTE_FLOW_ACTION_TYPE_VF |\n+ +----+-----------------------------------------+\n+ | 10 | RTE_FLOW_ACTION_TYPE_OF_POP_VLAN |\n+ +----+-----------------------------------------+\n+\n+.. _table_cnxk_supported_egress_action_types:\n+\n+.. table:: Egress action types\n+\n+ +----+-----------------------------------------+\n+ | # | Action Type |\n+ +====+=========================================+\n+ | 1 | RTE_FLOW_ACTION_TYPE_COUNT |\n+ +----+-----------------------------------------+\n+ | 2 | RTE_FLOW_ACTION_TYPE_DROP |\n+ +----+-----------------------------------------+\n+ | 3 | RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN |\n+ +----+-----------------------------------------+\n+ | 4 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID |\n+ +----+-----------------------------------------+\n+ | 5 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP |\n+ +----+-----------------------------------------+\ndiff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex 192c15a..7b6d832 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -25,6 +25,7 @@ Unicast MAC filter = Y\n RSS hash = Y\n Inner RSS = Y\n Flow control = Y\n+Flow API = Y\n Jumbo frame = Y\n Scattered Rx = Y\n L3 checksum offload = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex e990480..ef37088 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -24,6 +24,7 @@ Unicast MAC filter = Y\n RSS hash = Y\n Inner RSS = Y\n Flow control = Y\n+Flow API = Y\n Jumbo frame = Y\n L3 checksum offload = Y\n L4 checksum offload = Y\ndiff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini\nindex 3a4417c..69419d1 100644\n--- a/doc/guides/nics/features/cnxk_vf.ini\n+++ b/doc/guides/nics/features/cnxk_vf.ini\n@@ -20,6 +20,7 @@ MTU update = Y\n TSO = Y\n RSS hash = Y\n Inner RSS = Y\n+Flow API = Y\n Jumbo frame = Y\n Scattered Rx = Y\n L3 checksum offload = Y\ndiff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c\nnew file mode 100644\nindex 0000000..344e01f\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_rte_flow.c\n@@ -0,0 +1,280 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#include <cnxk_rte_flow.h>\n+\n+static int\n+cnxk_map_actions(struct rte_eth_dev *dev,\n+\t\t const struct rte_flow_action actions[],\n+\t\t struct roc_npc_action in_actions[])\n+{\n+\tstruct cnxk_eth_dev *hw = dev->data->dev_private;\n+\tconst struct rte_flow_action_count *act_count;\n+\tconst struct rte_flow_action_queue *act_q;\n+\tint rq;\n+\tint i = 0;\n+\n+\tRTE_SET_USED(hw);\n+\n+\tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n+\t\tswitch (actions->type) {\n+\t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_VOID;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_MARK:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_MARK;\n+\t\t\tin_actions[i].conf = actions->conf;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_FLAG:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_FLAG;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n+\t\t\tact_count = (const struct rte_flow_action_count *)\n+\t\t\t\t\t actions->conf;\n+\n+\t\t\tif (act_count->shared == 1) {\n+\t\t\t\tplt_npc_dbg(\"Shared counter is not supported\");\n+\t\t\t\tgoto err_exit;\n+\t\t\t}\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_COUNT;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_DROP;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_PF:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_PF;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_VF:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_VF;\n+\t\t\tin_actions[i].conf = actions->conf;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n+\t\t\tact_q = (const struct rte_flow_action_queue *)\n+\t\t\t\t\tactions->conf;\n+\t\t\trq = act_q->index;\n+\t\t\tif (rq >= dev->data->nb_rx_queues) {\n+\t\t\t\tplt_npc_dbg(\"Invalid queue index\");\n+\t\t\t\tgoto err_exit;\n+\t\t\t}\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_QUEUE;\n+\t\t\tin_actions[i].conf = actions->conf;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_RSS;\n+\t\t\tbreak;\n+\n+\t\tcase RTE_FLOW_ACTION_TYPE_SECURITY:\n+\t\t\tin_actions[i].type = ROC_NPC_ACTION_TYPE_SEC;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tplt_npc_dbg(\"Action is not supported = %d\",\n+\t\t\t\t actions->type);\n+\t\t\tgoto err_exit;\n+\t\t}\n+\t\ti++;\n+\t}\n+\tin_actions[i].type = ROC_NPC_ACTION_TYPE_END;\n+\treturn 0;\n+\n+err_exit:\n+\treturn -EINVAL;\n+}\n+\n+static int\n+cnxk_map_flow_data(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n+\t\t const struct rte_flow_item pattern[],\n+\t\t const struct rte_flow_action actions[],\n+\t\t struct roc_npc_attr *in_attr,\n+\t\t struct roc_npc_item_info in_pattern[],\n+\t\t struct roc_npc_action in_actions[])\n+{\n+\tint i = 0;\n+\n+\tin_attr->priority = attr->priority;\n+\tin_attr->ingress = attr->ingress;\n+\tin_attr->egress = attr->egress;\n+\n+\twhile (pattern->type != RTE_FLOW_ITEM_TYPE_END) {\n+\t\tin_pattern[i].spec = pattern->spec;\n+\t\tin_pattern[i].last = pattern->last;\n+\t\tin_pattern[i].mask = pattern->mask;\n+\t\tin_pattern[i].type = term[pattern->type].item_type;\n+\t\tin_pattern[i].size = term[pattern->type].item_size;\n+\t\tpattern++;\n+\t\ti++;\n+\t}\n+\tin_pattern[i].type = ROC_NPC_ITEM_TYPE_END;\n+\n+\treturn cnxk_map_actions(dev, actions, in_actions);\n+}\n+\n+static int\n+cnxk_flow_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n+\t\t const struct rte_flow_item pattern[],\n+\t\t const struct rte_flow_action actions[],\n+\t\t struct rte_flow_error *error)\n+{\n+\tstruct roc_npc_item_info in_pattern[ROC_NPC_ITEM_TYPE_END + 1];\n+\tstruct roc_npc_action in_actions[ROC_NPC_MAX_ACTION_COUNT];\n+\tstruct cnxk_eth_dev *hw = dev->data->dev_private;\n+\tstruct roc_npc *npc = &hw->npc;\n+\tstruct roc_npc_attr in_attr;\n+\tstruct roc_npc_flow flow;\n+\tint rc;\n+\n+\trc = cnxk_map_flow_data(dev, attr, pattern, actions, &in_attr,\n+\t\t\t\tin_pattern, in_actions);\n+\tif (rc) {\n+\t\trte_flow_error_set(error, 0, RTE_FLOW_ERROR_TYPE_ACTION_NUM,\n+\t\t\t\t NULL, \"Failed to map flow data\");\n+\t\treturn rc;\n+\t}\n+\n+\treturn roc_npc_flow_parse(npc, &in_attr, in_pattern, in_actions, &flow);\n+}\n+\n+static struct rte_flow *\n+cnxk_flow_create(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n+\t\t const struct rte_flow_item pattern[],\n+\t\t const struct rte_flow_action actions[],\n+\t\t struct rte_flow_error *error)\n+{\n+\tstruct cnxk_eth_dev *hw = dev->data->dev_private;\n+\tstruct roc_npc_item_info in_pattern[ROC_NPC_ITEM_TYPE_END + 1];\n+\tstruct roc_npc_action in_actions[ROC_NPC_MAX_ACTION_COUNT];\n+\tstruct roc_npc *npc = &hw->npc;\n+\tstruct roc_npc_attr in_attr;\n+\tstruct roc_npc_flow *flow;\n+\tint errcode;\n+\tint rc;\n+\n+\trc = cnxk_map_flow_data(dev, attr, pattern, actions, &in_attr,\n+\t\t\t\tin_pattern, in_actions);\n+\tif (rc) {\n+\t\trte_flow_error_set(error, 0, RTE_FLOW_ERROR_TYPE_ACTION_NUM,\n+\t\t\t\t NULL, \"Failed to map flow data\");\n+\t\treturn NULL;\n+\t}\n+\n+\tflow = roc_npc_flow_create(npc, &in_attr, in_pattern, in_actions,\n+\t\t\t\t &errcode);\n+\tif (errcode != 0) {\n+\t\trte_flow_error_set(error, errcode, errcode, NULL,\n+\t\t\t\t roc_error_msg_get(errcode));\n+\t\treturn NULL;\n+\t}\n+\n+\treturn (struct rte_flow *)flow;\n+}\n+\n+static int\n+cnxk_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,\n+\t\t struct rte_flow_error *error)\n+{\n+\tstruct roc_npc_flow *in_flow = (struct roc_npc_flow *)flow;\n+\tstruct cnxk_eth_dev *hw = dev->data->dev_private;\n+\tstruct roc_npc *npc = &hw->npc;\n+\tint rc;\n+\n+\trc = roc_npc_flow_destroy(npc, in_flow);\n+\tif (rc)\n+\t\trte_flow_error_set(error, rc, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL, \"Flow Destroy failed\");\n+\treturn rc;\n+}\n+\n+static int\n+cnxk_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)\n+{\n+\tstruct cnxk_eth_dev *hw = dev->data->dev_private;\n+\tstruct roc_npc *npc = &hw->npc;\n+\tint rc;\n+\n+\trc = roc_npc_mcam_free_all_resources(npc);\n+\tif (rc) {\n+\t\trte_flow_error_set(error, EIO, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t NULL, \"Failed to flush filter\");\n+\t\treturn -rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,\n+\t\tconst struct rte_flow_action *action, void *data,\n+\t\tstruct rte_flow_error *error)\n+{\n+\tstruct roc_npc_flow *in_flow = (struct roc_npc_flow *)flow;\n+\tstruct cnxk_eth_dev *hw = dev->data->dev_private;\n+\tstruct roc_npc *npc = &hw->npc;\n+\tstruct rte_flow_query_count *query = data;\n+\tconst char *errmsg = NULL;\n+\tint errcode = ENOTSUP;\n+\tint rc;\n+\n+\tif (action->type != RTE_FLOW_ACTION_TYPE_COUNT) {\n+\t\terrmsg = \"Only COUNT is supported in query\";\n+\t\tgoto err_exit;\n+\t}\n+\n+\tif (in_flow->ctr_id == NPC_COUNTER_NONE) {\n+\t\terrmsg = \"Counter is not available\";\n+\t\tgoto err_exit;\n+\t}\n+\n+\trc = roc_npc_mcam_read_counter(npc, in_flow->ctr_id, &query->hits);\n+\tif (rc != 0) {\n+\t\terrcode = EIO;\n+\t\terrmsg = \"Error reading flow counter\";\n+\t\tgoto err_exit;\n+\t}\n+\tquery->hits_set = 1;\n+\tquery->bytes_set = 0;\n+\n+\tif (query->reset)\n+\t\trc = roc_npc_mcam_clear_counter(npc, in_flow->ctr_id);\n+\tif (rc != 0) {\n+\t\terrcode = EIO;\n+\t\terrmsg = \"Error clearing flow counter\";\n+\t\tgoto err_exit;\n+\t}\n+\n+\treturn 0;\n+\n+err_exit:\n+\trte_flow_error_set(error, errcode, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t NULL, errmsg);\n+\treturn -rte_errno;\n+}\n+\n+static int\n+cnxk_flow_isolate(struct rte_eth_dev *dev __rte_unused, int enable __rte_unused,\n+\t\t struct rte_flow_error *error)\n+{\n+\t/* If we support, we need to un-install the default mcam\n+\t * entry for this port.\n+\t */\n+\n+\trte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t NULL, \"Flow isolation not supported\");\n+\n+\treturn -rte_errno;\n+}\n+\n+const struct rte_flow_ops cnxk_flow_ops = {\n+\t.validate = cnxk_flow_validate,\n+\t.create = cnxk_flow_create,\n+\t.destroy = cnxk_flow_destroy,\n+\t.flush = cnxk_flow_flush,\n+\t.query = cnxk_flow_query,\n+\t.isolate = cnxk_flow_isolate,\n+};\ndiff --git a/drivers/net/cnxk/cnxk_rte_flow.h b/drivers/net/cnxk/cnxk_rte_flow.h\nnew file mode 100644\nindex 0000000..3740226\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_rte_flow.h\n@@ -0,0 +1,69 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef __CNXK_RTE_FLOW_H__\n+#define __CNXK_RTE_FLOW_H__\n+\n+#include <rte_flow_driver.h>\n+#include <rte_malloc.h>\n+\n+#include \"cnxk_ethdev.h\"\n+#include \"roc_api.h\"\n+#include \"roc_npc_priv.h\"\n+\n+struct cnxk_rte_flow_term_info {\n+\tuint16_t item_type;\n+\tuint16_t item_size;\n+};\n+\n+struct cnxk_rte_flow_term_info term[] = {\n+\t[RTE_FLOW_ITEM_TYPE_ETH] = {ROC_NPC_ITEM_TYPE_ETH,\n+\t\t\t\t sizeof(struct rte_flow_item_eth)},\n+\t[RTE_FLOW_ITEM_TYPE_VLAN] = {ROC_NPC_ITEM_TYPE_VLAN,\n+\t\t\t\t sizeof(struct rte_flow_item_vlan)},\n+\t[RTE_FLOW_ITEM_TYPE_E_TAG] = {ROC_NPC_ITEM_TYPE_E_TAG,\n+\t\t\t\t sizeof(struct rte_flow_item_e_tag)},\n+\t[RTE_FLOW_ITEM_TYPE_IPV4] = {ROC_NPC_ITEM_TYPE_IPV4,\n+\t\t\t\t sizeof(struct rte_flow_item_ipv4)},\n+\t[RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6,\n+\t\t\t\t sizeof(struct rte_flow_item_ipv6)},\n+\t[RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,\n+\t\t sizeof(struct rte_flow_item_arp_eth_ipv4)},\n+\t[RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS,\n+\t\t\t\t sizeof(struct rte_flow_item_mpls)},\n+\t[RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP,\n+\t\t\t\t sizeof(struct rte_flow_item_icmp)},\n+\t[RTE_FLOW_ITEM_TYPE_UDP] = {ROC_NPC_ITEM_TYPE_UDP,\n+\t\t\t\t sizeof(struct rte_flow_item_udp)},\n+\t[RTE_FLOW_ITEM_TYPE_TCP] = {ROC_NPC_ITEM_TYPE_TCP,\n+\t\t\t\t sizeof(struct rte_flow_item_tcp)},\n+\t[RTE_FLOW_ITEM_TYPE_SCTP] = {ROC_NPC_ITEM_TYPE_SCTP,\n+\t\t\t\t sizeof(struct rte_flow_item_sctp)},\n+\t[RTE_FLOW_ITEM_TYPE_ESP] = {ROC_NPC_ITEM_TYPE_ESP,\n+\t\t\t\t sizeof(struct rte_flow_item_esp)},\n+\t[RTE_FLOW_ITEM_TYPE_GRE] = {ROC_NPC_ITEM_TYPE_GRE,\n+\t\t\t\t sizeof(struct rte_flow_item_gre)},\n+\t[RTE_FLOW_ITEM_TYPE_NVGRE] = {ROC_NPC_ITEM_TYPE_NVGRE,\n+\t\t\t\t sizeof(struct rte_flow_item_nvgre)},\n+\t[RTE_FLOW_ITEM_TYPE_VXLAN] = {ROC_NPC_ITEM_TYPE_VXLAN,\n+\t\t\t\t sizeof(struct rte_flow_item_vxlan)},\n+\t[RTE_FLOW_ITEM_TYPE_GTPC] = {ROC_NPC_ITEM_TYPE_GTPC,\n+\t\t\t\t sizeof(struct rte_flow_item_gtp)},\n+\t[RTE_FLOW_ITEM_TYPE_GTPU] = {ROC_NPC_ITEM_TYPE_GTPU,\n+\t\t\t\t sizeof(struct rte_flow_item_gtp)},\n+\t[RTE_FLOW_ITEM_TYPE_GENEVE] = {ROC_NPC_ITEM_TYPE_GENEVE,\n+\t\t\t\t sizeof(struct rte_flow_item_geneve)},\n+\t[RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = {ROC_NPC_ITEM_TYPE_VXLAN_GPE,\n+\t\t\tsizeof(struct rte_flow_item_vxlan_gpe)},\n+\t[RTE_FLOW_ITEM_TYPE_IPV6_EXT] = {ROC_NPC_ITEM_TYPE_IPV6_EXT,\n+\t\t\t\t\t sizeof(struct rte_flow_item_ipv6_ext)},\n+\t[RTE_FLOW_ITEM_TYPE_VOID] = {ROC_NPC_ITEM_TYPE_VOID, 0},\n+\t[RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0},\n+\t[RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY,\n+\t\t\t\t\tsizeof(uint32_t)},\n+\t[RTE_FLOW_ITEM_TYPE_HIGIG2] = {\n+\t\tROC_NPC_ITEM_TYPE_HIGIG2,\n+\t\tsizeof(struct rte_flow_item_higig2_hdr)}\n+};\n+\n+#endif /* __CNXK_RTE_FLOW_H__ */\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 0e141d7..49aa016 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -13,6 +13,7 @@ sources = files('cnxk_ethdev.c',\n \t\t'cnxk_ethdev_devargs.c',\n \t\t'cnxk_link.c',\n \t\t'cnxk_lookup.c',\n+\t\t'cnxk_rte_flow.c',\n \t\t'cnxk_stats.c')\n \n # CN9K\n", "prefixes": [ "41/44" ] }