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GET /api/patches/88618/?format=api
{ "id": 88618, "url": "http://patches.dpdk.org/api/patches/88618/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-22-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306153404.10781-22-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306153404.10781-22-ndabilpuram@marvell.com", "date": "2021-03-06T15:33:41", "name": "[21/44] net/cnxk: add Tx multi-segment version for cn10k", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e7943dbeb9ad69e9cb275f16a635892911f3027b", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-22-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15515, "url": "http://patches.dpdk.org/api/series/15515/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15515", "date": "2021-03-06T15:33:20", "name": "Marvell CNXK Ethdev Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15515/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88618/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/88618/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 50A46A0548;\n\tSat, 6 Mar 2021 16:37:42 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 40F0622A3EC;\n\tSat, 6 Mar 2021 16:35:25 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id E3B9922A37A\n for <dev@dpdk.org>; Sat, 6 Mar 2021 16:35:23 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126FVumM029368 for <dev@dpdk.org>; Sat, 6 Mar 2021 07:35:23 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3747yurccn-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 07:35:23 -0800", "from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:35:21 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:35:21 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 07:35:21 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 8B33C3F703F;\n Sat, 6 Mar 2021 07:35:18 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=/i26B1zPNjdhzdF2qOzdeDLEc1WFKoMZdZ7yMz44HAA=;\n b=P7BXcHfhdnZXYLbE9MxxHOnPLZ8ndpSicsKOtZl84vfGS+NPJerz0ubaBnRzGsPEmJpv\n 4fT1B5R335rGo+wHktQ9fi1tuZbRo2lN6B4o3lvNo0nytKUZsNP3r8CPXLj11OO2nMxX\n B8J+CkB+bnVlFfKyKI/J3GxvyfWEIbpBJmpa/lO15iXO0k+4BOgDsRacsTTz4JfkAsjN\n M49tBEy2hTb6ppzetCy+QKPy7+RQ62zQaHtA3q4OQuc/kGuaoS1S+mhgkgEA+R7gOAnt\n pmMllqi21FZIUK2TVdWp1BVF3UpLhJ79WhLJiYhdFCZXjOOrU+GgCB0gfF4cccCN3Axn PA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Sat, 6 Mar 2021 21:03:41 +0530", "Message-ID": "<20210306153404.10781-22-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 21/44] net/cnxk: add Tx multi-segment version for\n cn10k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add Tx burst multi-segment version for CN10K.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/net/cnxk/cn10k_tx.c | 124 ++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cn10k_tx.h | 71 +++++++++++++++++++++++++\n 2 files changed, 195 insertions(+)", "diff": "diff --git a/drivers/net/cnxk/cn10k_tx.c b/drivers/net/cnxk/cn10k_tx.c\nindex 0fad4c0..d170f31 100644\n--- a/drivers/net/cnxk/cn10k_tx.c\n+++ b/drivers/net/cnxk/cn10k_tx.c\n@@ -125,6 +125,98 @@ nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n \treturn pkts;\n }\n \n+static __rte_always_inline uint16_t\n+nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n+\t\t uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct cn10k_eth_txq *txq = tx_queue;\n+\tuintptr_t pa0, pa1, lmt_addr = txq->lmt_base;\n+\tconst rte_iova_t io_addr = txq->io_addr;\n+\tuint16_t segdw, lmt_id, burst, left, i;\n+\tuint64_t data0, data1;\n+\t__uint128_t data128;\n+\tuint16_t shft;\n+\n+\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\n+\tcn10k_nix_tx_skeleton(txq, cmd, flags);\n+\n+\t/* Reduce the cached count */\n+\ttxq->fc_cache_pkts -= pkts;\n+\n+\t/* Get LMT base address and LMT ID as lcore id */\n+\tROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);\n+\tleft = pkts;\n+again:\n+\tburst = left > 32 ? 32 : left;\n+\tshft = 16;\n+\tdata128 = 0;\n+\tfor (i = 0; i < burst; i++) {\n+\t\t/* Perform header writes for TSO, barrier at\n+\t\t * lmt steorl will suffice.\n+\t\t */\n+\t\tif (flags & NIX_TX_OFFLOAD_TSO_F)\n+\t\t\tcn10k_nix_xmit_prepare_tso(tx_pkts[i], flags);\n+\n+\t\tcn10k_nix_xmit_prepare(tx_pkts[i], cmd, lmt_addr, flags);\n+\t\t/* Store sg list directly on lmt line */\n+\t\tsegdw = cn10k_nix_prepare_mseg(tx_pkts[i], (uint64_t *)lmt_addr,\n+\t\t\t\t\t flags);\n+\t\tlmt_addr += (1ULL << ROC_LMT_LINE_SIZE_LOG2);\n+\t\tdata128 |= (((__uint128_t)(segdw - 1)) << shft);\n+\t\tshft += 3;\n+\t}\n+\n+\tdata0 = (uint64_t)data128;\n+\tdata1 = (uint64_t)(data128 >> 64);\n+\t/* Make data0 similar to data1 */\n+\tdata0 >>= 16;\n+\t/* Trigger LMTST */\n+\tif (burst > 16) {\n+\t\tpa0 = io_addr | (data0 & 0x7) << 4;\n+\t\tdata0 &= ~0x7ULL;\n+\t\t/* Move lmtst1..15 sz to bits 63:19 */\n+\t\tdata0 <<= 16;\n+\t\tdata0 |= (15ULL << 12);\n+\t\tdata0 |= (uint64_t)lmt_id;\n+\n+\t\t/* STEOR0 */\n+\t\troc_lmt_submit_steorl(data0, pa0);\n+\n+\t\tpa1 = io_addr | (data1 & 0x7) << 4;\n+\t\tdata1 &= ~0x7ULL;\n+\t\tdata1 <<= 16;\n+\t\tdata1 |= ((uint64_t)(burst - 17)) << 12;\n+\t\tdata1 |= (uint64_t)(lmt_id + 16);\n+\n+\t\t/* STEOR1 */\n+\t\troc_lmt_submit_steorl(data1, pa1);\n+\t} else if (burst) {\n+\t\tpa0 = io_addr | (data0 & 0x7) << 4;\n+\t\tdata0 &= ~0x7ULL;\n+\t\t/* Move lmtst1..15 sz to bits 63:19 */\n+\t\tdata0 <<= 16;\n+\t\tdata0 |= ((burst - 1) << 12);\n+\t\tdata0 |= (uint64_t)lmt_id;\n+\n+\t\t/* STEOR0 */\n+\t\troc_lmt_submit_steorl(data0, pa0);\n+\t}\n+\n+\tleft -= burst;\n+\trte_io_wmb();\n+\tif (left) {\n+\t\t/* Start processing another burst */\n+\t\ttx_pkts += burst;\n+\t\t/* Reset lmt base addr */\n+\t\tlmt_addr -= (1ULL << ROC_LMT_LINE_SIZE_LOG2);\n+\t\tlmt_addr &= (~(BIT_ULL(ROC_LMT_BASE_PER_CORE_LOG2) - 1));\n+\t\tgoto again;\n+\t}\n+\n+\treturn pkts;\n+}\n+\n \n #define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t \\\n \tstatic uint16_t __rte_noinline __rte_hot cn10k_nix_xmit_pkts_##name( \\\n@@ -142,6 +234,25 @@ nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts,\n NIX_TX_FASTPATH_MODES\n #undef T\n \n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t \\\n+\tstatic uint16_t __rte_noinline __rte_hot \\\n+\t\tcn10k_nix_xmit_pkts_mseg_##name(void *tx_queue, \\\n+\t\t\t\t\t\tstruct rte_mbuf **tx_pkts, \\\n+\t\t\t\t\t\tuint16_t pkts) \\\n+\t{ \\\n+\t\tuint64_t cmd[(sz)]; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\t/* For TSO inner checksum is a must */ \\\n+\t\tif (((flags) & NIX_TX_OFFLOAD_TSO_F) &&\t\t\t \\\n+\t\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t \\\n+\t\t\treturn 0; \\\n+\t\treturn nix_xmit_pkts_mseg(tx_queue, tx_pkts, pkts, cmd, \\\n+\t\t\t\t\t (flags) | NIX_TX_MULTI_SEG_F); \\\n+\t}\n+\n+NIX_TX_FASTPATH_MODES\n+#undef T\n+\n static inline void\n pick_tx_func(struct rte_eth_dev *eth_dev,\n \t const eth_tx_burst_t tx_burst[2][2][2][2][2])\n@@ -160,6 +271,8 @@ pick_tx_func(struct rte_eth_dev *eth_dev,\n void\n cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n {\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\n \tconst eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2] = {\n #define T(name, f4, f3, f2, f1, f0, sz, flags) \\\n \t[f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_##name,\n@@ -168,7 +281,18 @@ cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n #undef T\n \t};\n \n+\tconst eth_tx_burst_t nix_eth_tx_burst_mseg[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+\t[f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_mseg_##name,\n+\n+\t\tNIX_TX_FASTPATH_MODES\n+#undef T\n+\t};\n+\n \tpick_tx_func(eth_dev, nix_eth_tx_burst);\n \n+\tif (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)\n+\t\tpick_tx_func(eth_dev, nix_eth_tx_burst_mseg);\n+\n \trte_mb();\n }\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex ce1d4a0..22f7a2b 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -295,6 +295,77 @@ cn10k_nix_xmit_prepare(struct rte_mbuf *m, uint64_t *cmd, uintptr_t lmt_addr,\n \t*(rte_iova_t *)(lmt_addr + 8) = *(rte_iova_t *)(sg + 1);\n }\n \n+static __rte_always_inline uint16_t\n+cn10k_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tunion nix_send_sg_s *sg;\n+\tstruct rte_mbuf *m_next;\n+\tuint64_t *slist, sg_u;\n+\tuint64_t nb_segs;\n+\tuint64_t segdw;\n+\tuint8_t off, i;\n+\n+\tsend_hdr = (struct nix_send_hdr_s *)cmd;\n+\tsend_hdr->w0.total = m->pkt_len;\n+\tsend_hdr->w0.aura = roc_npa_aura_handle_to_aura(m->pool->pool_id);\n+\n+\tif (flags & NIX_TX_NEED_EXT_HDR)\n+\t\toff = 2;\n+\telse\n+\t\toff = 0;\n+\n+\tsg = (union nix_send_sg_s *)&cmd[2 + off];\n+\t/* Clear sg->u header before use */\n+\tsg->u &= 0xFC00000000000000;\n+\tsg_u = sg->u;\n+\tslist = &cmd[3 + off];\n+\n+\ti = 0;\n+\tnb_segs = m->nb_segs;\n+\n+\t/* Fill mbuf segments */\n+\tdo {\n+\t\tm_next = m->next;\n+\t\tsg_u = sg_u | ((uint64_t)m->data_len << (i << 4));\n+\t\t*slist = rte_mbuf_data_iova(m);\n+\t\t/* Set invert df if buffer is not to be freed by H/W */\n+\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)\n+\t\t\tsg_u |= (cnxk_nix_prefree_seg(m) << (i + 55));\n+\t\t\t/* Mark mempool object as \"put\" since it is freed by NIX\n+\t\t\t */\n+#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n+\t\tif (!(sg_u & (1ULL << (i + 55))))\n+\t\t\t__mempool_check_cookies(m->pool, (void **)&m, 1, 0);\n+#endif\n+\t\tslist++;\n+\t\ti++;\n+\t\tnb_segs--;\n+\t\tif (i > 2 && nb_segs) {\n+\t\t\ti = 0;\n+\t\t\t/* Next SG subdesc */\n+\t\t\t*(uint64_t *)slist = sg_u & 0xFC00000000000000;\n+\t\t\tsg->u = sg_u;\n+\t\t\tsg->segs = 3;\n+\t\t\tsg = (union nix_send_sg_s *)slist;\n+\t\t\tsg_u = sg->u;\n+\t\t\tslist++;\n+\t\t}\n+\t\tm = m_next;\n+\t} while (nb_segs);\n+\n+\tsg->u = sg_u;\n+\tsg->segs = i;\n+\tsegdw = (uint64_t *)slist - (uint64_t *)&cmd[2 + off];\n+\t/* Roundup extra dwords to multiple of 2 */\n+\tsegdw = (segdw >> 1) + (segdw & 0x1);\n+\t/* Default dwords */\n+\tsegdw += (off >> 1) + 1;\n+\tsend_hdr->w0.sizem1 = segdw - 1;\n+\n+\treturn segdw;\n+}\n+\n #define L3L4CSUM_F NIX_TX_OFFLOAD_L3_L4_CSUM_F\n #define OL3OL4CSUM_F NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\n #define VLAN_F\t NIX_TX_OFFLOAD_VLAN_QINQ_F\n", "prefixes": [ "21/44" ] }