Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/88616/?format=api
{ "id": 88616, "url": "http://patches.dpdk.org/api/patches/88616/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-20-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306153404.10781-20-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306153404.10781-20-ndabilpuram@marvell.com", "date": "2021-03-06T15:33:39", "name": "[19/44] net/cnxk: add Rx vector version for cn10k", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2f80f68133c64eeafbb4243b50e0f501237b2cd5", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-20-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15515, "url": "http://patches.dpdk.org/api/series/15515/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15515", "date": "2021-03-06T15:33:20", "name": "Marvell CNXK Ethdev Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15515/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88616/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/88616/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 56D5AA0548;\n\tSat, 6 Mar 2021 16:37:22 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6513C22A3EF;\n\tSat, 6 Mar 2021 16:35:19 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 1A36822A358\n for <dev@dpdk.org>; Sat, 6 Mar 2021 16:35:16 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126FYJGI001300 for <dev@dpdk.org>; Sat, 6 Mar 2021 07:35:16 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3747yurccc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 07:35:16 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:35:14 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:35:14 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 07:35:14 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id C3A3A3F7044;\n Sat, 6 Mar 2021 07:35:11 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=rAHvnjndr8/eZe3zxEbkfprhtXAqakwNSqCPX64wN1c=;\n b=Le7c4W1vorEitQ3QSH56TrXhgS1gYNFgF6f0PD0cuzJThcNRSws0/0LEg9a7Q4gv64g4\n lgGBlfmBYQdyJxhZ+0Qq7VGh7P3mt3Gldfs1wRSeX+bYNFriIpX+MRhiqpS2hdJxutmx\n mDSC4DrQPhy5XJQMuNTnLGsk8k+gMr6jLRluk2hxilJqaz0Pi7xqX5wd3wjZTZmLeKT+\n DFLIsxbokVnuDdpLV7u56pV+Hsr5fqZK/vHsPa8dxmQlYDlOYd7ykmW9hpm77L5paRU3\n t2F0VFhxMSiPa3PFPpQIDiFM6VADjEFv+rMBAV/vEaSFif8P1yHD+f4W3dLeFnS0tsOU KA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Sat, 6 Mar 2021 21:03:39 +0530", "Message-ID": "<20210306153404.10781-20-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 19/44] net/cnxk: add Rx vector version for cn10k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Rx burst vector version for CN10K.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 1 +\n drivers/net/cnxk/cn10k_rx.c | 240 +++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 240 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex 789ec29..4187e9d 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -24,6 +24,7 @@ Features of the CNXK Ethdev PMD are:\n - Receiver Side Scaling (RSS)\n - Link state information\n - Scatter-Gather IO support\n+- Vector Poll mode driver\n \n Prerequisites\n -------------\ndiff --git a/drivers/net/cnxk/cn10k_rx.c b/drivers/net/cnxk/cn10k_rx.c\nindex b98e7a1..2bc952d 100644\n--- a/drivers/net/cnxk/cn10k_rx.c\n+++ b/drivers/net/cnxk/cn10k_rx.c\n@@ -2,6 +2,8 @@\n * Copyright(C) 2021 Marvell.\n */\n \n+#include <rte_vect.h>\n+\n #include \"cn10k_ethdev.h\"\n #include \"cn10k_rx.h\"\n \n@@ -83,6 +85,223 @@ nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \treturn nb_pkts;\n }\n \n+#if defined(RTE_ARCH_ARM64)\n+\n+static __rte_always_inline uint16_t\n+nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n+\t\t const uint16_t flags)\n+{\n+\tstruct cn10k_eth_rxq *rxq = rx_queue;\n+\tuint16_t packets = 0;\n+\tuint64x2_t cq0_w8, cq1_w8, cq2_w8, cq3_w8, mbuf01, mbuf23;\n+\tconst uint64_t mbuf_initializer = rxq->mbuf_initializer;\n+\tconst uint64x2_t data_off = vdupq_n_u64(rxq->data_off);\n+\tuint64_t ol_flags0, ol_flags1, ol_flags2, ol_flags3;\n+\tuint64x2_t rearm0 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm1 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n+\tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n+\tconst uint16_t *lookup_mem = rxq->lookup_mem;\n+\tconst uint32_t qmask = rxq->qmask;\n+\tconst uint64_t wdata = rxq->wdata;\n+\tconst uintptr_t desc = rxq->desc;\n+\tuint8x16_t f0, f1, f2, f3;\n+\tuint32_t head = rxq->head;\n+\tuint16_t pkts_left;\n+\n+\tpkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n+\tpkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);\n+\n+\t/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */\n+\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\n+\twhile (packets < pkts) {\n+\t\t/* Exit loop if head is about to wrap and become unaligned */\n+\t\tif (((head + NIX_DESCS_PER_LOOP - 1) & qmask) <\n+\t\t NIX_DESCS_PER_LOOP) {\n+\t\t\tpkts_left += (pkts - packets);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tconst uintptr_t cq0 = desc + CQE_SZ(head);\n+\n+\t\t/* Prefetch N desc ahead */\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(8)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(9)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(10)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(11)));\n+\n+\t\t/* Get NIX_RX_SG_S for size and buffer pointer */\n+\t\tcq0_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0) + 64));\n+\t\tcq1_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1) + 64));\n+\t\tcq2_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2) + 64));\n+\t\tcq3_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3) + 64));\n+\n+\t\t/* Extract mbuf from NIX_RX_SG_S */\n+\t\tmbuf01 = vzip2q_u64(cq0_w8, cq1_w8);\n+\t\tmbuf23 = vzip2q_u64(cq2_w8, cq3_w8);\n+\t\tmbuf01 = vqsubq_u64(mbuf01, data_off);\n+\t\tmbuf23 = vqsubq_u64(mbuf23, data_off);\n+\n+\t\t/* Move mbufs to scalar registers for future use */\n+\t\tmbuf0 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 0);\n+\t\tmbuf1 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 1);\n+\t\tmbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0);\n+\t\tmbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1);\n+\n+\t\t/* Mask to get packet len from NIX_RX_SG_S */\n+\t\tconst uint8x16_t shuf_msk = {\n+\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t0, 1, /* octet 1~0, low 16 bits pkt_len */\n+\t\t\t0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t0, 1, /* octet 1~0, 16 bits data_len */\n+\t\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};\n+\n+\t\t/* Form the rx_descriptor_fields1 with pkt_len and data_len */\n+\t\tf0 = vqtbl1q_u8(cq0_w8, shuf_msk);\n+\t\tf1 = vqtbl1q_u8(cq1_w8, shuf_msk);\n+\t\tf2 = vqtbl1q_u8(cq2_w8, shuf_msk);\n+\t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n+\n+\t\t/* Load CQE word0 and word 1 */\n+\t\tuint64_t cq0_w0 = ((uint64_t *)(cq0 + CQE_SZ(0)))[0];\n+\t\tuint64_t cq0_w1 = ((uint64_t *)(cq0 + CQE_SZ(0)))[1];\n+\t\tuint64_t cq1_w0 = ((uint64_t *)(cq0 + CQE_SZ(1)))[0];\n+\t\tuint64_t cq1_w1 = ((uint64_t *)(cq0 + CQE_SZ(1)))[1];\n+\t\tuint64_t cq2_w0 = ((uint64_t *)(cq0 + CQE_SZ(2)))[0];\n+\t\tuint64_t cq2_w1 = ((uint64_t *)(cq0 + CQE_SZ(2)))[1];\n+\t\tuint64_t cq3_w0 = ((uint64_t *)(cq0 + CQE_SZ(3)))[0];\n+\t\tuint64_t cq3_w1 = ((uint64_t *)(cq0 + CQE_SZ(3)))[1];\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_RSS_F) {\n+\t\t\t/* Fill rss in the rx_descriptor_fields1 */\n+\t\t\tf0 = vsetq_lane_u32(cq0_w0, f0, 3);\n+\t\t\tf1 = vsetq_lane_u32(cq1_w0, f1, 3);\n+\t\t\tf2 = vsetq_lane_u32(cq2_w0, f2, 3);\n+\t\t\tf3 = vsetq_lane_u32(cq3_w0, f3, 3);\n+\t\t\tol_flags0 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags1 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags2 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags3 = PKT_RX_RSS_HASH;\n+\t\t} else {\n+\t\t\tol_flags0 = 0;\n+\t\t\tol_flags1 = 0;\n+\t\t\tol_flags2 = 0;\n+\t\t\tol_flags3 = 0;\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_PTYPE_F) {\n+\t\t\t/* Fill packet_type in the rx_descriptor_fields1 */\n+\t\t\tf0 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq0_w1),\n+\t\t\t\t\t f0, 0);\n+\t\t\tf1 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq1_w1),\n+\t\t\t\t\t f1, 0);\n+\t\t\tf2 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq2_w1),\n+\t\t\t\t\t f2, 0);\n+\t\t\tf3 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq3_w1),\n+\t\t\t\t\t f3, 0);\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_CHECKSUM_F) {\n+\t\t\tol_flags0 |= nix_rx_olflags_get(lookup_mem, cq0_w1);\n+\t\t\tol_flags1 |= nix_rx_olflags_get(lookup_mem, cq1_w1);\n+\t\t\tol_flags2 |= nix_rx_olflags_get(lookup_mem, cq2_w1);\n+\t\t\tol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_MARK_UPDATE_F) {\n+\t\t\tol_flags0 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(0) + 38), ol_flags0,\n+\t\t\t\tmbuf0);\n+\t\t\tol_flags1 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(1) + 38), ol_flags1,\n+\t\t\t\tmbuf1);\n+\t\t\tol_flags2 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(2) + 38), ol_flags2,\n+\t\t\t\tmbuf2);\n+\t\t\tol_flags3 = nix_update_match_id(\n+\t\t\t\t*(uint16_t *)(cq0 + CQE_SZ(3) + 38), ol_flags3,\n+\t\t\t\tmbuf3);\n+\t\t}\n+\n+\t\t/* Form rearm_data with ol_flags */\n+\t\trearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);\n+\t\trearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);\n+\t\trearm2 = vsetq_lane_u64(ol_flags2, rearm2, 1);\n+\t\trearm3 = vsetq_lane_u64(ol_flags3, rearm3, 1);\n+\n+\t\t/* Update rx_descriptor_fields1 */\n+\t\tvst1q_u64((uint64_t *)mbuf0->rx_descriptor_fields1, f0);\n+\t\tvst1q_u64((uint64_t *)mbuf1->rx_descriptor_fields1, f1);\n+\t\tvst1q_u64((uint64_t *)mbuf2->rx_descriptor_fields1, f2);\n+\t\tvst1q_u64((uint64_t *)mbuf3->rx_descriptor_fields1, f3);\n+\n+\t\t/* Update rearm_data */\n+\t\tvst1q_u64((uint64_t *)mbuf0->rearm_data, rearm0);\n+\t\tvst1q_u64((uint64_t *)mbuf1->rearm_data, rearm1);\n+\t\tvst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);\n+\t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n+\n+\t\t/* Update that no more segments */\n+\t\tmbuf0->next = NULL;\n+\t\tmbuf1->next = NULL;\n+\t\tmbuf2->next = NULL;\n+\t\tmbuf3->next = NULL;\n+\n+\t\t/* Store the mbufs to rx_pkts */\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n+\n+\t\t/* Prefetch mbufs */\n+\t\troc_prefetch_store_keep(mbuf0);\n+\t\troc_prefetch_store_keep(mbuf1);\n+\t\troc_prefetch_store_keep(mbuf2);\n+\t\troc_prefetch_store_keep(mbuf3);\n+\n+\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t\t__mempool_check_cookies(mbuf0->pool, (void **)&mbuf0, 1, 1);\n+\t\t__mempool_check_cookies(mbuf1->pool, (void **)&mbuf1, 1, 1);\n+\t\t__mempool_check_cookies(mbuf2->pool, (void **)&mbuf2, 1, 1);\n+\t\t__mempool_check_cookies(mbuf3->pool, (void **)&mbuf3, 1, 1);\n+\n+\t\t/* Advance head pointer and packets */\n+\t\thead += NIX_DESCS_PER_LOOP;\n+\t\thead &= qmask;\n+\t\tpackets += NIX_DESCS_PER_LOOP;\n+\t}\n+\n+\trxq->head = head;\n+\trxq->available -= packets;\n+\n+\trte_io_wmb();\n+\t/* Free all the CQs that we've processed */\n+\tplt_write64((rxq->wdata | packets), rxq->cq_door);\n+\n+\tif (unlikely(pkts_left))\n+\t\tpackets += nix_recv_pkts(rx_queue, &rx_pkts[packets], pkts_left,\n+\t\t\t\t\t flags);\n+\n+\treturn packets;\n+}\n+\n+#else\n+\n+static inline uint16_t\n+nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n+\t\t const uint16_t flags)\n+{\n+\tRTE_SET_USED(rx_queue);\n+\tRTE_SET_USED(rx_pkts);\n+\tRTE_SET_USED(pkts);\n+\tRTE_SET_USED(flags);\n+\n+\treturn 0;\n+}\n+\n+#endif\n+\n #define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t \\\n \tstatic uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name( \\\n \t\tvoid *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \\\n@@ -97,6 +316,14 @@ nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,\n \t{ \\\n \t\treturn nix_recv_pkts(rx_queue, rx_pkts, pkts, \\\n \t\t\t\t (flags) | NIX_RX_MULTI_SEG_F); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tstatic uint16_t __rte_noinline __rte_hot \\\n+\t\tcn10k_nix_recv_pkts_vec_##name(void *rx_queue, \\\n+\t\t\t\t\t struct rte_mbuf **rx_pkts, \\\n+\t\t\t\t\t uint16_t pkts) \\\n+\t{ \\\n+\t\treturn nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, (flags)); \\\n \t}\n \n NIX_RX_FASTPATH_MODES\n@@ -137,7 +364,18 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n #undef R\n \t};\n \n-\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\tconst eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2] = {\n+#define R(name, f3, f2, f1, f0, flags)\t\t\t\t\t \\\n+\t[f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name,\n+\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tif (dev->scalar_ena)\n+\t\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\telse\n+\t\tpick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n \n \tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n \t\tpick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n", "prefixes": [ "19/44" ] }