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GET /api/patches/88572/?format=api
{ "id": 88572, "url": "http://patches.dpdk.org/api/patches/88572/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-46-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-46-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-46-ndabilpuram@marvell.com", "date": "2021-03-05T13:39:11", "name": "[45/52] common/cnxk: add base sso device support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9c2fa20dea0f63ab28abc4d4c262cc1ccdcc00ee", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-46-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88572/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88572/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E382CA0547;\n\tFri, 5 Mar 2021 14:47:39 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 278A322A47C;\n\tFri, 5 Mar 2021 14:41:49 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 2DDA622A477\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:41:47 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DdlEl008297 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:41:46 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 370p7p0dh4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:41:46 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:44 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:44 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:41:44 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 948EF3F703F;\n Fri, 5 Mar 2021 05:41:41 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=yEaguHtGOw9IQmVg1mm5dCbHAUFXHkFJqDBg6z5aRYI=;\n b=GPjiGCMDr7W3wePkjEhuuR/5Z5fk1925VqWlz7zLjjCs/5qGahvFuXlttz/a2Y8KwSV0\n 881oa8aRKxiIv/mPe4kZn0WS7z0ibgAVqmhrGK8QUJht0au13R7AlqYlZWZE5H0nyVVb\n rpJwX2XuKNz35gyYfFTIbGpzvGuOArEBhRB7Zrr4JcP9lHHgjZSabPoVdu9a+PIWk2fj\n yDFzYkdfQGgObwBO9NfNAEO2rvzFo/7FC3IFa6OOi+U2PI8yASlSwInKDROPfWOqyunC\n aRYEYRKnelFsg9Ggff/EhnMlpGCVsJm3hssHCaZj85K0MfxldXYUp+NHVwhfzbxfsErI Nw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Fri, 5 Mar 2021 19:09:11 +0530", "Message-ID": "<20210305133918.8005-46-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 45/52] common/cnxk: add base sso device support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd SSO device init and fini which attach SSO LF resources to the\nRVU PF/VF and SSO HWS and HWGRP LFs alloc, free.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_idev.c | 27 ++++\n drivers/common/cnxk/roc_idev_priv.h | 5 +\n drivers/common/cnxk/roc_nix.c | 1 +\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_sso.c | 273 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_sso.h | 34 +++++\n drivers/common/cnxk/roc_sso_priv.h | 33 +++++\n drivers/common/cnxk/roc_utils.c | 1 +\n drivers/common/cnxk/version.map | 5 +\n 13 files changed, 389 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_sso.c\n create mode 100644 drivers/common/cnxk/roc_sso.h\n create mode 100644 drivers/common/cnxk/roc_sso_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex ff7ca6f..ed2106e 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -40,5 +40,6 @@ sources = files('roc_dev.c',\n \t\t'roc_npc_parse.c',\n \t\t'roc_npc_utils.c',\n \t\t'roc_platform.c',\n+\t\t'roc_sso.c',\n \t\t'roc_utils.c')\n includes += include_directories('../../bus/pci')\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 44bed9a..acdc97e 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -88,6 +88,9 @@\n /* NIX */\n #include \"roc_nix.h\"\n \n+/* SSO */\n+#include \"roc_sso.h\"\n+\n /* Utils */\n #include \"roc_utils.h\"\n \ndiff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex e038956..e93b282 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -29,6 +29,7 @@ idev_get_cfg(void)\n void\n idev_set_defaults(struct idev_cfg *idev)\n {\n+\tidev->sso_pf_func = 0;\n \tidev->npa = NULL;\n \tidev->npa_pf_func = 0;\n \tidev->max_pools = 128;\n@@ -39,6 +40,32 @@ idev_set_defaults(struct idev_cfg *idev)\n }\n \n uint16_t\n+idev_sso_pffunc_get(void)\n+{\n+\tstruct idev_cfg *idev;\n+\tuint16_t sso_pf_func;\n+\n+\tidev = idev_get_cfg();\n+\tsso_pf_func = 0;\n+\tif (idev != NULL)\n+\t\tsso_pf_func = __atomic_load_n(&idev->sso_pf_func,\n+\t\t\t\t\t __ATOMIC_ACQUIRE);\n+\n+\treturn sso_pf_func;\n+}\n+\n+void\n+idev_sso_pffunc_set(uint16_t sso_pf_func)\n+{\n+\tstruct idev_cfg *idev;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev != NULL)\n+\t\t__atomic_store_n(&idev->sso_pf_func, sso_pf_func,\n+\t\t\t\t __ATOMIC_RELEASE);\n+}\n+\n+uint16_t\n idev_npa_pffunc_get(void)\n {\n \tstruct idev_cfg *idev;\ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex 535575a..579cdb1 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -8,6 +8,7 @@\n /* Intra device related functions */\n struct npa_lf;\n struct idev_cfg {\n+\tuint16_t sso_pf_func;\n \tuint16_t npa_pf_func;\n \tstruct npa_lf *npa;\n \tuint16_t npa_refcnt;\n@@ -28,6 +29,10 @@ uint32_t idev_npa_maxpools_get(void);\n void idev_npa_maxpools_set(uint32_t max_pools);\n uint16_t idev_npa_lf_active(struct dev *dev);\n \n+/* idev sso */\n+void idev_sso_pffunc_set(uint16_t sso_pf_func);\n+uint16_t idev_sso_pffunc_get(void);\n+\n /* idev lmt */\n uint16_t idev_lmt_pffunc_get(void);\n \ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 32ebd77..f7f7b2f 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -143,6 +143,7 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,\n \treq->rss_sz = nix->reta_sz;\n \treq->rss_grps = ROC_NIX_RSS_GRPS;\n \treq->npa_func = idev_npa_pffunc_get();\n+\treq->sso_func = idev_sso_pffunc_get();\n \treq->rx_cfg = rx_cfg;\n \n \tif (!roc_nix->rss_tag_as_xor)\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 11ff0f8..927bdca 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -33,4 +33,5 @@ RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex d585d53..16db7f0 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -129,6 +129,7 @@ extern int cnxk_logtype_mbox;\n extern int cnxk_logtype_npa;\n extern int cnxk_logtype_nix;\n extern int cnxk_logtype_npc;\n+extern int cnxk_logtype_sso;\n extern int cnxk_logtype_tm;\n \n #define plt_err(fmt, args...) \\\n@@ -150,6 +151,7 @@ extern int cnxk_logtype_tm;\n #define plt_npa_dbg(fmt, ...)\tplt_dbg(npa, fmt, ##__VA_ARGS__)\n #define plt_nix_dbg(fmt, ...)\tplt_dbg(nix, fmt, ##__VA_ARGS__)\n #define plt_npc_dbg(fmt, ...)\tplt_dbg(npc, fmt, ##__VA_ARGS__)\n+#define plt_sso_dbg(fmt, ...)\tplt_dbg(sso, fmt, ##__VA_ARGS__)\n #define plt_tm_dbg(fmt, ...)\tplt_dbg(tm, fmt, ##__VA_ARGS__)\n \n #ifdef __cplusplus\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex b1756fe..01e8f6b 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -26,4 +26,7 @@\n /* NPC */\n #include \"roc_npc_priv.h\"\n \n+/* SSO */\n+#include \"roc_sso_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nnew file mode 100644\nindex 0000000..caf399b\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -0,0 +1,273 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+/* Private functions. */\n+static int\n+sso_lf_alloc(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf,\n+\t void **rsp)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tint rc = -ENOSPC;\n+\n+\tswitch (lf_type) {\n+\tcase SSO_LF_TYPE_HWS: {\n+\t\tstruct ssow_lf_alloc_req *req;\n+\n+\t\treq = mbox_alloc_msg_ssow_lf_alloc(dev->mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->hws = nb_lf;\n+\t} break;\n+\tcase SSO_LF_TYPE_HWGRP: {\n+\t\tstruct sso_lf_alloc_req *req;\n+\n+\t\treq = mbox_alloc_msg_sso_lf_alloc(dev->mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->hwgrps = nb_lf;\n+\t} break;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\trc = mbox_process_msg(dev->mbox, rsp);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\treturn 0;\n+}\n+\n+static int\n+sso_lf_free(struct roc_sso *roc_sso, enum sso_lf_type lf_type, uint16_t nb_lf)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tint rc = -ENOSPC;\n+\n+\tswitch (lf_type) {\n+\tcase SSO_LF_TYPE_HWS: {\n+\t\tstruct ssow_lf_free_req *req;\n+\n+\t\treq = mbox_alloc_msg_ssow_lf_free(dev->mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->hws = nb_lf;\n+\t} break;\n+\tcase SSO_LF_TYPE_HWGRP: {\n+\t\tstruct sso_lf_free_req *req;\n+\n+\t\treq = mbox_alloc_msg_sso_lf_free(dev->mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->hwgrps = nb_lf;\n+\t} break;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\treturn 0;\n+}\n+\n+static int\n+sso_rsrc_attach(struct roc_sso *roc_sso, enum sso_lf_type lf_type,\n+\t\tuint16_t nb_lf)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct rsrc_attach_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_attach_resources(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\tswitch (lf_type) {\n+\tcase SSO_LF_TYPE_HWS:\n+\t\treq->ssow = nb_lf;\n+\t\tbreak;\n+\tcase SSO_LF_TYPE_HWGRP:\n+\t\treq->sso = nb_lf;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn SSO_ERR_PARAM;\n+\t}\n+\n+\treq->modify = true;\n+\tif (mbox_process(dev->mbox) < 0)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+static int\n+sso_rsrc_detach(struct roc_sso *roc_sso, enum sso_lf_type lf_type)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct rsrc_detach_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_detach_resources(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\tswitch (lf_type) {\n+\tcase SSO_LF_TYPE_HWS:\n+\t\treq->ssow = true;\n+\t\tbreak;\n+\tcase SSO_LF_TYPE_HWGRP:\n+\t\treq->sso = true;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn SSO_ERR_PARAM;\n+\t}\n+\n+\treq->partial = true;\n+\tif (mbox_process(dev->mbox) < 0)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+static int\n+sso_rsrc_get(struct roc_sso *roc_sso)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct free_rsrcs_rsp *rsrc_cnt;\n+\tint rc;\n+\n+\tmbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n+\trc = mbox_process_msg(dev->mbox, (void **)&rsrc_cnt);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to get free resource count\\n\");\n+\t\treturn rc;\n+\t}\n+\n+\troc_sso->max_hwgrp = rsrc_cnt->sso;\n+\troc_sso->max_hws = rsrc_cnt->ssow;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n+{\n+\tstruct sso_lf_alloc_rsp *rsp_hwgrp;\n+\tint rc;\n+\n+\tif (roc_sso->max_hwgrp < nb_hwgrp)\n+\t\treturn -ENOENT;\n+\tif (roc_sso->max_hws < nb_hws)\n+\t\treturn -ENOENT;\n+\n+\trc = sso_rsrc_attach(roc_sso, SSO_LF_TYPE_HWS, nb_hws);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to attach SSO HWS LFs\");\n+\t\treturn rc;\n+\t}\n+\n+\trc = sso_rsrc_attach(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to attach SSO HWGRP LFs\");\n+\t\tgoto hwgrp_atch_fail;\n+\t}\n+\n+\trc = sso_lf_alloc(roc_sso, SSO_LF_TYPE_HWS, nb_hws, NULL);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to alloc SSO HWS LFs\");\n+\t\tgoto hws_alloc_fail;\n+\t}\n+\n+\trc = sso_lf_alloc(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp,\n+\t\t\t (void **)&rsp_hwgrp);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to alloc SSO HWGRP Lfs\");\n+\t\tgoto hwgrp_alloc_fail;\n+\t}\n+\n+\troc_sso->xaq_buf_size = rsp_hwgrp->xaq_buf_size;\n+\troc_sso->xae_waes = rsp_hwgrp->xaq_wq_entries;\n+\troc_sso->iue = rsp_hwgrp->in_unit_entries;\n+\n+\troc_sso->nb_hwgrp = nb_hwgrp;\n+\troc_sso->nb_hws = nb_hws;\n+\n+\treturn 0;\n+hwgrp_alloc_fail:\n+\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWS, nb_hws);\n+hws_alloc_fail:\n+\tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWGRP);\n+hwgrp_atch_fail:\n+\tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWS);\n+\treturn rc;\n+}\n+\n+void\n+roc_sso_rsrc_fini(struct roc_sso *roc_sso)\n+{\n+\tif (!roc_sso->nb_hws && !roc_sso->nb_hwgrp)\n+\t\treturn;\n+\n+\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWS, roc_sso->nb_hws);\n+\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWGRP, roc_sso->nb_hwgrp);\n+\n+\tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWS);\n+\tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWGRP);\n+\n+\troc_sso->nb_hwgrp = 0;\n+\troc_sso->nb_hws = 0;\n+}\n+\n+int\n+roc_sso_dev_init(struct roc_sso *roc_sso)\n+{\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct sso *sso;\n+\tint rc;\n+\n+\tif (roc_sso == NULL || roc_sso->pci_dev == NULL)\n+\t\treturn SSO_ERR_PARAM;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct sso) <= ROC_SSO_MEM_SZ);\n+\tsso = roc_sso_to_sso_priv(roc_sso);\n+\tmemset(sso, 0, sizeof(*sso));\n+\tpci_dev = roc_sso->pci_dev;\n+\n+\trc = dev_init(&sso->dev, pci_dev);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to init roc device\");\n+\t\tgoto fail;\n+\t}\n+\n+\trc = sso_rsrc_get(roc_sso);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to get SSO resources\");\n+\t\tgoto rsrc_fail;\n+\t}\n+\trc = -ENOMEM;\n+\n+\tidev_sso_pffunc_set(sso->dev.pf_func);\n+\tsso->pci_dev = pci_dev;\n+\tsso->dev.drv_inited = true;\n+\troc_sso->lmt_base = sso->dev.lmt_base;\n+\n+\treturn 0;\n+rsrc_fail:\n+\trc |= dev_fini(&sso->dev, pci_dev);\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_sso_dev_fini(struct roc_sso *roc_sso)\n+{\n+\tstruct sso *sso;\n+\n+\tsso = roc_sso_to_sso_priv(roc_sso);\n+\tsso->dev.drv_inited = false;\n+\n+\treturn dev_fini(&sso->dev, sso->pci_dev);\n+}\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nnew file mode 100644\nindex 0000000..007ad41\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -0,0 +1,34 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_SSO_H_\n+#define _ROC_SSO_H_\n+\n+struct roc_sso {\n+\tstruct plt_pci_device *pci_dev;\n+\t/* Public data. */\n+\tuint16_t max_hwgrp;\n+\tuint16_t max_hws;\n+\tuint16_t nb_hwgrp;\n+\tuint8_t nb_hws;\n+\tuintptr_t lmt_base;\n+\t/* HW Const. */\n+\tuint32_t xae_waes;\n+\tuint32_t xaq_buf_size;\n+\tuint32_t iue;\n+\t/* Private data. */\n+#define ROC_SSO_MEM_SZ (16 * 1024)\n+\tuint8_t reserved[ROC_SSO_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+/* SSO device initialization */\n+int __roc_api roc_sso_dev_init(struct roc_sso *roc_sso);\n+int __roc_api roc_sso_dev_fini(struct roc_sso *roc_sso);\n+\n+/* SSO device configuration */\n+int __roc_api roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws,\n+\t\t\t\tuint16_t nb_hwgrp);\n+void __roc_api roc_sso_rsrc_fini(struct roc_sso *roc_sso);\n+\n+#endif /* _ROC_SSOW_H_ */\ndiff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h\nnew file mode 100644\nindex 0000000..d629b97\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_sso_priv.h\n@@ -0,0 +1,33 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_SSO_PRIV_H_\n+#define _ROC_SSO_PRIV_H_\n+\n+struct sso_rsrc {\n+\tuint16_t rsrc_id;\n+\tuint64_t base;\n+};\n+\n+struct sso {\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct dev dev;\n+} __plt_cache_aligned;\n+\n+enum sso_err_status {\n+\tSSO_ERR_PARAM = -4096,\n+};\n+\n+enum sso_lf_type {\n+\tSSO_LF_TYPE_HWS,\n+\tSSO_LF_TYPE_HWGRP,\n+};\n+\n+static inline struct sso *\n+roc_sso_to_sso_priv(struct roc_sso *roc_sso)\n+{\n+\treturn (struct sso *)&roc_sso->reserved[0];\n+}\n+\n+#endif /* _ROC_SSO_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex c5c5962..b699aa1 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -15,6 +15,7 @@ roc_error_msg_get(int errorcode)\n \tcase NIX_ERR_PARAM:\n \tcase NPA_ERR_PARAM:\n \tcase NPC_ERR_PARAM:\n+\tcase SSO_ERR_PARAM:\n \tcase UTIL_ERR_PARAM:\n \t\terr_msg = \"Invalid parameter\";\n \t\tbreak;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 749156e..5385b36 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -6,6 +6,7 @@ INTERNAL {\n \tcnxk_logtype_nix;\n \tcnxk_logtype_npa;\n \tcnxk_logtype_npc;\n+\tcnxk_logtype_sso;\n \tcnxk_logtype_tm;\n \tplt_init;\n \troc_clk_freq_get;\n@@ -171,6 +172,10 @@ INTERNAL {\n \troc_npc_mcam_write_entry;\n \troc_npc_mcam_read_counter;\n \troc_npc_profile_name_get;\n+\troc_sso_dev_fini;\n+\troc_sso_dev_init;\n+\troc_sso_rsrc_fini;\n+\troc_sso_rsrc_init;\n \n \tlocal: *;\n };\n", "prefixes": [ "45/52" ] }