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GET /api/patches/88567/?format=api
{ "id": 88567, "url": "http://patches.dpdk.org/api/patches/88567/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-41-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-41-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-41-ndabilpuram@marvell.com", "date": "2021-03-05T13:39:06", "name": "[40/52] common/cnxk: add npc support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "54d8d42a434af9998240a4173b8b669c1dee1dcd", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-41-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88567/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88567/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 827E1A0547;\n\tFri, 5 Mar 2021 14:46:50 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4040D22A458;\n\tFri, 5 Mar 2021 14:41:33 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id F11D622A433\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:41:31 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DevhQ001889 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:41:31 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrr9-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:41:31 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:29 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:41:29 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 1F6753F7040;\n Fri, 5 Mar 2021 05:41:26 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=Mkse9tPyYZ+5bFpkPm5uuz5hu7r3hTy8lLFiYnTqse8=;\n b=LAihFFVGQD8hjIOjHpMstR84PiGw1Lr0II3uLRj5BhX/+ZKA9X5BUq6sxPKCn2IS4Myf\n tMPYV55ybryodCiKg1917TuNSZwgv/O4Kly9jzbRFbuCw6kXOvAWQ/nuEfiYFY0VAktk\n xJY4lNeT7Hw5T2TgZut5uNSTppFGt/ZJaT8CTHYpkGEGNVCUYdqR35XH+METCb/pTnU6\n VjEuAku9HRLjNrOfZSpbttEEq8bd8V1Ts3h+Cp9zc+FQsLEVLukh65HRVa+Gh6jT7t1h\n icBL+9Xdo1fKe3LbjC0pBj15wPdDJfsTAqBBSBFOzmEwQNEa5yPowLBrhIJSv448Pv1P jQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Fri, 5 Mar 2021 19:09:06 +0530", "Message-ID": "<20210305133918.8005-41-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 40/52] common/cnxk: add npc support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdding initial npc support.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_npc.h | 129 +++++++++++++\n drivers/common/cnxk/roc_npc_priv.h | 381 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_utils.c | 24 +++\n drivers/common/cnxk/version.map | 1 +\n 8 files changed, 544 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_npc.h\n create mode 100644 drivers/common/cnxk/roc_npc_priv.h", "diff": "diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex b805425..44bed9a 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -82,6 +82,9 @@\n /* NPA */\n #include \"roc_npa.h\"\n \n+/* NPC */\n+#include \"roc_npc.h\"\n+\n /* NIX */\n #include \"roc_nix.h\"\n \ndiff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h\nnew file mode 100644\nindex 0000000..f273976\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_npc.h\n@@ -0,0 +1,129 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_NPC_H_\n+#define _ROC_NPC_H_\n+\n+#include <sys/queue.h>\n+\n+enum roc_npc_item_type {\n+\tROC_NPC_ITEM_TYPE_VOID,\n+\tROC_NPC_ITEM_TYPE_ANY,\n+\tROC_NPC_ITEM_TYPE_ETH,\n+\tROC_NPC_ITEM_TYPE_VLAN,\n+\tROC_NPC_ITEM_TYPE_E_TAG,\n+\tROC_NPC_ITEM_TYPE_IPV4,\n+\tROC_NPC_ITEM_TYPE_IPV6,\n+\tROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,\n+\tROC_NPC_ITEM_TYPE_MPLS,\n+\tROC_NPC_ITEM_TYPE_ICMP,\n+\tROC_NPC_ITEM_TYPE_IGMP,\n+\tROC_NPC_ITEM_TYPE_UDP,\n+\tROC_NPC_ITEM_TYPE_TCP,\n+\tROC_NPC_ITEM_TYPE_SCTP,\n+\tROC_NPC_ITEM_TYPE_ESP,\n+\tROC_NPC_ITEM_TYPE_GRE,\n+\tROC_NPC_ITEM_TYPE_NVGRE,\n+\tROC_NPC_ITEM_TYPE_VXLAN,\n+\tROC_NPC_ITEM_TYPE_GTPC,\n+\tROC_NPC_ITEM_TYPE_GTPU,\n+\tROC_NPC_ITEM_TYPE_GENEVE,\n+\tROC_NPC_ITEM_TYPE_VXLAN_GPE,\n+\tROC_NPC_ITEM_TYPE_IPV6_EXT,\n+\tROC_NPC_ITEM_TYPE_GRE_KEY,\n+\tROC_NPC_ITEM_TYPE_HIGIG2,\n+\tROC_NPC_ITEM_TYPE_CPT_HDR,\n+\tROC_NPC_ITEM_TYPE_L3_CUSTOM,\n+\tROC_NPC_ITEM_TYPE_QINQ,\n+\tROC_NPC_ITEM_TYPE_END,\n+};\n+\n+struct roc_npc_item_info {\n+\tenum roc_npc_item_type type; /* Item type */\n+\tuint32_t size;\t\t /* item size */\n+\tconst void *spec; /**< Pointer to item specification structure. */\n+\tconst void *mask; /**< Bit-mask applied to spec and last. */\n+\tconst void *last; /* For range */\n+};\n+\n+#define ROC_NPC_MAX_ACTION_COUNT 12\n+\n+enum roc_npc_action_type {\n+\tROC_NPC_ACTION_TYPE_END = (1 << 0),\n+\tROC_NPC_ACTION_TYPE_VOID = (1 << 1),\n+\tROC_NPC_ACTION_TYPE_MARK = (1 << 2),\n+\tROC_NPC_ACTION_TYPE_FLAG = (1 << 3),\n+\tROC_NPC_ACTION_TYPE_DROP = (1 << 4),\n+\tROC_NPC_ACTION_TYPE_QUEUE = (1 << 5),\n+\tROC_NPC_ACTION_TYPE_RSS = (1 << 6),\n+\tROC_NPC_ACTION_TYPE_DUP = (1 << 7),\n+\tROC_NPC_ACTION_TYPE_SEC = (1 << 8),\n+\tROC_NPC_ACTION_TYPE_COUNT = (1 << 9),\n+\tROC_NPC_ACTION_TYPE_PF = (1 << 10),\n+\tROC_NPC_ACTION_TYPE_VF = (1 << 11),\n+};\n+\n+struct roc_npc_action {\n+\tenum roc_npc_action_type type; /**< Action type. */\n+\tconst void *conf; /**< Pointer to action configuration object. */\n+};\n+\n+struct roc_npc_action_mark {\n+\tuint32_t id; /**< Integer value to return with packets. */\n+};\n+\n+struct roc_npc_action_vf {\n+\tuint32_t original : 1;\t/**< Use original VF ID if possible. */\n+\tuint32_t reserved : 31; /**< Reserved, must be zero. */\n+\tuint32_t id;\t\t/**< VF ID. */\n+};\n+\n+struct roc_npc_action_queue {\n+\tuint16_t index; /**< Queue index to use. */\n+};\n+\n+struct roc_npc_attr {\n+\tuint32_t priority;\t/**< Rule priority level within group. */\n+\tuint32_t ingress : 1;\t/**< Rule applies to ingress traffic. */\n+\tuint32_t egress : 1;\t/**< Rule applies to egress traffic. */\n+\tuint32_t reserved : 30; /**< Reserved, must be zero. */\n+};\n+\n+struct roc_npc_flow {\n+\tuint8_t nix_intf;\n+\tuint8_t enable;\n+\tuint32_t mcam_id;\n+\tint32_t ctr_id;\n+\tuint32_t priority;\n+#define ROC_NPC_MAX_MCAM_WIDTH_DWORDS 7\n+\t/* Contiguous match string */\n+\tuint64_t mcam_data[ROC_NPC_MAX_MCAM_WIDTH_DWORDS];\n+\tuint64_t mcam_mask[ROC_NPC_MAX_MCAM_WIDTH_DWORDS];\n+\tuint64_t npc_action;\n+\tuint64_t vtag_action;\n+\n+\tTAILQ_ENTRY(roc_npc_flow) next;\n+};\n+\n+enum roc_npc_intf {\n+\tROC_NPC_INTF_RX = 0,\n+\tROC_NPC_INTF_TX = 1,\n+\tROC_NPC_INTF_MAX = 2,\n+};\n+\n+struct roc_npc {\n+\tstruct roc_nix *roc_nix;\n+\tuint8_t switch_header_type;\n+\tuint16_t flow_prealloc_size;\n+\tuint16_t flow_max_priority;\n+\tuint16_t channel;\n+\tuint16_t pf_func;\n+\tuint64_t kex_capability;\n+\tuint64_t rx_parse_nibble;\n+\n+#define ROC_NPC_MEM_SZ (5 * 1024)\n+\tuint8_t reserved[ROC_NPC_MEM_SZ];\n+} __plt_cache_aligned;\n+\n+#endif /* _ROC_NPC_H_ */\ndiff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h\nnew file mode 100644\nindex 0000000..0c3947a\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_npc_priv.h\n@@ -0,0 +1,381 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_NPC_PRIV_H_\n+#define _ROC_NPC_PRIV_H_\n+\n+#define NPC_IH_LENGTH\t 8\n+#define NPC_TPID_LENGTH\t 2\n+#define NPC_HIGIG2_LENGTH 16\n+#define NPC_COUNTER_NONE (-1)\n+\n+#define NPC_RSS_GRPS 8\n+\n+#define NPC_ACTION_FLAG_DEFAULT 0xffff\n+\n+#define NPC_PFVF_FUNC_MASK 0x3FF\n+\n+/* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */\n+#define NPC_MAX_EXTRACT_DATA_LEN (64)\n+#define NPC_MAX_EXTRACT_HW_LEN\t (4 * NPC_MAX_EXTRACT_DATA_LEN)\n+#define NPC_LDATA_LFLAG_LEN\t (16)\n+#define NPC_MAX_KEY_NIBBLES\t (31)\n+\n+/* Nibble offsets */\n+#define NPC_LAYER_KEYX_SZ\t (3)\n+#define NPC_PARSE_KEX_S_LA_OFFSET (7)\n+#define NPC_PARSE_KEX_S_LID_OFFSET(lid) \\\n+\t((((lid) - (NPC_LID_LA)) * NPC_LAYER_KEYX_SZ) + \\\n+\t NPC_PARSE_KEX_S_LA_OFFSET)\n+\n+/* This mark value indicates flag action */\n+#define NPC_FLOW_FLAG_VAL (0xffff)\n+\n+#define NPC_RX_ACT_MATCH_OFFSET (40)\n+#define NPC_RX_ACT_MATCH_MASK\t(0xFFFF)\n+\n+#define NPC_RSS_ACT_GRP_OFFSET (20)\n+#define NPC_RSS_ACT_ALG_OFFSET (56)\n+#define NPC_RSS_ACT_GRP_MASK (0xFFFFF)\n+#define NPC_RSS_ACT_ALG_MASK (0x1F)\n+\n+#define NPC_MCAM_KEX_FIELD_MAX\t 23\n+#define NPC_MCAM_MAX_PROTO_FIELDS (NPC_MCAM_KEX_FIELD_MAX + 1)\n+#define NPC_MCAM_KEY_X4_WORDS\t 7 /* Number of 64-bit words */\n+\n+#define NPC_RVUPF_MAX_9XXX 0x10 /* HRM: RVU_PRIV_CONST */\n+#define NPC_RVUPF_MAX_10XX 0x20 /* HRM: RVU_PRIV_CONST */\n+#define NPC_NIXLF_MAX\t 0x80 /* HRM: NIX_AF_CONST2 */\n+#define NPC_MCAME_PER_PF 2\t/* DRV: RSVD_MCAM_ENTRIES_PER_PF */\n+#define NPC_MCAME_PER_LF 1\t/* DRV: RSVD_MCAM_ENTRIES_PER_NIXLF */\n+#define NPC_MCAME_RESVD_9XXX \\\n+\t(NPC_NIXLF_MAX * NPC_MCAME_PER_LF + \\\n+\t (NPC_RVUPF_MAX_9XXX - 1) * NPC_MCAME_PER_PF)\n+\n+#define NPC_MCAME_RESVD_10XX \\\n+\t(NPC_NIXLF_MAX * NPC_MCAME_PER_LF + \\\n+\t (NPC_RVUPF_MAX_10XX - 1) * NPC_MCAME_PER_PF)\n+\n+enum npc_err_status {\n+\tNPC_ERR_PARAM = -1024,\n+\tNPC_ERR_NO_MEM,\n+\tNPC_ERR_INVALID_SPEC,\n+\tNPC_ERR_INVALID_MASK,\n+\tNPC_ERR_INVALID_RANGE,\n+\tNPC_ERR_INVALID_KEX,\n+\tNPC_ERR_INVALID_SIZE,\n+\tNPC_ERR_INTERNAL,\n+\tNPC_ERR_MCAM_ALLOC,\n+\tNPC_ERR_ACTION_NOTSUP,\n+\tNPC_ERR_PATTERN_NOTSUP,\n+};\n+\n+enum npc_mcam_intf { NPC_MCAM_RX, NPC_MCAM_TX };\n+\n+typedef union npc_kex_cap_terms_t {\n+\tstruct {\n+\t\t/** Total length of received packet */\n+\t\tuint64_t len : 1;\n+\t\t/** Initial (outer) Ethertype only */\n+\t\tuint64_t ethtype_0 : 1;\n+\t\t/** Ethertype of most inner VLAN tag */\n+\t\tuint64_t ethtype_x : 1;\n+\t\t/** First VLAN ID (outer) */\n+\t\tuint64_t vlan_id_0 : 1;\n+\t\t/** Last VLAN ID (inner) */\n+\t\tuint64_t vlan_id_x : 1;\n+\t\t/** destination MAC address */\n+\t\tuint64_t dmac : 1;\n+\t\t/** IP Protocol or IPv6 Next Header */\n+\t\tuint64_t ip_proto : 1;\n+\t\t/** Destination UDP port, implies IPPROTO=17 */\n+\t\tuint64_t udp_dport : 1;\n+\t\t/** Destination TCP port implies IPPROTO=6 */\n+\t\tuint64_t tcp_dport : 1;\n+\t\t/** Source UDP Port */\n+\t\tuint64_t udp_sport : 1;\n+\t\t/** Source TCP port */\n+\t\tuint64_t tcp_sport : 1;\n+\t\t/** Source IP address */\n+\t\tuint64_t sip_addr : 1;\n+\t\t/** Destination IP address */\n+\t\tuint64_t dip_addr : 1;\n+\t\t/** Source IP address */\n+\t\tuint64_t sip6_addr : 1;\n+\t\t/** Destination IP address */\n+\t\tuint64_t dip6_addr : 1;\n+\t\t/** IPsec session identifier */\n+\t\tuint64_t ipsec_spi : 1;\n+\t\t/** NVGRE/VXLAN network identifier */\n+\t\tuint64_t ld_vni : 1;\n+\t\t/** Custom frame match rule. PMR offset is counted from\n+\t\t * the start of the packet.\n+\t\t */\n+\t\tuint64_t custom_frame : 1;\n+\t\t/** Custom layer 3 match rule. PMR offset is counted from\n+\t\t * the start of layer 3 in the packet.\n+\t\t */\n+\t\tuint64_t custom_l3 : 1;\n+\t\t/** IGMP Group address */\n+\t\tuint64_t igmp_grp_addr : 1;\n+\t\t/** ICMP identifier */\n+\t\tuint64_t icmp_id : 1;\n+\t\t/** ICMP type */\n+\t\tuint64_t icmp_type : 1;\n+\t\t/** ICMP code */\n+\t\tuint64_t icmp_code : 1;\n+\t\t/** Source SCTP port */\n+\t\tuint64_t sctp_sport : 1;\n+\t\t/** Destination SCTP port */\n+\t\tuint64_t sctp_dport : 1;\n+\t\t/** GTPU Tunnel endpoint identifier */\n+\t\tuint64_t gtpu_teid : 1;\n+\n+\t} bit;\n+\t/** All bits of the bit field structure */\n+\tuint64_t all_bits;\n+} npc_kex_cap_terms_t;\n+\n+struct npc_parse_item_info {\n+\tconst void *def_mask; /* default mask */\n+\tvoid *hw_mask;\t /* hardware supported mask */\n+\tint len;\t /* length of item */\n+\tconst void *spec; /* spec to use, NULL implies match any */\n+\tconst void *mask; /* mask to use */\n+\tuint8_t hw_hdr_len; /* Extra data len at each layer*/\n+};\n+\n+struct npc_parse_state {\n+\tstruct npc *npc;\n+\tconst struct roc_npc_item_info *pattern;\n+\tconst struct roc_npc_item_info *last_pattern;\n+\tstruct roc_npc_flow *flow;\n+\tuint8_t nix_intf;\n+\tuint8_t tunnel;\n+\tuint8_t terminate;\n+\tuint8_t layer_mask;\n+\tuint8_t lt[NPC_MAX_LID];\n+\tuint8_t flags[NPC_MAX_LID];\n+\tuint8_t *mcam_data; /* point to flow->mcam_data + key_len */\n+\tuint8_t *mcam_mask; /* point to flow->mcam_mask + key_len */\n+\tbool is_vf;\n+};\n+\n+enum npc_kpu_parser_flag {\n+\tNPC_F_NA = 0,\n+\tNPC_F_PKI,\n+\tNPC_F_PKI_VLAN,\n+\tNPC_F_PKI_ETAG,\n+\tNPC_F_PKI_ITAG,\n+\tNPC_F_PKI_MPLS,\n+\tNPC_F_PKI_NSH,\n+\tNPC_F_ETYPE_UNK,\n+\tNPC_F_ETHER_VLAN,\n+\tNPC_F_ETHER_ETAG,\n+\tNPC_F_ETHER_ITAG,\n+\tNPC_F_ETHER_MPLS,\n+\tNPC_F_ETHER_NSH,\n+\tNPC_F_STAG_CTAG,\n+\tNPC_F_STAG_CTAG_UNK,\n+\tNPC_F_STAG_STAG_CTAG,\n+\tNPC_F_STAG_STAG_STAG,\n+\tNPC_F_QINQ_CTAG,\n+\tNPC_F_QINQ_CTAG_UNK,\n+\tNPC_F_QINQ_QINQ_CTAG,\n+\tNPC_F_QINQ_QINQ_QINQ,\n+\tNPC_F_BTAG_ITAG,\n+\tNPC_F_BTAG_ITAG_STAG,\n+\tNPC_F_BTAG_ITAG_CTAG,\n+\tNPC_F_BTAG_ITAG_UNK,\n+\tNPC_F_ETAG_CTAG,\n+\tNPC_F_ETAG_BTAG_ITAG,\n+\tNPC_F_ETAG_STAG,\n+\tNPC_F_ETAG_QINQ,\n+\tNPC_F_ETAG_ITAG,\n+\tNPC_F_ETAG_ITAG_STAG,\n+\tNPC_F_ETAG_ITAG_CTAG,\n+\tNPC_F_ETAG_ITAG_UNK,\n+\tNPC_F_ITAG_STAG_CTAG,\n+\tNPC_F_ITAG_STAG,\n+\tNPC_F_ITAG_CTAG,\n+\tNPC_F_MPLS_4_LABELS,\n+\tNPC_F_MPLS_3_LABELS,\n+\tNPC_F_MPLS_2_LABELS,\n+\tNPC_F_IP_HAS_OPTIONS,\n+\tNPC_F_IP_IP_IN_IP,\n+\tNPC_F_IP_6TO4,\n+\tNPC_F_IP_MPLS_IN_IP,\n+\tNPC_F_IP_UNK_PROTO,\n+\tNPC_F_IP_IP_IN_IP_HAS_OPTIONS,\n+\tNPC_F_IP_6TO4_HAS_OPTIONS,\n+\tNPC_F_IP_MPLS_IN_IP_HAS_OPTIONS,\n+\tNPC_F_IP_UNK_PROTO_HAS_OPTIONS,\n+\tNPC_F_IP6_HAS_EXT,\n+\tNPC_F_IP6_TUN_IP6,\n+\tNPC_F_IP6_MPLS_IN_IP,\n+\tNPC_F_TCP_HAS_OPTIONS,\n+\tNPC_F_TCP_HTTP,\n+\tNPC_F_TCP_HTTPS,\n+\tNPC_F_TCP_PPTP,\n+\tNPC_F_TCP_UNK_PORT,\n+\tNPC_F_TCP_HTTP_HAS_OPTIONS,\n+\tNPC_F_TCP_HTTPS_HAS_OPTIONS,\n+\tNPC_F_TCP_PPTP_HAS_OPTIONS,\n+\tNPC_F_TCP_UNK_PORT_HAS_OPTIONS,\n+\tNPC_F_UDP_VXLAN,\n+\tNPC_F_UDP_VXLAN_NOVNI,\n+\tNPC_F_UDP_VXLAN_NOVNI_NSH,\n+\tNPC_F_UDP_VXLANGPE,\n+\tNPC_F_UDP_VXLANGPE_NSH,\n+\tNPC_F_UDP_VXLANGPE_MPLS,\n+\tNPC_F_UDP_VXLANGPE_NOVNI,\n+\tNPC_F_UDP_VXLANGPE_NOVNI_NSH,\n+\tNPC_F_UDP_VXLANGPE_NOVNI_MPLS,\n+\tNPC_F_UDP_VXLANGPE_UNK,\n+\tNPC_F_UDP_VXLANGPE_NONP,\n+\tNPC_F_UDP_GTP_GTPC,\n+\tNPC_F_UDP_GTP_GTPU_G_PDU,\n+\tNPC_F_UDP_GTP_GTPU_UNK,\n+\tNPC_F_UDP_UNK_PORT,\n+\tNPC_F_UDP_GENEVE,\n+\tNPC_F_UDP_GENEVE_OAM,\n+\tNPC_F_UDP_GENEVE_CRI_OPT,\n+\tNPC_F_UDP_GENEVE_OAM_CRI_OPT,\n+\tNPC_F_GRE_NVGRE,\n+\tNPC_F_GRE_HAS_SRE,\n+\tNPC_F_GRE_HAS_CSUM,\n+\tNPC_F_GRE_HAS_KEY,\n+\tNPC_F_GRE_HAS_SEQ,\n+\tNPC_F_GRE_HAS_CSUM_KEY,\n+\tNPC_F_GRE_HAS_CSUM_SEQ,\n+\tNPC_F_GRE_HAS_KEY_SEQ,\n+\tNPC_F_GRE_HAS_CSUM_KEY_SEQ,\n+\tNPC_F_GRE_HAS_ROUTE,\n+\tNPC_F_GRE_UNK_PROTO,\n+\tNPC_F_GRE_VER1,\n+\tNPC_F_GRE_VER1_HAS_SEQ,\n+\tNPC_F_GRE_VER1_HAS_ACK,\n+\tNPC_F_GRE_VER1_HAS_SEQ_ACK,\n+\tNPC_F_GRE_VER1_UNK_PROTO,\n+\tNPC_F_TU_ETHER_UNK,\n+\tNPC_F_TU_ETHER_CTAG,\n+\tNPC_F_TU_ETHER_CTAG_UNK,\n+\tNPC_F_TU_ETHER_STAG_CTAG,\n+\tNPC_F_TU_ETHER_STAG_CTAG_UNK,\n+\tNPC_F_TU_ETHER_STAG,\n+\tNPC_F_TU_ETHER_STAG_UNK,\n+\tNPC_F_TU_ETHER_QINQ_CTAG,\n+\tNPC_F_TU_ETHER_QINQ_CTAG_UNK,\n+\tNPC_F_TU_ETHER_QINQ,\n+\tNPC_F_TU_ETHER_QINQ_UNK,\n+\tNPC_F_LAST /* has to be the last item */\n+};\n+\n+#define NPC_ACTION_TERM \\\n+\t(ROC_NPC_ACTION_TYPE_DROP | ROC_NPC_ACTION_TYPE_QUEUE | \\\n+\t ROC_NPC_ACTION_TYPE_RSS | ROC_NPC_ACTION_TYPE_DUP | \\\n+\t ROC_NPC_ACTION_TYPE_SEC)\n+\n+struct npc_xtract_info {\n+\t/* Length in bytes of pkt data extracted. len = 0\n+\t * indicates that extraction is disabled.\n+\t */\n+\tuint8_t len;\n+\tuint8_t hdr_off; /* Byte offset of proto hdr: extract_src */\n+\tuint8_t key_off; /* Byte offset in MCAM key where data is placed */\n+\tuint8_t enable;\t /* Extraction enabled or disabled */\n+\tuint8_t flags_enable; /* Flags extraction enabled */\n+};\n+\n+/* Information for a given {LAYER, LTYPE} */\n+struct npc_lid_lt_xtract_info {\n+\t/* Info derived from parser configuration */\n+\tuint16_t npc_proto;\t /* Network protocol identified */\n+\tuint8_t valid_flags_mask; /* Flags applicable */\n+\tuint8_t is_terminating : 1; /* No more parsing */\n+\tstruct npc_xtract_info xtract[NPC_MAX_LD];\n+};\n+\n+union npc_kex_ldata_flags_cfg {\n+\tstruct {\n+\t\tuint64_t lid : 3;\n+\t\tuint64_t rvsd_62_1 : 61;\n+\t} s;\n+\n+\tuint64_t i;\n+};\n+\n+typedef struct npc_lid_lt_xtract_info npc_dxcfg_t[NPC_MAX_INTF][NPC_MAX_LID]\n+\t\t\t\t\t\t [NPC_MAX_LT];\n+typedef struct npc_lid_lt_xtract_info npc_fxcfg_t[NPC_MAX_INTF][NPC_MAX_LD]\n+\t\t\t\t\t\t [NPC_MAX_LFL];\n+typedef union npc_kex_ldata_flags_cfg npc_ld_flags_t[NPC_MAX_LD];\n+\n+/* MBOX_MSG_NPC_GET_DATAX_CFG Response */\n+struct npc_get_datax_cfg {\n+\t/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */\n+\tunion npc_kex_ldata_flags_cfg ld_flags[NPC_MAX_LD];\n+\t/* Extract information indexed with [LID][LTYPE] */\n+\tstruct npc_lid_lt_xtract_info lid_lt_xtract[NPC_MAX_LID][NPC_MAX_LT];\n+\t/* Flags based extract indexed with [LDATA][FLAGS_LOWER_NIBBLE]\n+\t * Fields flags_ena_ld0, flags_ena_ld1 in\n+\t * struct npc_lid_lt_xtract_info indicate if this is applicable\n+\t * for a given {LAYER, LTYPE}\n+\t */\n+\tstruct npc_xtract_info flag_xtract[NPC_MAX_LD][NPC_MAX_LT];\n+};\n+\n+TAILQ_HEAD(npc_flow_list, roc_npc_flow);\n+\n+struct npc_mcam_ents_info {\n+\t/* Current max & min values of mcam index */\n+\tuint32_t max_id;\n+\tuint32_t min_id;\n+\tuint32_t free_ent;\n+\tuint32_t live_ent;\n+};\n+\n+struct npc {\n+\tstruct mbox *mbox;\t\t\t/* Mbox */\n+\tuint32_t keyx_supp_nmask[NPC_MAX_INTF]; /* nibble mask */\n+\tuint8_t profile_name[MKEX_NAME_LEN];\t/* KEX profile name */\n+\tuint32_t keyx_len[NPC_MAX_INTF];\t/* per intf key len in bits */\n+\tuint32_t datax_len[NPC_MAX_INTF];\t/* per intf data len in bits */\n+\tuint32_t keyw[NPC_MAX_INTF];\t\t/* max key + data len bits */\n+\tuint32_t mcam_entries;\t\t\t/* mcam entries supported */\n+\tuint16_t channel;\t\t\t/* RX Channel number */\n+\tuint32_t rss_grps;\t\t\t/* rss groups supported */\n+\tuint16_t flow_prealloc_size;\t\t/* Pre allocated mcam size */\n+\tuint16_t flow_max_priority;\t\t/* Max priority for flow */\n+\tuint16_t switch_header_type; /* Suppprted switch header type */\n+\tuint32_t mark_actions;\t /* Number of mark actions */\n+\tuint16_t pf_func;\t /* pf_func of device */\n+\tnpc_dxcfg_t prx_dxcfg;\t /* intf, lid, lt, extract */\n+\tnpc_fxcfg_t prx_fxcfg;\t /* Flag extract */\n+\tnpc_ld_flags_t prx_lfcfg; /* KEX LD_Flags CFG */\n+\t/* mcam entry info per priority level: both free & in-use */\n+\tstruct npc_mcam_ents_info *flow_entry_info;\n+\t/* Bitmap of free preallocated entries in ascending index &\n+\t * descending priority\n+\t */\n+\tstruct plt_bitmap **free_entries;\n+\t/* Bitmap of free preallocated entries in descending index &\n+\t * ascending priority\n+\t */\n+\tstruct plt_bitmap **free_entries_rev;\n+\t/* Bitmap of live entries in ascending index & descending priority */\n+\tstruct plt_bitmap **live_entries;\n+\t/* Bitmap of live entries in descending index & ascending priority */\n+\tstruct plt_bitmap **live_entries_rev;\n+\t/* Priority bucket wise tail queue of all npc_flow resources */\n+\tstruct npc_flow_list *flow_list;\n+\tstruct plt_bitmap *rss_grp_entries;\n+};\n+\n+static inline struct npc *\n+roc_npc_to_npc_priv(struct roc_npc *npc)\n+{\n+\treturn (struct npc *)npc->reserved;\n+}\n+#endif /* _ROC_NPC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex dd33e58..11ff0f8 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -32,4 +32,5 @@ RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 8f46fb3..d585d53 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -128,6 +128,7 @@ extern int cnxk_logtype_base;\n extern int cnxk_logtype_mbox;\n extern int cnxk_logtype_npa;\n extern int cnxk_logtype_nix;\n+extern int cnxk_logtype_npc;\n extern int cnxk_logtype_tm;\n \n #define plt_err(fmt, args...) \\\n@@ -148,6 +149,7 @@ extern int cnxk_logtype_tm;\n #define plt_mbox_dbg(fmt, ...)\tplt_dbg(mbox, fmt, ##__VA_ARGS__)\n #define plt_npa_dbg(fmt, ...)\tplt_dbg(npa, fmt, ##__VA_ARGS__)\n #define plt_nix_dbg(fmt, ...)\tplt_dbg(nix, fmt, ##__VA_ARGS__)\n+#define plt_npc_dbg(fmt, ...)\tplt_dbg(npc, fmt, ##__VA_ARGS__)\n #define plt_tm_dbg(fmt, ...)\tplt_dbg(tm, fmt, ##__VA_ARGS__)\n \n #ifdef __cplusplus\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 4a1eb9c..b1756fe 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -23,4 +23,7 @@\n /* NIX */\n #include \"roc_nix_priv.h\"\n \n+/* NPC */\n+#include \"roc_npc_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex 43ba177..c5c5962 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -14,16 +14,20 @@ roc_error_msg_get(int errorcode)\n \tcase NIX_AF_ERR_PARAM:\n \tcase NIX_ERR_PARAM:\n \tcase NPA_ERR_PARAM:\n+\tcase NPC_ERR_PARAM:\n \tcase UTIL_ERR_PARAM:\n \t\terr_msg = \"Invalid parameter\";\n \t\tbreak;\n \tcase NIX_ERR_NO_MEM:\n+\tcase NPC_ERR_NO_MEM:\n \t\terr_msg = \"Out of memory\";\n \t\tbreak;\n \tcase NIX_ERR_INVALID_RANGE:\n+\tcase NPC_ERR_INVALID_RANGE:\n \t\terr_msg = \"Range is not supported\";\n \t\tbreak;\n \tcase NIX_ERR_INTERNAL:\n+\tcase NPC_ERR_INTERNAL:\n \t\terr_msg = \"Internal error\";\n \t\tbreak;\n \tcase NIX_ERR_OP_NOTSUP:\n@@ -104,6 +108,26 @@ roc_error_msg_get(int errorcode)\n \tcase NIX_ERR_NDC_SYNC:\n \t\terr_msg = \"NDC Sync failed\";\n \t\tbreak;\n+\tcase NPC_ERR_INVALID_SPEC:\n+\t\terr_msg = \"NPC invalid spec\";\n+\t\tbreak;\n+\tcase NPC_ERR_INVALID_MASK:\n+\t\terr_msg = \"NPC invalid mask\";\n+\t\tbreak;\n+\tcase NPC_ERR_INVALID_KEX:\n+\t\terr_msg = \"NPC invalid key\";\n+\t\tbreak;\n+\tcase NPC_ERR_INVALID_SIZE:\n+\t\terr_msg = \"NPC invalid key size\";\n+\t\tbreak;\n+\tcase NPC_ERR_ACTION_NOTSUP:\n+\t\terr_msg = \"NPC action not supported\";\n+\t\tbreak;\n+\tcase NPC_ERR_PATTERN_NOTSUP:\n+\t\terr_msg = \"NPC pattern not supported\";\n+\t\tbreak;\n+\tcase NPC_ERR_MCAM_ALLOC:\n+\t\terr_msg = \"MCAM entry alloc failed\";\n \t\tbreak;\n \tcase NPA_ERR_ALLOC:\n \t\terr_msg = \"NPA alloc failed\";\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 829d471..5e2ec93 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -5,6 +5,7 @@ INTERNAL {\n \tcnxk_logtype_mbox;\n \tcnxk_logtype_nix;\n \tcnxk_logtype_npa;\n+\tcnxk_logtype_npc;\n \tcnxk_logtype_tm;\n \tplt_init;\n \troc_clk_freq_get;\n", "prefixes": [ "40/52" ] }