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GET /api/patches/88562/?format=api
{ "id": 88562, "url": "http://patches.dpdk.org/api/patches/88562/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-36-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-36-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-36-ndabilpuram@marvell.com", "date": "2021-03-05T13:39:01", "name": "[35/52] common/cnxk: add nix tm helper to alloc and free resource", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a79b175ea0356885fd76497cd7b9d40e5ab00b6c", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-36-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88562/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88562/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B9AEAA0547;\n\tFri, 5 Mar 2021 14:45:59 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9FCD422A429;\n\tFri, 5 Mar 2021 14:41:17 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 6B31222A413\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:41:16 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DerQT001873 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:41:15 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrqk-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:41:15 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:13 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:41:13 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 2DE7D3F7041;\n Fri, 5 Mar 2021 05:41:10 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=Y3cMDOUlxGo4XSr3mMLRgBtSd896BQlltkd/hkswO7I=;\n b=P+DaJWv93xnI2FMJpARuAC24HBGZBzOAPPvfM+Xz7pBEPassBhd+eH38I5RoV91/XP1W\n PsORABchOP2z2I53q8P57qPTGPLPGAuqiNU+6jkjDXCmnPvWI9dUjop5sjUpaF9d7BkW\n hAJcnh8bMUu8B6F4zDDu3dfprToYdnM0DW1SwUZwsQi7gOjU9G4NtBcNcWll0nP528Gz\n sN6b3hIS8nJZZiGtEPwttISA8eSuLJwZUL0yKoISs/v7vduWPVihXugPQpHzmO26BqJi\n gksHUr4kJDR2RomvWf0chjAKnykO6LDkJ+hd1R3Mn8/LWF9Sl+WTvOfxoCbwj9oXVC3F BQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Fri, 5 Mar 2021 19:09:01 +0530", "Message-ID": "<20210305133918.8005-36-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 35/52] common/cnxk: add nix tm helper to alloc\n and free resource", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add TM helper API to estimate, alloc, assign, and free resources\nfor a NIX LF / ethdev.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 1 +\n drivers/common/cnxk/roc_nix_priv.h | 16 ++\n drivers/common/cnxk/roc_nix_tm.c | 461 +++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_tm_ops.c | 11 +\n drivers/common/cnxk/roc_nix_tm_utils.c | 133 ++++++++++\n drivers/common/cnxk/version.map | 1 +\n 6 files changed, 623 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex cadf4ea..0f3b85c 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -359,6 +359,7 @@ int __roc_api roc_nix_tm_node_add(struct roc_nix *roc_nix,\n \t\t\t\t struct roc_nix_tm_node *roc_node);\n int __roc_api roc_nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t\t\t bool free);\n+int __roc_api roc_nix_tm_free_resources(struct roc_nix *roc_nix, bool hw_only);\n int __roc_api roc_nix_tm_node_pkt_mode_update(struct roc_nix *roc_nix,\n \t\t\t\t\t uint32_t node_id, bool pkt_mode);\n int __roc_api roc_nix_tm_shaper_profile_add(\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 278e7df..6e86681 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -329,8 +329,17 @@ int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node);\n int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t enum roc_nix_tm_tree tree, bool free);\n int nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node);\n+int nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask,\n+\t\t\t bool hw_only);\n int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);\n void nix_tm_clear_shaper_profiles(struct nix *nix);\n+int nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree);\n+int nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree);\n+int nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,\n+\t\t\t bool above_thresh);\n+void nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp);\n+\n+int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);\n \n /*\n * TM priv utils.\n@@ -347,11 +356,18 @@ struct nix_tm_shaper_profile *nix_tm_shaper_profile_search(struct nix *nix,\n \t\t\t\t\t\t\t uint32_t id);\n uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,\n \t\t\t volatile uint64_t *reg, volatile uint64_t *regval);\n+uint32_t nix_tm_check_rr(struct nix *nix, uint32_t parent_id,\n+\t\t\t enum roc_nix_tm_tree tree, uint32_t *rr_prio,\n+\t\t\t uint32_t *max_prio);\n uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);\n uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,\n \t\t\t\t uint64_t *mantissa_p, uint64_t *div_exp_p);\n uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,\n \t\t\t\t uint64_t *mantissa_p);\n+bool nix_tm_child_res_valid(struct nix_tm_node_list *list,\n+\t\t\t struct nix_tm_node *parent);\n+uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,\n+\t\t\t\t uint16_t *schq, enum roc_nix_tm_tree tree);\n struct nix_tm_node *nix_tm_node_alloc(void);\n void nix_tm_node_free(struct nix_tm_node *node);\n struct nix_tm_shaper_profile *nix_tm_shaper_profile_alloc(void);\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 1bfdbf9..9adeab9 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -5,6 +5,15 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n+static inline int\n+bitmap_ctzll(uint64_t slab)\n+{\n+\tif (slab == 0)\n+\t\treturn 0;\n+\n+\treturn __builtin_ctzll(slab);\n+}\n+\n void\n nix_tm_clear_shaper_profiles(struct nix *nix)\n {\n@@ -22,6 +31,44 @@ nix_tm_clear_shaper_profiles(struct nix *nix)\n }\n \n int\n+nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree)\n+{\n+\tstruct nix_tm_node *child, *parent;\n+\tstruct nix_tm_node_list *list;\n+\tuint32_t rr_prio, max_prio;\n+\tuint32_t rr_num = 0;\n+\n+\tlist = nix_tm_node_list(nix, tree);\n+\n+\t/* Release all the node hw resources locally\n+\t * if parent marked as dirty and resource exists.\n+\t */\n+\tTAILQ_FOREACH(child, list, node) {\n+\t\t/* Release resource only if parent direct hierarchy changed */\n+\t\tif (child->flags & NIX_TM_NODE_HWRES && child->parent &&\n+\t\t child->parent->child_realloc) {\n+\t\t\tnix_tm_free_node_resource(nix, child);\n+\t\t}\n+\t\tchild->max_prio = UINT32_MAX;\n+\t}\n+\n+\tTAILQ_FOREACH(parent, list, node) {\n+\t\t/* Count group of children of same priority i.e are RR */\n+\t\trr_num = nix_tm_check_rr(nix, parent->id, tree, &rr_prio,\n+\t\t\t\t\t &max_prio);\n+\n+\t\t/* Assuming that multiple RR groups are\n+\t\t * not configured based on capability.\n+\t\t */\n+\t\tparent->rr_prio = rr_prio;\n+\t\tparent->rr_num = rr_num;\n+\t\tparent->max_prio = max_prio;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n@@ -431,6 +478,71 @@ nix_tm_sq_flush_post(struct roc_nix_sq *sq)\n }\n \n int\n+nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,\n+\t\t\t bool above_thresh)\n+{\n+\tuint16_t avail, thresh, to_free = 0, schq;\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_txsch_free_req *req;\n+\tstruct plt_bitmap *bmp;\n+\tuint64_t slab = 0;\n+\tuint32_t pos = 0;\n+\tint rc = -ENOSPC;\n+\n+\tbmp = contig ? nix->schq_contig_bmp[hw_lvl] : nix->schq_bmp[hw_lvl];\n+\tthresh =\n+\t\tcontig ? nix->contig_rsvd[hw_lvl] : nix->discontig_rsvd[hw_lvl];\n+\tplt_bitmap_scan_init(bmp);\n+\n+\tavail = nix_tm_resource_avail(nix, hw_lvl, contig);\n+\n+\tif (above_thresh) {\n+\t\t/* Release only above threshold */\n+\t\tif (avail > thresh)\n+\t\t\tto_free = avail - thresh;\n+\t} else {\n+\t\t/* Release everything */\n+\t\tto_free = avail;\n+\t}\n+\n+\t/* Now release resources to AF */\n+\twhile (to_free) {\n+\t\tif (!slab && !plt_bitmap_scan(bmp, &pos, &slab))\n+\t\t\tbreak;\n+\n+\t\tschq = bitmap_ctzll(slab);\n+\t\tslab &= ~(1ULL << schq);\n+\t\tschq += pos;\n+\n+\t\t/* Free to AF */\n+\t\treq = mbox_alloc_msg_nix_txsch_free(mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn rc;\n+\t\treq->flags = 0;\n+\t\treq->schq_lvl = hw_lvl;\n+\t\treq->schq = schq;\n+\t\trc = mbox_process(mbox);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"failed to release hwres %s(%u) rc %d\",\n+\t\t\t\tnix_tm_hwlvl2str(hw_lvl), schq, rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tplt_tm_dbg(\"Released hwres %s(%u)\", nix_tm_hwlvl2str(hw_lvl),\n+\t\t\t schq);\n+\t\tplt_bitmap_clear(bmp, schq);\n+\t\tto_free--;\n+\t}\n+\n+\tif (to_free) {\n+\t\tplt_err(\"resource inconsistency for %s(%u)\",\n+\t\t\tnix_tm_hwlvl2str(hw_lvl), contig);\n+\t\treturn -EFAULT;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node)\n {\n \tstruct mbox *mbox = (&nix->dev)->mbox;\n@@ -539,6 +651,355 @@ nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,\n \treturn 0;\n }\n \n+static int\n+nix_tm_assign_hw_id(struct nix *nix, struct nix_tm_node *parent,\n+\t\t uint16_t *contig_id, int *contig_cnt,\n+\t\t struct nix_tm_node_list *list)\n+{\n+\tstruct nix_tm_node *child;\n+\tstruct plt_bitmap *bmp;\n+\tuint8_t child_hw_lvl;\n+\tint spare_schq = -1;\n+\tuint32_t pos = 0;\n+\tuint64_t slab;\n+\tuint16_t schq;\n+\n+\tchild_hw_lvl = parent->hw_lvl - 1;\n+\tbmp = nix->schq_bmp[child_hw_lvl];\n+\tplt_bitmap_scan_init(bmp);\n+\tslab = 0;\n+\n+\t/* Save spare schq if it is case of RR + SP */\n+\tif (parent->rr_prio != 0xf && *contig_cnt > 1)\n+\t\tspare_schq = *contig_id + parent->rr_prio;\n+\n+\tTAILQ_FOREACH(child, list, node) {\n+\t\tif (!child->parent)\n+\t\t\tcontinue;\n+\t\tif (child->parent->id != parent->id)\n+\t\t\tcontinue;\n+\n+\t\t/* Resource never expected to be present */\n+\t\tif (child->flags & NIX_TM_NODE_HWRES) {\n+\t\t\tplt_err(\"Resource exists for child (%s)%u, id %u (%p)\",\n+\t\t\t\tnix_tm_hwlvl2str(child->hw_lvl), child->hw_id,\n+\t\t\t\tchild->id, child);\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\n+\t\tif (!slab)\n+\t\t\tplt_bitmap_scan(bmp, &pos, &slab);\n+\n+\t\tif (child->priority == parent->rr_prio && spare_schq != -1) {\n+\t\t\t/* Use spare schq first if present */\n+\t\t\tschq = spare_schq;\n+\t\t\tspare_schq = -1;\n+\t\t\t*contig_cnt = *contig_cnt - 1;\n+\n+\t\t} else if (child->priority == parent->rr_prio) {\n+\t\t\t/* Assign a discontiguous queue */\n+\t\t\tif (!slab) {\n+\t\t\t\tplt_err(\"Schq not found for Child %u \"\n+\t\t\t\t\t\"lvl %u (%p)\",\n+\t\t\t\t\tchild->id, child->lvl, child);\n+\t\t\t\treturn -ENOENT;\n+\t\t\t}\n+\n+\t\t\tschq = bitmap_ctzll(slab);\n+\t\t\tslab &= ~(1ULL << schq);\n+\t\t\tschq += pos;\n+\t\t\tplt_bitmap_clear(bmp, schq);\n+\t\t} else {\n+\t\t\t/* Assign a contiguous queue */\n+\t\t\tschq = *contig_id + child->priority;\n+\t\t\t*contig_cnt = *contig_cnt - 1;\n+\t\t}\n+\n+\t\tplt_tm_dbg(\"Resource %s(%u), for lvl %u id %u(%p)\",\n+\t\t\t nix_tm_hwlvl2str(child->hw_lvl), schq, child->lvl,\n+\t\t\t child->id, child);\n+\n+\t\tchild->hw_id = schq;\n+\t\tchild->parent_hw_id = parent->hw_id;\n+\t\tchild->flags |= NIX_TM_NODE_HWRES;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree)\n+{\n+\tstruct nix_tm_node *parent, *root = NULL;\n+\tstruct plt_bitmap *bmp, *bmp_contig;\n+\tstruct nix_tm_node_list *list;\n+\tuint8_t child_hw_lvl, hw_lvl;\n+\tuint16_t contig_id, j;\n+\tuint64_t slab = 0;\n+\tuint32_t pos = 0;\n+\tint cnt, rc;\n+\n+\tlist = nix_tm_node_list(nix, tree);\n+\t/* Walk from TL1 to TL4 parents */\n+\tfor (hw_lvl = NIX_TXSCH_LVL_TL1; hw_lvl > 0; hw_lvl--) {\n+\t\tTAILQ_FOREACH(parent, list, node) {\n+\t\t\tchild_hw_lvl = parent->hw_lvl - 1;\n+\t\t\tif (parent->hw_lvl != hw_lvl)\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Remember root for future */\n+\t\t\tif (parent->hw_lvl == nix->tm_root_lvl)\n+\t\t\t\troot = parent;\n+\n+\t\t\tif (!parent->child_realloc) {\n+\t\t\t\t/* Skip when parent is not dirty */\n+\t\t\t\tif (nix_tm_child_res_valid(list, parent))\n+\t\t\t\t\tcontinue;\n+\t\t\t\tplt_err(\"Parent not dirty but invalid \"\n+\t\t\t\t\t\"child res parent id %u(lvl %u)\",\n+\t\t\t\t\tparent->id, parent->lvl);\n+\t\t\t\treturn -EFAULT;\n+\t\t\t}\n+\n+\t\t\tbmp_contig = nix->schq_contig_bmp[child_hw_lvl];\n+\n+\t\t\t/* Prealloc contiguous indices for a parent */\n+\t\t\tcontig_id = NIX_TM_MAX_HW_TXSCHQ;\n+\t\t\tcnt = (int)parent->max_prio + 1;\n+\t\t\tif (cnt > 0) {\n+\t\t\t\tplt_bitmap_scan_init(bmp_contig);\n+\t\t\t\tif (!plt_bitmap_scan(bmp_contig, &pos, &slab)) {\n+\t\t\t\t\tplt_err(\"Contig schq not found\");\n+\t\t\t\t\treturn -ENOENT;\n+\t\t\t\t}\n+\t\t\t\tcontig_id = pos + bitmap_ctzll(slab);\n+\n+\t\t\t\t/* Check if we have enough */\n+\t\t\t\tfor (j = contig_id; j < contig_id + cnt; j++) {\n+\t\t\t\t\tif (!plt_bitmap_get(bmp_contig, j))\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\n+\t\t\t\tif (j != contig_id + cnt) {\n+\t\t\t\t\tplt_err(\"Contig schq not sufficient\");\n+\t\t\t\t\treturn -ENOENT;\n+\t\t\t\t}\n+\n+\t\t\t\tfor (j = contig_id; j < contig_id + cnt; j++)\n+\t\t\t\t\tplt_bitmap_clear(bmp_contig, j);\n+\t\t\t}\n+\n+\t\t\t/* Assign hw id to all children */\n+\t\t\trc = nix_tm_assign_hw_id(nix, parent, &contig_id, &cnt,\n+\t\t\t\t\t\t list);\n+\t\t\tif (cnt || rc) {\n+\t\t\t\tplt_err(\"Unexpected err, contig res alloc, \"\n+\t\t\t\t\t\"parent %u, of %s, rc=%d, cnt=%d\",\n+\t\t\t\t\tparent->id, nix_tm_hwlvl2str(hw_lvl),\n+\t\t\t\t\trc, cnt);\n+\t\t\t\treturn -EFAULT;\n+\t\t\t}\n+\n+\t\t\t/* Clear the dirty bit as children's\n+\t\t\t * resources are reallocated.\n+\t\t\t */\n+\t\t\tparent->child_realloc = false;\n+\t\t}\n+\t}\n+\n+\t/* Root is always expected to be there */\n+\tif (!root)\n+\t\treturn -EFAULT;\n+\n+\tif (root->flags & NIX_TM_NODE_HWRES)\n+\t\treturn 0;\n+\n+\t/* Process root node */\n+\tbmp = nix->schq_bmp[nix->tm_root_lvl];\n+\tplt_bitmap_scan_init(bmp);\n+\tif (!plt_bitmap_scan(bmp, &pos, &slab)) {\n+\t\tplt_err(\"Resource not allocated for root\");\n+\t\treturn -EIO;\n+\t}\n+\n+\troot->hw_id = pos + bitmap_ctzll(slab);\n+\troot->flags |= NIX_TM_NODE_HWRES;\n+\tplt_bitmap_clear(bmp, root->hw_id);\n+\n+\t/* Get TL1 id as well when root is not TL1 */\n+\tif (!nix_tm_have_tl1_access(nix)) {\n+\t\tbmp = nix->schq_bmp[NIX_TXSCH_LVL_TL1];\n+\n+\t\tplt_bitmap_scan_init(bmp);\n+\t\tif (!plt_bitmap_scan(bmp, &pos, &slab)) {\n+\t\t\tplt_err(\"Resource not found for TL1\");\n+\t\t\treturn -EIO;\n+\t\t}\n+\t\troot->parent_hw_id = pos + bitmap_ctzll(slab);\n+\t\tplt_bitmap_clear(bmp, root->parent_hw_id);\n+\t}\n+\n+\tplt_tm_dbg(\"Resource %s(%u) for root(id %u) (%p)\",\n+\t\t nix_tm_hwlvl2str(root->hw_lvl), root->hw_id, root->id, root);\n+\n+\treturn 0;\n+}\n+\n+void\n+nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp)\n+{\n+\tuint8_t lvl;\n+\tuint16_t i;\n+\n+\tfor (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {\n+\t\tfor (i = 0; i < rsp->schq[lvl]; i++)\n+\t\t\tplt_bitmap_set(nix->schq_bmp[lvl],\n+\t\t\t\t rsp->schq_list[lvl][i]);\n+\n+\t\tfor (i = 0; i < rsp->schq_contig[lvl]; i++)\n+\t\t\tplt_bitmap_set(nix->schq_contig_bmp[lvl],\n+\t\t\t\t rsp->schq_contig_list[lvl][i]);\n+\t}\n+}\n+\n+int\n+nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)\n+{\n+\tuint16_t schq_contig[NIX_TXSCH_LVL_CNT];\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tuint16_t schq[NIX_TXSCH_LVL_CNT];\n+\tstruct nix_txsch_alloc_req *req;\n+\tstruct nix_txsch_alloc_rsp *rsp;\n+\tuint8_t hw_lvl, i;\n+\tbool pend;\n+\tint rc;\n+\n+\tmemset(schq, 0, sizeof(schq));\n+\tmemset(schq_contig, 0, sizeof(schq_contig));\n+\n+\t/* Estimate requirement */\n+\trc = nix_tm_resource_estimate(nix, schq_contig, schq, tree);\n+\tif (!rc)\n+\t\treturn 0;\n+\n+\t/* Release existing contiguous resources when realloc requested\n+\t * as there is no way to guarantee continuity of old with new.\n+\t */\n+\tfor (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\tif (schq_contig[hw_lvl])\n+\t\t\tnix_tm_release_resources(nix, hw_lvl, true, false);\n+\t}\n+\n+\t/* Alloc as needed */\n+\tdo {\n+\t\tpend = false;\n+\t\treq = mbox_alloc_msg_nix_txsch_alloc(mbox);\n+\t\tif (!req) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto alloc_err;\n+\t\t}\n+\t\tmbox_memcpy(req->schq, schq, sizeof(req->schq));\n+\t\tmbox_memcpy(req->schq_contig, schq_contig,\n+\t\t\t sizeof(req->schq_contig));\n+\n+\t\t/* Each alloc can be at max of MAX_TXSCHQ_PER_FUNC per level.\n+\t\t * So split alloc to multiple requests.\n+\t\t */\n+\t\tfor (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {\n+\t\t\tif (req->schq[i] > MAX_TXSCHQ_PER_FUNC)\n+\t\t\t\treq->schq[i] = MAX_TXSCHQ_PER_FUNC;\n+\t\t\tschq[i] -= req->schq[i];\n+\n+\t\t\tif (req->schq_contig[i] > MAX_TXSCHQ_PER_FUNC)\n+\t\t\t\treq->schq_contig[i] = MAX_TXSCHQ_PER_FUNC;\n+\t\t\tschq_contig[i] -= req->schq_contig[i];\n+\n+\t\t\tif (schq[i] || schq_contig[i])\n+\t\t\t\tpend = true;\n+\t\t}\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\tgoto alloc_err;\n+\n+\t\tnix_tm_copy_rsp_to_nix(nix, rsp);\n+\t} while (pend);\n+\n+\tnix->tm_link_cfg_lvl = rsp->link_cfg_lvl;\n+\treturn 0;\n+alloc_err:\n+\tfor (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {\n+\t\tif (nix_tm_release_resources(nix, i, true, false))\n+\t\t\tplt_err(\"Failed to release contig resources of \"\n+\t\t\t\t\"lvl %d on error\",\n+\t\t\t\ti);\n+\t\tif (nix_tm_release_resources(nix, i, false, false))\n+\t\t\tplt_err(\"Failed to release discontig resources of \"\n+\t\t\t\t\"lvl %d on error\",\n+\t\t\t\ti);\n+\t}\n+\treturn rc;\n+}\n+\n+int\n+nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask, bool hw_only)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_tm_shaper_profile *profile;\n+\tstruct nix_tm_node *node, *next_node;\n+\tstruct nix_tm_node_list *list;\n+\tenum roc_nix_tm_tree tree;\n+\tuint32_t profile_id;\n+\tint rc = 0;\n+\n+\tfor (tree = 0; tree < ROC_NIX_TM_TREE_MAX; tree++) {\n+\t\tif (!(tree_mask & BIT(tree)))\n+\t\t\tcontinue;\n+\n+\t\tplt_tm_dbg(\"Freeing resources of tree %u\", tree);\n+\n+\t\tlist = nix_tm_node_list(nix, tree);\n+\t\tnext_node = TAILQ_FIRST(list);\n+\t\twhile (next_node) {\n+\t\t\tnode = next_node;\n+\t\t\tnext_node = TAILQ_NEXT(node, node);\n+\n+\t\t\tif (!nix_tm_is_leaf(nix, node->lvl) &&\n+\t\t\t node->flags & NIX_TM_NODE_HWRES) {\n+\t\t\t\t/* Clear xoff in path for flush to succeed */\n+\t\t\t\trc = nix_tm_clear_path_xoff(nix, node);\n+\t\t\t\tif (rc)\n+\t\t\t\t\treturn rc;\n+\t\t\t\trc = nix_tm_free_node_resource(nix, node);\n+\t\t\t\tif (rc)\n+\t\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Leave software elements if needed */\n+\t\tif (hw_only)\n+\t\t\tcontinue;\n+\n+\t\tnext_node = TAILQ_FIRST(list);\n+\t\twhile (next_node) {\n+\t\t\tnode = next_node;\n+\t\t\tnext_node = TAILQ_NEXT(node, node);\n+\n+\t\t\tplt_tm_dbg(\"Free node lvl %u id %u (%p)\", node->lvl,\n+\t\t\t\t node->id, node);\n+\n+\t\t\tprofile_id = node->shaper_profile_id;\n+\t\t\tprofile = nix_tm_shaper_profile_search(nix, profile_id);\n+\t\t\tif (profile)\n+\t\t\t\tprofile->ref_cnt--;\n+\n+\t\t\tTAILQ_REMOVE(list, node, node);\n+\t\t\tnix_tm_node_free(node);\n+\t\t}\n+\t}\n+\treturn rc;\n+}\n+\n int\n nix_tm_conf_init(struct roc_nix *roc_nix)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex 015f20e..958cceb 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -66,6 +66,17 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)\n \treturn 0;\n }\n \n+int\n+roc_nix_tm_free_resources(struct roc_nix *roc_nix, bool hw_only)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (nix->tm_flags & NIX_TM_HIERARCHY_ENA)\n+\t\treturn -EBUSY;\n+\n+\treturn nix_tm_free_resources(roc_nix, BIT(ROC_NIX_TM_USER), hw_only);\n+}\n+\n static int\n nix_tm_shaper_profile_add(struct roc_nix *roc_nix,\n \t\t\t struct nix_tm_shaper_profile *profile, int skip_ins)\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex 5eb93a7..e385787 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -177,6 +177,58 @@ nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,\n \treturn NIX_TM_SHAPER_BURST(exponent, mantissa);\n }\n \n+uint32_t\n+nix_tm_check_rr(struct nix *nix, uint32_t parent_id, enum roc_nix_tm_tree tree,\n+\t\tuint32_t *rr_prio, uint32_t *max_prio)\n+{\n+\tuint32_t node_cnt[NIX_TM_TLX_SP_PRIO_MAX];\n+\tstruct nix_tm_node_list *list;\n+\tstruct nix_tm_node *node;\n+\tuint32_t rr_num = 0, i;\n+\tuint32_t children = 0;\n+\tuint32_t priority;\n+\n+\tmemset(node_cnt, 0, sizeof(node_cnt));\n+\t*rr_prio = 0xF;\n+\t*max_prio = UINT32_MAX;\n+\n+\tlist = nix_tm_node_list(nix, tree);\n+\tTAILQ_FOREACH(node, list, node) {\n+\t\tif (!node->parent)\n+\t\t\tcontinue;\n+\n+\t\tif (!(node->parent->id == parent_id))\n+\t\t\tcontinue;\n+\n+\t\tpriority = node->priority;\n+\t\tnode_cnt[priority]++;\n+\t\tchildren++;\n+\t}\n+\n+\tfor (i = 0; i < NIX_TM_TLX_SP_PRIO_MAX; i++) {\n+\t\tif (!node_cnt[i])\n+\t\t\tbreak;\n+\n+\t\tif (node_cnt[i] > rr_num) {\n+\t\t\t*rr_prio = i;\n+\t\t\trr_num = node_cnt[i];\n+\t\t}\n+\t}\n+\n+\t/* RR group of single RR child is considered as SP */\n+\tif (rr_num == 1) {\n+\t\t*rr_prio = 0xF;\n+\t\trr_num = 0;\n+\t}\n+\n+\t/* Max prio will be returned only when we have non zero prio\n+\t * or if a parent has single child.\n+\t */\n+\tif (i > 1 || (children == 1))\n+\t\t*max_prio = i - 1;\n+\treturn rr_num;\n+}\n+\n static uint16_t\n nix_tm_max_prio(struct nix *nix, uint16_t hw_lvl)\n {\n@@ -241,6 +293,21 @@ nix_tm_validate_prio(struct nix *nix, uint32_t lvl, uint32_t parent_id,\n \treturn 0;\n }\n \n+bool\n+nix_tm_child_res_valid(struct nix_tm_node_list *list,\n+\t\t struct nix_tm_node *parent)\n+{\n+\tstruct nix_tm_node *child;\n+\n+\tTAILQ_FOREACH(child, list, node) {\n+\t\tif (child->parent != parent)\n+\t\t\tcontinue;\n+\t\tif (!(child->flags & NIX_TM_NODE_HWRES))\n+\t\t\treturn false;\n+\t}\n+\treturn true;\n+}\n+\n uint8_t\n nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,\n \t\t volatile uint64_t *reg, volatile uint64_t *regval)\n@@ -325,6 +392,72 @@ nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig)\n \treturn count;\n }\n \n+uint16_t\n+nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig, uint16_t *schq,\n+\t\t\t enum roc_nix_tm_tree tree)\n+{\n+\tstruct nix_tm_node_list *list;\n+\tuint8_t contig_cnt, hw_lvl;\n+\tstruct nix_tm_node *parent;\n+\tuint16_t cnt = 0, avail;\n+\n+\tlist = nix_tm_node_list(nix, tree);\n+\t/* Walk through parents from TL1..TL4 */\n+\tfor (hw_lvl = NIX_TXSCH_LVL_TL1; hw_lvl > 0; hw_lvl--) {\n+\t\tTAILQ_FOREACH(parent, list, node) {\n+\t\t\tif (hw_lvl != parent->hw_lvl)\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Skip accounting for children whose\n+\t\t\t * parent does not indicate so.\n+\t\t\t */\n+\t\t\tif (!parent->child_realloc)\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Count children needed */\n+\t\t\tschq[hw_lvl - 1] += parent->rr_num;\n+\t\t\tif (parent->max_prio != UINT32_MAX) {\n+\t\t\t\tcontig_cnt = parent->max_prio + 1;\n+\t\t\t\tschq_contig[hw_lvl - 1] += contig_cnt;\n+\t\t\t\t/* When we have SP + DWRR at a parent,\n+\t\t\t\t * we will always have a spare schq at rr prio\n+\t\t\t\t * location in contiguous queues. Hence reduce\n+\t\t\t\t * discontiguous count by 1.\n+\t\t\t\t */\n+\t\t\t\tif (parent->max_prio > 0 && parent->rr_num)\n+\t\t\t\t\tschq[hw_lvl - 1] -= 1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tschq[nix->tm_root_lvl] = 1;\n+\tif (!nix_tm_have_tl1_access(nix))\n+\t\tschq[NIX_TXSCH_LVL_TL1] = 1;\n+\n+\t/* Now check for existing resources */\n+\tfor (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\tavail = nix_tm_resource_avail(nix, hw_lvl, false);\n+\t\tif (schq[hw_lvl] <= avail)\n+\t\t\tschq[hw_lvl] = 0;\n+\t\telse\n+\t\t\tschq[hw_lvl] -= avail;\n+\n+\t\t/* For contiguous queues, realloc everything */\n+\t\tavail = nix_tm_resource_avail(nix, hw_lvl, true);\n+\t\tif (schq_contig[hw_lvl] <= avail)\n+\t\t\tschq_contig[hw_lvl] = 0;\n+\n+\t\tcnt += schq[hw_lvl];\n+\t\tcnt += schq_contig[hw_lvl];\n+\n+\t\tplt_tm_dbg(\"Estimate resources needed for %s: dis %u cont %u\",\n+\t\t\t nix_tm_hwlvl2str(hw_lvl), schq[hw_lvl],\n+\t\t\t schq_contig[hw_lvl]);\n+\t}\n+\n+\treturn cnt;\n+}\n+\n int\n roc_nix_tm_node_lvl(struct roc_nix *roc_nix, uint32_t node_id)\n {\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 5acbf4c..7b940c1 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -103,6 +103,7 @@ INTERNAL {\n \troc_nix_xstats_names_get;\n \troc_nix_switch_hdr_set;\n \troc_nix_eeprom_info_get;\n+\troc_nix_tm_free_resources;\n \troc_nix_tm_node_add;\n \troc_nix_tm_node_delete;\n \troc_nix_tm_node_get;\n", "prefixes": [ "35/52" ] }