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GET /api/patches/88561/?format=api
{ "id": 88561, "url": "http://patches.dpdk.org/api/patches/88561/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-35-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-35-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-35-ndabilpuram@marvell.com", "date": "2021-03-05T13:39:00", "name": "[34/52] common/cnxk: add nix tm shaper profile add support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "783be76a4af139857da18408b793dfab230c9fc9", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-35-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88561/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 60257A0547;\n\tFri, 5 Mar 2021 14:45:51 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 786B022A426;\n\tFri, 5 Mar 2021 14:41:15 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 6FF7D22A41C\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:41:13 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DelDQ001639 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:41:12 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrqe-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:41:12 -0800", "from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:11 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:10 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:41:10 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 0C4F23F703F;\n Fri, 5 Mar 2021 05:41:07 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=95KDmmUfCLeVBm08j4v0T33fXRU886vqHjVCPnAB684=;\n b=Awn+MpCMEYLKZslXvTWE7vMeFKbay2CGDNkB3T7lxAQF5REoMqG4lYfKTzJNqJ89IGTd\n AD2dzcALJgY6zNrSr7JtnQbZ+lmWjrBAr4W9gDS9FoiRkBqpftFcYyhLQm1tWhA/ssqM\n 3JJWfLNE+FG4mouuGXucdxZSyB6wxsn7ASxQQyalmNScKotUmVQU7zOEoAdVsr1pw3nu\n 8lLeJt0yHHSbGimgj0JnjgVDZ5tn8xK4SKFp6w/PiYx2xo2CRvValQPzCNWA6bpaQubt\n XLmANL7jBcmmbK3shBR6u8fq1WlpmUbRFELVDG04wr7wNLW0tkusgGIlXHvdddDKF8jX xg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Fri, 5 Mar 2021 19:09:00 +0530", "Message-ID": "<20210305133918.8005-35-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 34/52] common/cnxk: add nix tm shaper profile add\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nAdd support to add/delete/update shaper profile for\na given NIX. Also add support to walk through existing\nshaper profiles.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 25 +++++\n drivers/common/cnxk/roc_nix_priv.h | 8 ++\n drivers/common/cnxk/roc_nix_tm.c | 18 ++++\n drivers/common/cnxk/roc_nix_tm_ops.c | 145 ++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_tm_utils.c | 167 +++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 5 +\n 6 files changed, 368 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex fbbea1b..cadf4ea 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -340,17 +340,42 @@ struct roc_nix_tm_node {\n \tvoid (*free_fn)(void *node);\n };\n \n+struct roc_nix_tm_shaper_profile {\n+#define ROC_NIX_TM_SHAPER_PROFILE_SZ (128)\n+\tuint8_t reserved[ROC_NIX_TM_SHAPER_PROFILE_SZ];\n+\n+\tuint32_t id;\n+\tuint64_t commit_rate;\n+\tuint64_t commit_sz;\n+\tuint64_t peak_rate;\n+\tuint64_t peak_sz;\n+\tint32_t pkt_len_adj;\n+\tbool pkt_mode;\n+\t/* Function to free this memory */\n+\tvoid (*free_fn)(void *profile);\n+};\n+\n int __roc_api roc_nix_tm_node_add(struct roc_nix *roc_nix,\n \t\t\t\t struct roc_nix_tm_node *roc_node);\n int __roc_api roc_nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t\t\t bool free);\n int __roc_api roc_nix_tm_node_pkt_mode_update(struct roc_nix *roc_nix,\n \t\t\t\t\t uint32_t node_id, bool pkt_mode);\n+int __roc_api roc_nix_tm_shaper_profile_add(\n+\tstruct roc_nix *roc_nix, struct roc_nix_tm_shaper_profile *profile);\n+int __roc_api roc_nix_tm_shaper_profile_update(\n+\tstruct roc_nix *roc_nix, struct roc_nix_tm_shaper_profile *profile);\n+int __roc_api roc_nix_tm_shaper_profile_delete(struct roc_nix *roc_nix,\n+\t\t\t\t\t uint32_t id);\n \n struct roc_nix_tm_node *__roc_api roc_nix_tm_node_get(struct roc_nix *roc_nix,\n \t\t\t\t\t\t uint32_t node_id);\n struct roc_nix_tm_node *__roc_api\n roc_nix_tm_node_next(struct roc_nix *roc_nix, struct roc_nix_tm_node *__prev);\n+struct roc_nix_tm_shaper_profile *__roc_api\n+roc_nix_tm_shaper_profile_get(struct roc_nix *roc_nix, uint32_t profile_id);\n+struct roc_nix_tm_shaper_profile *__roc_api roc_nix_tm_shaper_profile_next(\n+\tstruct roc_nix *roc_nix, struct roc_nix_tm_shaper_profile *__prev);\n \n /*\n * TM utilities API.\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 2f7c20e..278e7df 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -330,6 +330,7 @@ int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,\n \t\t enum roc_nix_tm_tree tree, bool free);\n int nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node);\n int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);\n+void nix_tm_clear_shaper_profiles(struct nix *nix);\n \n /*\n * TM priv utils.\n@@ -346,7 +347,14 @@ struct nix_tm_shaper_profile *nix_tm_shaper_profile_search(struct nix *nix,\n \t\t\t\t\t\t\t uint32_t id);\n uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,\n \t\t\t volatile uint64_t *reg, volatile uint64_t *regval);\n+uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);\n+uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,\n+\t\t\t\t uint64_t *mantissa_p, uint64_t *div_exp_p);\n+uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,\n+\t\t\t\t uint64_t *mantissa_p);\n struct nix_tm_node *nix_tm_node_alloc(void);\n void nix_tm_node_free(struct nix_tm_node *node);\n+struct nix_tm_shaper_profile *nix_tm_shaper_profile_alloc(void);\n+void nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile);\n \n #endif /* _ROC_NIX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 776d6b4..1bfdbf9 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -5,6 +5,22 @@\n #include \"roc_api.h\"\n #include \"roc_priv.h\"\n \n+void\n+nix_tm_clear_shaper_profiles(struct nix *nix)\n+{\n+\tstruct nix_tm_shaper_profile *shaper_profile;\n+\n+\tshaper_profile = TAILQ_FIRST(&nix->shaper_profile_list);\n+\twhile (shaper_profile != NULL) {\n+\t\tif (shaper_profile->ref_cnt)\n+\t\t\tplt_warn(\"Shaper profile %u has non zero references\",\n+\t\t\t\t shaper_profile->id);\n+\t\tTAILQ_REMOVE(&nix->shaper_profile_list, shaper_profile, shaper);\n+\t\tnix_tm_shaper_profile_free(shaper_profile);\n+\t\tshaper_profile = TAILQ_FIRST(&nix->shaper_profile_list);\n+\t}\n+}\n+\n int\n nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)\n {\n@@ -532,6 +548,8 @@ nix_tm_conf_init(struct roc_nix *roc_nix)\n \tint rc, i;\n \n \tPLT_STATIC_ASSERT(sizeof(struct nix_tm_node) <= ROC_NIX_TM_NODE_SZ);\n+\tPLT_STATIC_ASSERT(sizeof(struct nix_tm_shaper_profile) <=\n+\t\t\t ROC_NIX_TM_SHAPER_PROFILE_SZ);\n \n \tnix->tm_flags = 0;\n \tfor (i = 0; i < ROC_NIX_TM_TREE_MAX; i++)\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex ede30fa..015f20e 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -66,6 +66,151 @@ roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)\n \treturn 0;\n }\n \n+static int\n+nix_tm_shaper_profile_add(struct roc_nix *roc_nix,\n+\t\t\t struct nix_tm_shaper_profile *profile, int skip_ins)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint64_t commit_rate, commit_sz;\n+\tuint64_t peak_rate, peak_sz;\n+\tuint32_t id;\n+\n+\tid = profile->id;\n+\tcommit_rate = profile->commit.rate;\n+\tcommit_sz = profile->commit.size;\n+\tpeak_rate = profile->peak.rate;\n+\tpeak_sz = profile->peak.size;\n+\n+\tif (nix_tm_shaper_profile_search(nix, id) && !skip_ins)\n+\t\treturn NIX_ERR_TM_SHAPER_PROFILE_EXISTS;\n+\n+\tif (profile->pkt_len_adj < NIX_TM_LENGTH_ADJUST_MIN ||\n+\t profile->pkt_len_adj > NIX_TM_LENGTH_ADJUST_MAX)\n+\t\treturn NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST;\n+\n+\t/* We cannot support both pkt length adjust and pkt mode */\n+\tif (profile->pkt_mode && profile->pkt_len_adj)\n+\t\treturn NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST;\n+\n+\t/* commit rate and burst size can be enabled/disabled */\n+\tif (commit_rate || commit_sz) {\n+\t\tif (commit_sz < NIX_TM_MIN_SHAPER_BURST ||\n+\t\t commit_sz > NIX_TM_MAX_SHAPER_BURST)\n+\t\t\treturn NIX_ERR_TM_INVALID_COMMIT_SZ;\n+\t\telse if (!nix_tm_shaper_rate_conv(commit_rate, NULL, NULL,\n+\t\t\t\t\t\t NULL))\n+\t\t\treturn NIX_ERR_TM_INVALID_COMMIT_RATE;\n+\t}\n+\n+\t/* Peak rate and burst size can be enabled/disabled */\n+\tif (peak_sz || peak_rate) {\n+\t\tif (peak_sz < NIX_TM_MIN_SHAPER_BURST ||\n+\t\t peak_sz > NIX_TM_MAX_SHAPER_BURST)\n+\t\t\treturn NIX_ERR_TM_INVALID_PEAK_SZ;\n+\t\telse if (!nix_tm_shaper_rate_conv(peak_rate, NULL, NULL, NULL))\n+\t\t\treturn NIX_ERR_TM_INVALID_PEAK_RATE;\n+\t}\n+\n+\tif (!skip_ins)\n+\t\tTAILQ_INSERT_TAIL(&nix->shaper_profile_list, profile, shaper);\n+\n+\tplt_tm_dbg(\"Added TM shaper profile %u, \"\n+\t\t \" pir %\" PRIu64 \" , pbs %\" PRIu64 \", cir %\" PRIu64\n+\t\t \", cbs %\" PRIu64 \" , adj %u, pkt_mode %u\",\n+\t\t id, profile->peak.rate, profile->peak.size,\n+\t\t profile->commit.rate, profile->commit.size,\n+\t\t profile->pkt_len_adj, profile->pkt_mode);\n+\n+\t/* Always use PIR for single rate shaping */\n+\tif (!peak_rate && commit_rate) {\n+\t\tprofile->peak.rate = profile->commit.rate;\n+\t\tprofile->peak.size = profile->commit.size;\n+\t\tprofile->commit.rate = 0;\n+\t\tprofile->commit.size = 0;\n+\t}\n+\n+\t/* update min rate */\n+\tnix->tm_rate_min = nix_tm_shaper_profile_rate_min(nix);\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_tm_shaper_profile_add(struct roc_nix *roc_nix,\n+\t\t\t struct roc_nix_tm_shaper_profile *roc_profile)\n+{\n+\tstruct nix_tm_shaper_profile *profile;\n+\n+\tprofile = (struct nix_tm_shaper_profile *)roc_profile->reserved;\n+\n+\tprofile->ref_cnt = 0;\n+\tprofile->id = roc_profile->id;\n+\tif (roc_profile->pkt_mode) {\n+\t\t/* Each packet accomulate single count, whereas HW\n+\t\t * considers each unit as Byte, so we need convert\n+\t\t * user pps to bps\n+\t\t */\n+\t\tprofile->commit.rate = roc_profile->commit_rate * 8;\n+\t\tprofile->peak.rate = roc_profile->peak_rate * 8;\n+\t} else {\n+\t\tprofile->commit.rate = roc_profile->commit_rate;\n+\t\tprofile->peak.rate = roc_profile->peak_rate;\n+\t}\n+\tprofile->commit.size = roc_profile->commit_sz;\n+\tprofile->peak.size = roc_profile->peak_sz;\n+\tprofile->pkt_len_adj = roc_profile->pkt_len_adj;\n+\tprofile->pkt_mode = roc_profile->pkt_mode;\n+\tprofile->free_fn = roc_profile->free_fn;\n+\n+\treturn nix_tm_shaper_profile_add(roc_nix, profile, 0);\n+}\n+\n+int\n+roc_nix_tm_shaper_profile_update(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_tm_shaper_profile *roc_profile)\n+{\n+\tstruct nix_tm_shaper_profile *profile;\n+\n+\tprofile = (struct nix_tm_shaper_profile *)roc_profile->reserved;\n+\n+\tif (roc_profile->pkt_mode) {\n+\t\t/* Each packet accomulate single count, whereas HW\n+\t\t * considers each unit as Byte, so we need convert\n+\t\t * user pps to bps\n+\t\t */\n+\t\tprofile->commit.rate = roc_profile->commit_rate * 8;\n+\t\tprofile->peak.rate = roc_profile->peak_rate * 8;\n+\t} else {\n+\t\tprofile->commit.rate = roc_profile->commit_rate;\n+\t\tprofile->peak.rate = roc_profile->peak_rate;\n+\t}\n+\tprofile->commit.size = roc_profile->commit_sz;\n+\tprofile->peak.size = roc_profile->peak_sz;\n+\n+\treturn nix_tm_shaper_profile_add(roc_nix, profile, 1);\n+}\n+\n+int\n+roc_nix_tm_shaper_profile_delete(struct roc_nix *roc_nix, uint32_t id)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_tm_shaper_profile *profile;\n+\n+\tprofile = nix_tm_shaper_profile_search(nix, id);\n+\tif (!profile)\n+\t\treturn NIX_ERR_TM_INVALID_SHAPER_PROFILE;\n+\n+\tif (profile->ref_cnt)\n+\t\treturn NIX_ERR_TM_SHAPER_PROFILE_IN_USE;\n+\n+\tplt_tm_dbg(\"Removing TM shaper profile %u\", id);\n+\tTAILQ_REMOVE(&nix->shaper_profile_list, profile, shaper);\n+\tnix_tm_shaper_profile_free(profile);\n+\n+\t/* update min rate */\n+\tnix->tm_rate_min = nix_tm_shaper_profile_rate_min(nix);\n+\treturn 0;\n+}\n+\n int\n roc_nix_tm_node_add(struct roc_nix *roc_nix, struct roc_nix_tm_node *roc_node)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex 09cb693..5eb93a7 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -77,6 +77,106 @@ nix_tm_node_search(struct nix *nix, uint32_t node_id, enum roc_nix_tm_tree tree)\n \treturn NULL;\n }\n \n+uint64_t\n+nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,\n+\t\t\tuint64_t *mantissa_p, uint64_t *div_exp_p)\n+{\n+\tuint64_t div_exp, exponent, mantissa;\n+\n+\t/* Boundary checks */\n+\tif (value < NIX_TM_MIN_SHAPER_RATE || value > NIX_TM_MAX_SHAPER_RATE)\n+\t\treturn 0;\n+\n+\tif (value <= NIX_TM_SHAPER_RATE(0, 0, 0)) {\n+\t\t/* Calculate rate div_exp and mantissa using\n+\t\t * the following formula:\n+\t\t *\n+\t\t * value = (2E6 * (256 + mantissa)\n+\t\t * / ((1 << div_exp) * 256))\n+\t\t */\n+\t\tdiv_exp = 0;\n+\t\texponent = 0;\n+\t\tmantissa = NIX_TM_MAX_RATE_MANTISSA;\n+\n+\t\twhile (value < (NIX_TM_SHAPER_RATE_CONST / (1 << div_exp)))\n+\t\t\tdiv_exp += 1;\n+\n+\t\twhile (value < ((NIX_TM_SHAPER_RATE_CONST * (256 + mantissa)) /\n+\t\t\t\t((1 << div_exp) * 256)))\n+\t\t\tmantissa -= 1;\n+\t} else {\n+\t\t/* Calculate rate exponent and mantissa using\n+\t\t * the following formula:\n+\t\t *\n+\t\t * value = (2E6 * ((256 + mantissa) << exponent)) / 256\n+\t\t *\n+\t\t */\n+\t\tdiv_exp = 0;\n+\t\texponent = NIX_TM_MAX_RATE_EXPONENT;\n+\t\tmantissa = NIX_TM_MAX_RATE_MANTISSA;\n+\n+\t\twhile (value < (NIX_TM_SHAPER_RATE_CONST * (1 << exponent)))\n+\t\t\texponent -= 1;\n+\n+\t\twhile (value < ((NIX_TM_SHAPER_RATE_CONST *\n+\t\t\t\t ((256 + mantissa) << exponent)) /\n+\t\t\t\t256))\n+\t\t\tmantissa -= 1;\n+\t}\n+\n+\tif (div_exp > NIX_TM_MAX_RATE_DIV_EXP ||\n+\t exponent > NIX_TM_MAX_RATE_EXPONENT ||\n+\t mantissa > NIX_TM_MAX_RATE_MANTISSA)\n+\t\treturn 0;\n+\n+\tif (div_exp_p)\n+\t\t*div_exp_p = div_exp;\n+\tif (exponent_p)\n+\t\t*exponent_p = exponent;\n+\tif (mantissa_p)\n+\t\t*mantissa_p = mantissa;\n+\n+\t/* Calculate real rate value */\n+\treturn NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);\n+}\n+\n+uint64_t\n+nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,\n+\t\t\t uint64_t *mantissa_p)\n+{\n+\tuint64_t exponent, mantissa;\n+\n+\tif (value < NIX_TM_MIN_SHAPER_BURST || value > NIX_TM_MAX_SHAPER_BURST)\n+\t\treturn 0;\n+\n+\t/* Calculate burst exponent and mantissa using\n+\t * the following formula:\n+\t *\n+\t * value = (((256 + mantissa) << (exponent + 1)\n+\t / 256)\n+\t *\n+\t */\n+\texponent = NIX_TM_MAX_BURST_EXPONENT;\n+\tmantissa = NIX_TM_MAX_BURST_MANTISSA;\n+\n+\twhile (value < (1ull << (exponent + 1)))\n+\t\texponent -= 1;\n+\n+\twhile (value < ((256 + mantissa) << (exponent + 1)) / 256)\n+\t\tmantissa -= 1;\n+\n+\tif (exponent > NIX_TM_MAX_BURST_EXPONENT ||\n+\t mantissa > NIX_TM_MAX_BURST_MANTISSA)\n+\t\treturn 0;\n+\n+\tif (exponent_p)\n+\t\t*exponent_p = exponent;\n+\tif (mantissa_p)\n+\t\t*mantissa_p = mantissa;\n+\n+\treturn NIX_TM_SHAPER_BURST(exponent, mantissa);\n+}\n+\n static uint16_t\n nix_tm_max_prio(struct nix *nix, uint16_t hw_lvl)\n {\n@@ -183,6 +283,23 @@ nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,\n \treturn k;\n }\n \n+/* Search for min rate in topology */\n+uint64_t\n+nix_tm_shaper_profile_rate_min(struct nix *nix)\n+{\n+\tstruct nix_tm_shaper_profile *profile;\n+\tuint64_t rate_min = 1E9; /* 1 Gbps */\n+\n+\tTAILQ_FOREACH(profile, &nix->shaper_profile_list, shaper) {\n+\t\tif (profile->peak.rate && profile->peak.rate < rate_min)\n+\t\t\trate_min = profile->peak.rate;\n+\n+\t\tif (profile->commit.rate && profile->commit.rate < rate_min)\n+\t\t\trate_min = profile->commit.rate;\n+\t}\n+\treturn rate_min;\n+}\n+\n uint16_t\n nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig)\n {\n@@ -251,6 +368,34 @@ roc_nix_tm_node_next(struct roc_nix *roc_nix, struct roc_nix_tm_node *__prev)\n \treturn (struct roc_nix_tm_node *)TAILQ_NEXT(prev, node);\n }\n \n+struct roc_nix_tm_shaper_profile *\n+roc_nix_tm_shaper_profile_get(struct roc_nix *roc_nix, uint32_t profile_id)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_tm_shaper_profile *profile;\n+\n+\tprofile = nix_tm_shaper_profile_search(nix, profile_id);\n+\treturn (struct roc_nix_tm_shaper_profile *)profile;\n+}\n+\n+struct roc_nix_tm_shaper_profile *\n+roc_nix_tm_shaper_profile_next(struct roc_nix *roc_nix,\n+\t\t\t struct roc_nix_tm_shaper_profile *__prev)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_tm_shaper_profile_list *list;\n+\tstruct nix_tm_shaper_profile *prev;\n+\n+\tprev = (struct nix_tm_shaper_profile *)__prev;\n+\tlist = &nix->shaper_profile_list;\n+\n+\t/* HEAD of the list */\n+\tif (!prev)\n+\t\treturn (struct roc_nix_tm_shaper_profile *)TAILQ_FIRST(list);\n+\n+\treturn (struct roc_nix_tm_shaper_profile *)TAILQ_NEXT(prev, shaper);\n+}\n+\n struct nix_tm_node *\n nix_tm_node_alloc(void)\n {\n@@ -272,3 +417,25 @@ nix_tm_node_free(struct nix_tm_node *node)\n \n \t(node->free_fn)(node);\n }\n+\n+struct nix_tm_shaper_profile *\n+nix_tm_shaper_profile_alloc(void)\n+{\n+\tstruct nix_tm_shaper_profile *profile;\n+\n+\tprofile = plt_zmalloc(sizeof(struct nix_tm_shaper_profile), 0);\n+\tif (!profile)\n+\t\treturn NULL;\n+\n+\tprofile->free_fn = plt_free;\n+\treturn profile;\n+}\n+\n+void\n+nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile)\n+{\n+\tif (!profile || !profile->free_fn)\n+\t\treturn;\n+\n+\t(profile->free_fn)(profile);\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 0f70fff..5acbf4c 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -110,6 +110,11 @@ INTERNAL {\n \troc_nix_tm_node_name_get;\n \troc_nix_tm_node_next;\n \troc_nix_tm_node_pkt_mode_update;\n+\troc_nix_tm_shaper_profile_add;\n+\troc_nix_tm_shaper_profile_delete;\n+\troc_nix_tm_shaper_profile_get;\n+\troc_nix_tm_shaper_profile_next;\n+\troc_nix_tm_shaper_profile_update;\n \troc_nix_tm_sq_aura_fc;\n \troc_nix_tm_sq_flush_spin;\n \troc_nix_unregister_cq_irqs;\n", "prefixes": [ "34/52" ] }