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GET /api/patches/88545/?format=api
{ "id": 88545, "url": "http://patches.dpdk.org/api/patches/88545/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-19-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-19-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-19-ndabilpuram@marvell.com", "date": "2021-03-05T13:38:44", "name": "[18/52] common/cnxk: add nix irq support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e619db2f828fe4b86db99fcf7a0cc66f916fdde0", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-19-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88545/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88545/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A5520A0547;\n\tFri, 5 Mar 2021 14:42:57 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AA31622A3BE;\n\tFri, 5 Mar 2021 14:40:27 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 0E03422A370\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:40:25 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DV6tl018520 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:40:25 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrn4-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:40:25 -0800", "from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:40:23 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:40:23 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:40:23 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id A43E73F703F;\n Fri, 5 Mar 2021 05:40:20 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=WgUK8CNngBpG7Hy+CMMDuM0ZwgKVgsm4LalkkyIxlOc=;\n b=hSyggvXltp+AXKF794fRZZmBjdGq/NfRO8s3A0VKjDI/IoZEaembV0NJhKA4dNgVKVpn\n SOK24c0eaAx04H6cRPDCFIROdFGrMuz071r2ervIr1h0kfIvt2iIxUBlzSkkRssVB0hF\n mYFnVPkUcMKUzuUav+lf3i1gXiE/0SBH97Z3tX/h59L5rppKghR0IM5uvW0z8AocsR3e\n D5oMTvxz7hMmmDpiDXNkY0xBpnEkIrX5x3AtOV86RDGNM/fqB+1n7EKDSAF+W7m3LPoT\n uv5BVIuIKQbxnNpI4MT0JQFbtmuBvdxvBMEIC06gTFLgiW8oexQXzw63wklml3xtzawM FA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Harman Kalra\n <hkalra@marvell.com>", "Date": "Fri, 5 Mar 2021 19:08:44 +0530", "Message-ID": "<20210305133918.8005-19-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 18/52] common/cnxk: add nix irq support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd support to register NIX error and completion\nqueue IRQ's using base device class IRQ helper API's.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_nix.c | 7 +\n drivers/common/cnxk/roc_nix.h | 12 +\n drivers/common/cnxk/roc_nix_irq.c | 484 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_priv.h | 18 ++\n drivers/common/cnxk/version.map | 8 +\n 6 files changed, 530 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_irq.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 1371450..39aa4ae 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -17,6 +17,7 @@ sources = files('roc_dev.c',\n \t\t'roc_mbox.c',\n \t\t'roc_model.c',\n \t\t'roc_nix.c',\n+\t\t'roc_nix_irq.c',\n \t\t'roc_npa.c',\n \t\t'roc_npa_debug.c',\n \t\t'roc_npa_irq.c',\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 992fe5d..41b4572 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -363,6 +363,11 @@ roc_nix_dev_init(struct roc_nix *roc_nix)\n \tnix->reta_sz = reta_sz;\n \tnix->mtu = ROC_NIX_DEFAULT_HW_FRS;\n \n+\t/* Register error and ras interrupts */\n+\trc = nix_register_irqs(nix);\n+\tif (rc)\n+\t\tgoto lf_detach;\n+\n \t/* Get NIX HW info */\n \troc_nix_get_hw_info(roc_nix);\n \tnix->dev.drv_inited = true;\n@@ -388,6 +393,8 @@ roc_nix_dev_fini(struct roc_nix *roc_nix)\n \tif (!nix->dev.drv_inited)\n \t\tgoto fini;\n \n+\tnix_unregister_irqs(nix);\n+\n \trc = nix_lf_detach(nix);\n \tnix->dev.drv_inited = false;\n fini:\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 5bbeb8b..f32f69d 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -81,4 +81,16 @@ int __roc_api roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq,\n \t\t\t uint32_t nb_txq, uint64_t rx_cfg);\n int __roc_api roc_nix_lf_free(struct roc_nix *roc_nix);\n \n+/* IRQ */\n+void __roc_api roc_nix_rx_queue_intr_enable(struct roc_nix *roc_nix,\n+\t\t\t\t\t uint16_t rxq_id);\n+void __roc_api roc_nix_rx_queue_intr_disable(struct roc_nix *roc_nix,\n+\t\t\t\t\t uint16_t rxq_id);\n+void __roc_api roc_nix_err_intr_ena_dis(struct roc_nix *roc_nix, bool enb);\n+void __roc_api roc_nix_ras_intr_ena_dis(struct roc_nix *roc_nix, bool enb);\n+int __roc_api roc_nix_register_queue_irqs(struct roc_nix *roc_nix);\n+void __roc_api roc_nix_unregister_queue_irqs(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_register_cq_irqs(struct roc_nix *roc_nix);\n+void __roc_api roc_nix_unregister_cq_irqs(struct roc_nix *roc_nix);\n+\n #endif /* _ROC_NIX_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c\nnew file mode 100644\nindex 0000000..d7390d4\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_irq.c\n@@ -0,0 +1,484 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static void\n+nix_err_intr_enb_dis(struct nix *nix, bool enb)\n+{\n+\t/* Enable all nix lf error irqs except RQ_DISABLED and CQ_DISABLED */\n+\tif (enb)\n+\t\tplt_write64(~(BIT_ULL(11) | BIT_ULL(24)),\n+\t\t\t nix->base + NIX_LF_ERR_INT_ENA_W1S);\n+\telse\n+\t\tplt_write64(~0ull, nix->base + NIX_LF_ERR_INT_ENA_W1C);\n+}\n+\n+static void\n+nix_ras_intr_enb_dis(struct nix *nix, bool enb)\n+{\n+\tif (enb)\n+\t\tplt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1S);\n+\telse\n+\t\tplt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1C);\n+}\n+\n+void\n+roc_nix_rx_queue_intr_enable(struct roc_nix *roc_nix, uint16_t rx_queue_id)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\t/* Enable CINT interrupt */\n+\tplt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1S(rx_queue_id));\n+}\n+\n+void\n+roc_nix_rx_queue_intr_disable(struct roc_nix *roc_nix, uint16_t rx_queue_id)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\t/* Clear and disable CINT interrupt */\n+\tplt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1C(rx_queue_id));\n+}\n+\n+void\n+roc_nix_err_intr_ena_dis(struct roc_nix *roc_nix, bool enb)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix_err_intr_enb_dis(nix, enb);\n+}\n+\n+void\n+roc_nix_ras_intr_ena_dis(struct roc_nix *roc_nix, bool enb)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix_ras_intr_enb_dis(nix, enb);\n+}\n+\n+static void\n+nix_lf_err_irq(void *param)\n+{\n+\tstruct nix *nix = (struct nix *)param;\n+\tstruct dev *dev = &nix->dev;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(nix->base + NIX_LF_ERR_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Err_irq=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, nix->base + NIX_LF_ERR_INT);\n+}\n+\n+static int\n+nix_lf_register_err_irq(struct nix *nix)\n+{\n+\tstruct plt_intr_handle *handle = &nix->pci_dev->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;\n+\t/* Clear err interrupt */\n+\tnix_err_intr_enb_dis(nix, false);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, nix_lf_err_irq, nix, vec);\n+\t/* Enable all dev interrupt except for RQ_DISABLED */\n+\tnix_err_intr_enb_dis(nix, true);\n+\n+\treturn rc;\n+}\n+\n+static void\n+nix_lf_unregister_err_irq(struct nix *nix)\n+{\n+\tstruct plt_intr_handle *handle = &nix->pci_dev->intr_handle;\n+\tint vec;\n+\n+\tvec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;\n+\t/* Clear err interrupt */\n+\tnix_err_intr_enb_dis(nix, false);\n+\tdev_irq_unregister(handle, nix_lf_err_irq, nix, vec);\n+}\n+\n+static void\n+nix_lf_ras_irq(void *param)\n+{\n+\tstruct nix *nix = (struct nix *)param;\n+\tstruct dev *dev = &nix->dev;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(nix->base + NIX_LF_RAS);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Ras_intr=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n+\t/* Clear interrupt */\n+\tplt_write64(intr, nix->base + NIX_LF_RAS);\n+}\n+\n+static int\n+nix_lf_register_ras_irq(struct nix *nix)\n+{\n+\tstruct plt_intr_handle *handle = &nix->pci_dev->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = nix->msixoff + NIX_LF_INT_VEC_POISON;\n+\t/* Clear err interrupt */\n+\tnix_ras_intr_enb_dis(nix, false);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, nix_lf_ras_irq, nix, vec);\n+\t/* Enable dev interrupt */\n+\tnix_ras_intr_enb_dis(nix, true);\n+\n+\treturn rc;\n+}\n+\n+static void\n+nix_lf_unregister_ras_irq(struct nix *nix)\n+{\n+\tstruct plt_intr_handle *handle = &nix->pci_dev->intr_handle;\n+\tint vec;\n+\n+\tvec = nix->msixoff + NIX_LF_INT_VEC_POISON;\n+\t/* Clear err interrupt */\n+\tnix_ras_intr_enb_dis(nix, false);\n+\tdev_irq_unregister(handle, nix_lf_ras_irq, nix, vec);\n+}\n+\n+static inline uint8_t\n+nix_lf_q_irq_get_and_clear(struct nix *nix, uint16_t q, uint32_t off,\n+\t\t\t uint64_t mask)\n+{\n+\tuint64_t reg, wdata;\n+\tuint8_t qint;\n+\n+\twdata = (uint64_t)q << 44;\n+\treg = roc_atomic64_add_nosync(wdata, (int64_t *)(nix->base + off));\n+\n+\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n+\t\tplt_err(\"Failed execute irq get off=0x%x\", off);\n+\t\treturn 0;\n+\t}\n+\tqint = reg & 0xff;\n+\twdata &= mask;\n+\tplt_write64(wdata | qint, nix->base + off);\n+\n+\treturn qint;\n+}\n+\n+static inline uint8_t\n+nix_lf_rq_irq_get_and_clear(struct nix *nix, uint16_t rq)\n+{\n+\treturn nix_lf_q_irq_get_and_clear(nix, rq, NIX_LF_RQ_OP_INT, ~0xff00);\n+}\n+\n+static inline uint8_t\n+nix_lf_cq_irq_get_and_clear(struct nix *nix, uint16_t cq)\n+{\n+\treturn nix_lf_q_irq_get_and_clear(nix, cq, NIX_LF_CQ_OP_INT, ~0xff00);\n+}\n+\n+static inline uint8_t\n+nix_lf_sq_irq_get_and_clear(struct nix *nix, uint16_t sq)\n+{\n+\treturn nix_lf_q_irq_get_and_clear(nix, sq, NIX_LF_SQ_OP_INT, ~0x1ff00);\n+}\n+\n+static inline void\n+nix_lf_sq_debug_reg(struct nix *nix, uint32_t off)\n+{\n+\tuint64_t reg;\n+\n+\treg = plt_read64(nix->base + off);\n+\tif (reg & BIT_ULL(44))\n+\t\tplt_err(\"SQ=%d err_code=0x%x\", (int)((reg >> 8) & 0xfffff),\n+\t\t\t(uint8_t)(reg & 0xff));\n+}\n+\n+static void\n+nix_lf_cq_irq(void *param)\n+{\n+\tstruct nix_qint *cint = (struct nix_qint *)param;\n+\tstruct nix *nix = cint->nix;\n+\n+\t/* Clear interrupt */\n+\tplt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_INT(cint->qintx));\n+}\n+\n+static void\n+nix_lf_q_irq(void *param)\n+{\n+\tstruct nix_qint *qint = (struct nix_qint *)param;\n+\tuint8_t irq, qintx = qint->qintx;\n+\tstruct nix *nix = qint->nix;\n+\tstruct dev *dev = &nix->dev;\n+\tint q, cq, rq, sq;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(nix->base + NIX_LF_QINTX_INT(qintx));\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Queue_intr=0x%\" PRIx64 \" qintx=%d pf=%d, vf=%d\", intr, qintx,\n+\t\tdev->pf, dev->vf);\n+\n+\t/* Handle RQ interrupts */\n+\tfor (q = 0; q < nix->nb_rx_queues; q++) {\n+\t\trq = q % nix->qints;\n+\t\tirq = nix_lf_rq_irq_get_and_clear(nix, rq);\n+\n+\t\tif (irq & BIT_ULL(NIX_RQINT_DROP))\n+\t\t\tplt_err(\"RQ=%d NIX_RQINT_DROP\", rq);\n+\n+\t\tif (irq & BIT_ULL(NIX_RQINT_RED))\n+\t\t\tplt_err(\"RQ=%d NIX_RQINT_RED\", rq);\n+\t}\n+\n+\t/* Handle CQ interrupts */\n+\tfor (q = 0; q < nix->nb_rx_queues; q++) {\n+\t\tcq = q % nix->qints;\n+\t\tirq = nix_lf_cq_irq_get_and_clear(nix, cq);\n+\n+\t\tif (irq & BIT_ULL(NIX_CQERRINT_DOOR_ERR))\n+\t\t\tplt_err(\"CQ=%d NIX_CQERRINT_DOOR_ERR\", cq);\n+\n+\t\tif (irq & BIT_ULL(NIX_CQERRINT_WR_FULL))\n+\t\t\tplt_err(\"CQ=%d NIX_CQERRINT_WR_FULL\", cq);\n+\n+\t\tif (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT))\n+\t\t\tplt_err(\"CQ=%d NIX_CQERRINT_CQE_FAULT\", cq);\n+\t}\n+\n+\t/* Handle SQ interrupts */\n+\tfor (q = 0; q < nix->nb_tx_queues; q++) {\n+\t\tsq = q % nix->qints;\n+\t\tirq = nix_lf_sq_irq_get_and_clear(nix, sq);\n+\n+\t\tif (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) {\n+\t\t\tplt_err(\"SQ=%d NIX_SQINT_LMT_ERR\", sq);\n+\t\t\tnix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG);\n+\t\t}\n+\t\tif (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) {\n+\t\t\tplt_err(\"SQ=%d NIX_SQINT_MNQ_ERR\", sq);\n+\t\t\tnix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG);\n+\t\t}\n+\t\tif (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) {\n+\t\t\tplt_err(\"SQ=%d NIX_SQINT_SEND_ERR\", sq);\n+\t\t\tnix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);\n+\t\t}\n+\t\tif (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) {\n+\t\t\tplt_err(\"SQ=%d NIX_SQINT_SQB_ALLOC_FAIL\", sq);\n+\t\t\tnix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);\n+\t\t}\n+\t}\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, nix->base + NIX_LF_QINTX_INT(qintx));\n+}\n+\n+int\n+roc_nix_register_queue_irqs(struct roc_nix *roc_nix)\n+{\n+\tint vec, q, sqs, rqs, qs, rc = 0;\n+\tstruct plt_intr_handle *handle;\n+\tstruct nix *nix;\n+\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\thandle = &nix->pci_dev->intr_handle;\n+\n+\t/* Figure out max qintx required */\n+\trqs = PLT_MIN(nix->qints, nix->nb_rx_queues);\n+\tsqs = PLT_MIN(nix->qints, nix->nb_tx_queues);\n+\tqs = PLT_MAX(rqs, sqs);\n+\n+\tnix->configured_qints = qs;\n+\n+\tnix->qints_mem =\n+\t\tplt_zmalloc(nix->configured_qints * sizeof(struct nix_qint), 0);\n+\tif (nix->qints_mem == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tfor (q = 0; q < qs; q++) {\n+\t\tvec = nix->msixoff + NIX_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\tplt_write64(0, nix->base + NIX_LF_QINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\tplt_write64(~0ull, nix->base + NIX_LF_QINTX_ENA_W1C(q));\n+\n+\t\tnix->qints_mem[q].nix = nix;\n+\t\tnix->qints_mem[q].qintx = q;\n+\n+\t\t/* Sync qints_mem update */\n+\t\tplt_wmb();\n+\n+\t\t/* Register queue irq vector */\n+\t\trc = dev_irq_register(handle, nix_lf_q_irq, &nix->qints_mem[q],\n+\t\t\t\t vec);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\n+\t\tplt_write64(0, nix->base + NIX_LF_QINTX_CNT(q));\n+\t\tplt_write64(0, nix->base + NIX_LF_QINTX_INT(q));\n+\t\t/* Enable QINT interrupt */\n+\t\tplt_write64(~0ull, nix->base + NIX_LF_QINTX_ENA_W1S(q));\n+\t}\n+\n+\treturn rc;\n+}\n+\n+void\n+roc_nix_unregister_queue_irqs(struct roc_nix *roc_nix)\n+{\n+\tstruct plt_intr_handle *handle;\n+\tstruct nix *nix;\n+\tint vec, q;\n+\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\thandle = &nix->pci_dev->intr_handle;\n+\n+\tfor (q = 0; q < nix->configured_qints; q++) {\n+\t\tvec = nix->msixoff + NIX_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\tplt_write64(0, nix->base + NIX_LF_QINTX_CNT(q));\n+\t\tplt_write64(0, nix->base + NIX_LF_QINTX_INT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\tplt_write64(~0ull, nix->base + NIX_LF_QINTX_ENA_W1C(q));\n+\n+\t\t/* Unregister queue irq vector */\n+\t\tdev_irq_unregister(handle, nix_lf_q_irq, &nix->qints_mem[q],\n+\t\t\t\t vec);\n+\t}\n+\tnix->configured_qints = 0;\n+\n+\tplt_free(nix->qints_mem);\n+\tnix->qints_mem = NULL;\n+}\n+\n+int\n+roc_nix_register_cq_irqs(struct roc_nix *roc_nix)\n+{\n+\tstruct plt_intr_handle *handle;\n+\tuint8_t rc = 0, vec, q;\n+\tstruct nix *nix;\n+\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\thandle = &nix->pci_dev->intr_handle;\n+\n+\tnix->configured_cints = PLT_MIN(nix->cints, nix->nb_rx_queues);\n+\n+\tnix->cints_mem =\n+\t\tplt_zmalloc(nix->configured_cints * sizeof(struct nix_qint), 0);\n+\tif (nix->cints_mem == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tfor (q = 0; q < nix->configured_cints; q++) {\n+\t\tvec = nix->msixoff + NIX_LF_INT_VEC_CINT_START + q;\n+\n+\t\t/* Clear CINT CNT */\n+\t\tplt_write64(0, nix->base + NIX_LF_CINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\tplt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1C(q));\n+\n+\t\tnix->cints_mem[q].nix = nix;\n+\t\tnix->cints_mem[q].qintx = q;\n+\n+\t\t/* Sync cints_mem update */\n+\t\tplt_wmb();\n+\n+\t\t/* Register queue irq vector */\n+\t\trc = dev_irq_register(handle, nix_lf_cq_irq, &nix->cints_mem[q],\n+\t\t\t\t vec);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Fail to register CQ irq, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tif (!handle->intr_vec) {\n+\t\t\thandle->intr_vec = plt_zmalloc(\n+\t\t\t\tnix->configured_cints * sizeof(int), 0);\n+\t\t\tif (!handle->intr_vec) {\n+\t\t\t\tplt_err(\"Failed to allocate %d rx intr_vec\",\n+\t\t\t\t\tnix->configured_cints);\n+\t\t\t\treturn -ENOMEM;\n+\t\t\t}\n+\t\t}\n+\t\t/* VFIO vector zero is resereved for misc interrupt so\n+\t\t * doing required adjustment. (b13bfab4cd)\n+\t\t */\n+\t\thandle->intr_vec[q] = PLT_INTR_VEC_RXTX_OFFSET + vec;\n+\n+\t\t/* Configure CQE interrupt coalescing parameters */\n+\t\tplt_write64(((CQ_CQE_THRESH_DEFAULT) |\n+\t\t\t (CQ_CQE_THRESH_DEFAULT << 32) |\n+\t\t\t (CQ_TIMER_THRESH_DEFAULT << 48)),\n+\t\t\t nix->base + NIX_LF_CINTX_WAIT((q)));\n+\n+\t\t/* Keeping the CQ interrupt disabled as the rx interrupt\n+\t\t * feature needs to be enabled/disabled on demand.\n+\t\t */\n+\t}\n+\n+\treturn rc;\n+}\n+\n+void\n+roc_nix_unregister_cq_irqs(struct roc_nix *roc_nix)\n+{\n+\tstruct plt_intr_handle *handle;\n+\tstruct nix *nix;\n+\tint vec, q;\n+\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\thandle = &nix->pci_dev->intr_handle;\n+\n+\tfor (q = 0; q < nix->configured_cints; q++) {\n+\t\tvec = nix->msixoff + NIX_LF_INT_VEC_CINT_START + q;\n+\n+\t\t/* Clear CINT CNT */\n+\t\tplt_write64(0, nix->base + NIX_LF_CINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\tplt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1C(q));\n+\n+\t\t/* Unregister queue irq vector */\n+\t\tdev_irq_unregister(handle, nix_lf_cq_irq, &nix->cints_mem[q],\n+\t\t\t\t vec);\n+\t}\n+\tplt_free(nix->cints_mem);\n+}\n+\n+int\n+nix_register_irqs(struct nix *nix)\n+{\n+\tint rc;\n+\n+\tif (nix->msixoff == MSIX_VECTOR_INVALID) {\n+\t\tplt_err(\"Invalid NIXLF MSIX vector offset vector: 0x%x\",\n+\t\t\tnix->msixoff);\n+\t\treturn NIX_ERR_PARAM;\n+\t}\n+\n+\t/* Register lf err interrupt */\n+\trc = nix_lf_register_err_irq(nix);\n+\t/* Register RAS interrupt */\n+\trc |= nix_lf_register_ras_irq(nix);\n+\n+\treturn rc;\n+}\n+\n+void\n+nix_unregister_irqs(struct nix *nix)\n+{\n+\tnix_lf_unregister_err_irq(nix);\n+\tnix_lf_unregister_ras_irq(nix);\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 3bd96d9..6e50a1b 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -18,11 +18,25 @@\n /* Apply BP/DROP when CQ is 95% full */\n #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)\n \n+/* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */\n+#define CQ_CQE_THRESH_DEFAULT\t0x1ULL\n+#define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */\n+#define CQ_TIMER_THRESH_MAX\t255\n+\n+struct nix_qint {\n+\tstruct nix *nix;\n+\tuint8_t qintx;\n+};\n+\n struct nix {\n \tuint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];\n \tenum roc_nix_rss_reta_sz reta_sz;\n \tstruct plt_pci_device *pci_dev;\n \tuint16_t bpid[NIX_MAX_CHAN];\n+\tstruct nix_qint *qints_mem;\n+\tstruct nix_qint *cints_mem;\n+\tuint8_t configured_qints;\n+\tuint8_t configured_cints;\n \tstruct roc_nix_sq **sqs;\n \tuint16_t vwqe_interval;\n \tuint16_t tx_chan_base;\n@@ -98,4 +112,8 @@ nix_priv_to_roc_nix(struct nix *nix)\n \t\t\t\t offsetof(struct roc_nix, reserved));\n }\n \n+/* IRQ */\n+int nix_register_irqs(struct nix *nix);\n+void nix_unregister_irqs(struct nix *nix);\n+\n #endif /* _ROC_NIX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex a7d0a6f..3a51c7a 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -16,6 +16,7 @@ INTERNAL {\n \troc_model;\n \troc_nix_dev_fini;\n \troc_nix_dev_init;\n+\troc_nix_err_intr_ena_dis;\n \troc_nix_get_base_chan;\n \troc_nix_get_pf;\n \troc_nix_get_pf_func;\n@@ -28,6 +29,13 @@ INTERNAL {\n \troc_nix_lf_alloc;\n \troc_nix_lf_free;\n \troc_nix_max_pkt_len;\n+\troc_nix_ras_intr_ena_dis;\n+\troc_nix_register_cq_irqs;\n+\troc_nix_register_queue_irqs;\n+\troc_nix_rx_queue_intr_disable;\n+\troc_nix_rx_queue_intr_enable;\n+\troc_nix_unregister_cq_irqs;\n+\troc_nix_unregister_queue_irqs;\n \troc_npa_aura_limit_modify;\n \troc_npa_aura_op_range_set;\n \troc_npa_ctx_dump;\n", "prefixes": [ "18/52" ] }