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GET /api/patches/88536/?format=api
{ "id": 88536, "url": "http://patches.dpdk.org/api/patches/88536/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-10-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-10-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-10-ndabilpuram@marvell.com", "date": "2021-03-05T13:38:35", "name": "[09/52] common/cnxk: add base npa device support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e74f9771f49b66f139acf23f7028a50e13b3cbda", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-10-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88536/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88536/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B7A95A0547;\n\tFri, 5 Mar 2021 14:41:17 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4557722A387;\n\tFri, 5 Mar 2021 14:40:00 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A6A5D22A372\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:39:59 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DUnM6018427 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:39:58 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrkx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:39:58 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:39:57 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:39:56 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:39:56 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 5CBDE3F7041;\n Fri, 5 Mar 2021 05:39:54 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=FxoBxj4zy4xVdQ8ss7oQpeoTy8uFHLz+rJOM2lGZk9o=;\n b=gElYLAFqn4mJdLDdCLb4oaHG0ENgBdXTCUObI4qtt1VcwzA7PCSJZOLQhCJoLzAdVx0D\n T5iXSlUsWyAMCOjWeAMR60a9+M4WclzxCZMJBFyZ0Lhsopzry65wHLntFarrv0Uh3NNs\n sWZNJQmuelVdv4RqUERjbNqusM49obtH22d/zoFxAO6Vb1gKEBuoU5dzWWRFzYM4ADj6\n AMtWAHRe2Aps8E6qMdTooUI0tUB3t2np2rWd88w0G4lwqvRXcsSlvFAQGitG3Gwr0Izc\n 3vQ1y5GxVThEF0CTBYPewUXhUHlc+c3dXQ4KIc47OG3ETOJDCkbnVXX6MraEhOtc3uBj Sg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Fri, 5 Mar 2021 19:08:35 +0530", "Message-ID": "<20210305133918.8005-10-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 09/52] common/cnxk: add base npa device support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ashwin Sekhar T K <asekhar@marvell.com>\n\nAdd NPA init and fini functions.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_dev.c | 11 ++\n drivers/common/cnxk/roc_dev_priv.h | 6 +\n drivers/common/cnxk/roc_idev.c | 67 ++++++++\n drivers/common/cnxk/roc_idev.h | 3 +\n drivers/common/cnxk/roc_idev_priv.h | 12 ++\n drivers/common/cnxk/roc_npa.c | 318 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_npa.h | 20 +++\n drivers/common/cnxk/roc_npa_priv.h | 59 +++++++\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_utils.c | 22 +++\n drivers/common/cnxk/version.map | 5 +\n 15 files changed, 533 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_npa.c\n create mode 100644 drivers/common/cnxk/roc_npa.h\n create mode 100644 drivers/common/cnxk/roc_npa_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 735d3f8..c684e1d 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -16,6 +16,7 @@ sources = files('roc_dev.c',\n \t\t'roc_irq.c',\n \t\t'roc_mbox.c',\n \t\t'roc_model.c',\n+\t\t'roc_npa.c',\n \t\t'roc_platform.c',\n \t\t'roc_utils.c')\n includes += include_directories('../../bus/pci')\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 83aa4f6..f2c5225 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -79,6 +79,9 @@\n /* Mbox */\n #include \"roc_mbox.h\"\n \n+/* NPA */\n+#include \"roc_npa.h\"\n+\n /* Utils */\n #include \"roc_utils.h\"\n \ndiff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex 1fe1371..157c155 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -1125,6 +1125,10 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)\n \t}\n \tdev->mbox_active = 1;\n \n+\trc = npa_lf_init(dev, pci_dev);\n+\tif (rc)\n+\t\tgoto iounmap;\n+\n \t/* Setup LMT line base */\n \trc = dev_lmt_setup(pci_dev, dev);\n \tif (rc)\n@@ -1150,6 +1154,13 @@ dev_fini(struct dev *dev, struct plt_pci_device *pci_dev)\n \tstruct plt_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tstruct mbox *mbox;\n \n+\t/* Check if this dev hosts npalf and has 1+ refs */\n+\tif (idev_npa_lf_active(dev) > 1)\n+\t\treturn -EAGAIN;\n+\n+\t/* Clear references to this pci dev */\n+\tnpa_lf_fini();\n+\n \tmbox_unregister_irq(pci_dev, dev);\n \n \tif (!dev_is_vf(dev))\ndiff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h\nindex 0996ec4..ac00e08 100644\n--- a/drivers/common/cnxk/roc_dev_priv.h\n+++ b/drivers/common/cnxk/roc_dev_priv.h\n@@ -78,6 +78,7 @@ struct dev {\n \tdev_intr_t intr;\n \tint timer_set; /* ~0 : no alarm handling */\n \tuint64_t hwcap;\n+\tstruct npa_lf npa;\n \tstruct mbox *mbox;\n \tuint16_t maxvf;\n \tstruct dev_ops *ops;\n@@ -85,6 +86,11 @@ struct dev {\n \tbool disable_shared_lmt; /* false(default): shared lmt mode enabled */\n } __plt_cache_aligned;\n \n+struct npa {\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct dev dev;\n+} __plt_cache_aligned;\n+\n extern uint16_t dev_rclk_freq;\n extern uint16_t dev_sclk_freq;\n \ndiff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex be762c5..dd03b2a 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -29,9 +29,76 @@ idev_get_cfg(void)\n void\n idev_set_defaults(struct idev_cfg *idev)\n {\n+\tidev->npa = NULL;\n+\tidev->npa_pf_func = 0;\n+\tidev->max_pools = 128;\n \tidev->lmt_pf_func = 0;\n \tidev->lmt_base_addr = 0;\n \tidev->num_lmtlines = 0;\n+\t__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);\n+}\n+\n+uint16_t\n+idev_npa_pffunc_get(void)\n+{\n+\tstruct idev_cfg *idev;\n+\tuint16_t npa_pf_func;\n+\n+\tidev = idev_get_cfg();\n+\tnpa_pf_func = 0;\n+\tif (idev != NULL)\n+\t\tnpa_pf_func = idev->npa_pf_func;\n+\n+\treturn npa_pf_func;\n+}\n+\n+struct npa_lf *\n+idev_npa_obj_get(void)\n+{\n+\tstruct idev_cfg *idev;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev && __atomic_load_n(&idev->npa_refcnt, __ATOMIC_ACQUIRE))\n+\t\treturn idev->npa;\n+\n+\treturn NULL;\n+}\n+\n+uint32_t\n+roc_idev_npa_maxpools_get(void)\n+{\n+\tstruct idev_cfg *idev;\n+\tuint32_t max_pools;\n+\n+\tidev = idev_get_cfg();\n+\tmax_pools = 0;\n+\tif (idev != NULL)\n+\t\tmax_pools = idev->max_pools;\n+\n+\treturn max_pools;\n+}\n+\n+void\n+roc_idev_npa_maxpools_set(uint32_t max_pools)\n+{\n+\tstruct idev_cfg *idev;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev != NULL)\n+\t\t__atomic_store_n(&idev->max_pools, max_pools, __ATOMIC_RELEASE);\n+}\n+\n+uint16_t\n+idev_npa_lf_active(struct dev *dev)\n+{\n+\tstruct idev_cfg *idev;\n+\n+\t/* Check if npalf is actively used on this dev */\n+\tidev = idev_get_cfg();\n+\tif (!idev || !idev->npa || idev->npa->mbox != dev->mbox)\n+\t\treturn 0;\n+\n+\treturn __atomic_load_n(&idev->npa_refcnt, __ATOMIC_ACQUIRE);\n }\n \n uint16_t\ndiff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h\nindex 9c45960..9715bb6 100644\n--- a/drivers/common/cnxk/roc_idev.h\n+++ b/drivers/common/cnxk/roc_idev.h\n@@ -5,6 +5,9 @@\n #ifndef _ROC_IDEV_H_\n #define _ROC_IDEV_H_\n \n+uint32_t __roc_api roc_idev_npa_maxpools_get(void);\n+void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools);\n+\n /* LMT */\n uint64_t __roc_api roc_idev_lmt_base_addr_get(void);\n uint16_t __roc_api roc_idev_num_lmtlines_get(void);\ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex c996c5c..535575a 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -6,7 +6,12 @@\n #define _ROC_IDEV_PRIV_H_\n \n /* Intra device related functions */\n+struct npa_lf;\n struct idev_cfg {\n+\tuint16_t npa_pf_func;\n+\tstruct npa_lf *npa;\n+\tuint16_t npa_refcnt;\n+\tuint32_t max_pools;\n \tuint16_t lmt_pf_func;\n \tuint16_t num_lmtlines;\n \tuint64_t lmt_base_addr;\n@@ -16,6 +21,13 @@ struct idev_cfg {\n struct idev_cfg *idev_get_cfg(void);\n void idev_set_defaults(struct idev_cfg *idev);\n \n+/* idev npa */\n+uint16_t idev_npa_pffunc_get(void);\n+struct npa_lf *idev_npa_obj_get(void);\n+uint32_t idev_npa_maxpools_get(void);\n+void idev_npa_maxpools_set(uint32_t max_pools);\n+uint16_t idev_npa_lf_active(struct dev *dev);\n+\n /* idev lmt */\n uint16_t idev_lmt_pffunc_get(void);\n \ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nnew file mode 100644\nindex 0000000..762f025\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -0,0 +1,318 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static inline int\n+npa_attach(struct mbox *mbox)\n+{\n+\tstruct rsrc_attach_req *req;\n+\n+\treq = mbox_alloc_msg_attach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\treq->modify = true;\n+\treq->npalf = true;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static inline int\n+npa_detach(struct mbox *mbox)\n+{\n+\tstruct rsrc_detach_req *req;\n+\n+\treq = mbox_alloc_msg_detach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\treq->partial = true;\n+\treq->npalf = true;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static inline int\n+npa_get_msix_offset(struct mbox *mbox, uint16_t *npa_msixoff)\n+{\n+\tstruct msix_offset_rsp *msix_rsp;\n+\tint rc;\n+\n+\t/* Get NPA MSIX vector offsets */\n+\tmbox_alloc_msg_msix_offset(mbox);\n+\trc = mbox_process_msg(mbox, (void *)&msix_rsp);\n+\tif (rc == 0)\n+\t\t*npa_msixoff = msix_rsp->npa_msixoff;\n+\n+\treturn rc;\n+}\n+\n+static inline int\n+npa_lf_alloc(struct npa_lf *lf)\n+{\n+\tstruct mbox *mbox = lf->mbox;\n+\tstruct npa_lf_alloc_req *req;\n+\tstruct npa_lf_alloc_rsp *rsp;\n+\tint rc;\n+\n+\treq = mbox_alloc_msg_npa_lf_alloc(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\treq->aura_sz = lf->aura_sz;\n+\treq->nr_pools = lf->nr_pools;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn NPA_ERR_ALLOC;\n+\n+\tlf->stack_pg_ptrs = rsp->stack_pg_ptrs;\n+\tlf->stack_pg_bytes = rsp->stack_pg_bytes;\n+\tlf->qints = rsp->qints;\n+\n+\treturn 0;\n+}\n+\n+static int\n+npa_lf_free(struct mbox *mbox)\n+{\n+\tmbox_alloc_msg_npa_lf_free(mbox);\n+\treturn mbox_process(mbox);\n+}\n+\n+static inline uint32_t\n+aura_size_to_u32(uint8_t val)\n+{\n+\tif (val == NPA_AURA_SZ_0)\n+\t\treturn 128;\n+\tif (val >= NPA_AURA_SZ_MAX)\n+\t\treturn BIT_ULL(20);\n+\n+\treturn 1 << (val + 6);\n+}\n+\n+static inline void\n+pool_count_aura_sz_get(uint32_t *nr_pools, uint8_t *aura_sz)\n+{\n+\tuint32_t val;\n+\n+\tval = roc_idev_npa_maxpools_get();\n+\tif (val < aura_size_to_u32(NPA_AURA_SZ_128))\n+\t\tval = 128;\n+\tif (val > aura_size_to_u32(NPA_AURA_SZ_1M))\n+\t\tval = BIT_ULL(20);\n+\n+\troc_idev_npa_maxpools_set(val);\n+\t*nr_pools = val;\n+\t*aura_sz = plt_log2_u32(val) - 6;\n+}\n+\n+static int\n+npa_dev_init(struct npa_lf *lf, uintptr_t base, struct mbox *mbox)\n+{\n+\tuint32_t i, bmp_sz, nr_pools;\n+\tuint8_t aura_sz;\n+\tint rc;\n+\n+\t/* Sanity checks */\n+\tif (!lf || !base || !mbox)\n+\t\treturn NPA_ERR_PARAM;\n+\n+\tif (base & ROC_AURA_ID_MASK)\n+\t\treturn NPA_ERR_BASE_INVALID;\n+\n+\tpool_count_aura_sz_get(&nr_pools, &aura_sz);\n+\tif (aura_sz == NPA_AURA_SZ_0 || aura_sz >= NPA_AURA_SZ_MAX)\n+\t\treturn NPA_ERR_PARAM;\n+\n+\tmemset(lf, 0x0, sizeof(*lf));\n+\tlf->base = base;\n+\tlf->aura_sz = aura_sz;\n+\tlf->nr_pools = nr_pools;\n+\tlf->mbox = mbox;\n+\n+\trc = npa_lf_alloc(lf);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tbmp_sz = plt_bitmap_get_memory_footprint(nr_pools);\n+\n+\t/* Allocate memory for bitmap */\n+\tlf->npa_bmp_mem = plt_zmalloc(bmp_sz, ROC_ALIGN);\n+\tif (lf->npa_bmp_mem == NULL) {\n+\t\trc = NPA_ERR_ALLOC;\n+\t\tgoto lf_free;\n+\t}\n+\n+\t/* Initialize pool resource bitmap array */\n+\tlf->npa_bmp = plt_bitmap_init(nr_pools, lf->npa_bmp_mem, bmp_sz);\n+\tif (lf->npa_bmp == NULL) {\n+\t\trc = NPA_ERR_PARAM;\n+\t\tgoto bmap_mem_free;\n+\t}\n+\n+\t/* Mark all pools available */\n+\tfor (i = 0; i < nr_pools; i++)\n+\t\tplt_bitmap_set(lf->npa_bmp, i);\n+\n+\t/* Allocate memory for qint context */\n+\tlf->npa_qint_mem = plt_zmalloc(sizeof(struct npa_qint) * nr_pools, 0);\n+\tif (lf->npa_qint_mem == NULL) {\n+\t\trc = NPA_ERR_ALLOC;\n+\t\tgoto bmap_free;\n+\t}\n+\n+\t/* Allocate memory for nap_aura_lim memory */\n+\tlf->aura_lim = plt_zmalloc(sizeof(struct npa_aura_lim) * nr_pools, 0);\n+\tif (lf->aura_lim == NULL) {\n+\t\trc = NPA_ERR_ALLOC;\n+\t\tgoto qint_free;\n+\t}\n+\n+\t/* Init aura start & end limits */\n+\tfor (i = 0; i < nr_pools; i++) {\n+\t\tlf->aura_lim[i].ptr_start = UINT64_MAX;\n+\t\tlf->aura_lim[i].ptr_end = 0x0ull;\n+\t}\n+\n+\treturn 0;\n+\n+qint_free:\n+\tplt_free(lf->npa_qint_mem);\n+bmap_free:\n+\tplt_bitmap_free(lf->npa_bmp);\n+bmap_mem_free:\n+\tplt_free(lf->npa_bmp_mem);\n+lf_free:\n+\tnpa_lf_free(lf->mbox);\n+exit:\n+\treturn rc;\n+}\n+\n+static int\n+npa_dev_fini(struct npa_lf *lf)\n+{\n+\tif (!lf)\n+\t\treturn NPA_ERR_PARAM;\n+\n+\tplt_free(lf->aura_lim);\n+\tplt_free(lf->npa_qint_mem);\n+\tplt_bitmap_free(lf->npa_bmp);\n+\tplt_free(lf->npa_bmp_mem);\n+\n+\treturn npa_lf_free(lf->mbox);\n+}\n+\n+int\n+npa_lf_init(struct dev *dev, struct plt_pci_device *pci_dev)\n+{\n+\tstruct idev_cfg *idev;\n+\tuint16_t npa_msixoff;\n+\tstruct npa_lf *lf;\n+\tint rc;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev == NULL)\n+\t\treturn NPA_ERR_ALLOC;\n+\n+\t/* Not the first PCI device */\n+\tif (__atomic_fetch_add(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST) != 0)\n+\t\treturn 0;\n+\n+\trc = npa_attach(dev->mbox);\n+\tif (rc)\n+\t\tgoto fail;\n+\n+\trc = npa_get_msix_offset(dev->mbox, &npa_msixoff);\n+\tif (rc)\n+\t\tgoto npa_detach;\n+\n+\tlf = &dev->npa;\n+\trc = npa_dev_init(lf, dev->bar2 + (RVU_BLOCK_ADDR_NPA << 20),\n+\t\t\t dev->mbox);\n+\tif (rc)\n+\t\tgoto npa_detach;\n+\n+\tlf->pf_func = dev->pf_func;\n+\tlf->npa_msixoff = npa_msixoff;\n+\tlf->intr_handle = &pci_dev->intr_handle;\n+\tlf->pci_dev = pci_dev;\n+\n+\tidev->npa_pf_func = dev->pf_func;\n+\tidev->npa = lf;\n+\tplt_wmb();\n+\n+\tplt_npa_dbg(\"npa=%p max_pools=%d pf_func=0x%x msix=0x%x\", lf,\n+\t\t roc_idev_npa_maxpools_get(), lf->pf_func, npa_msixoff);\n+\n+\treturn 0;\n+\n+npa_detach:\n+\tnpa_detach(dev->mbox);\n+fail:\n+\t__atomic_fetch_sub(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST);\n+\treturn rc;\n+}\n+\n+int\n+npa_lf_fini(void)\n+{\n+\tstruct idev_cfg *idev;\n+\tint rc = 0;\n+\n+\tidev = idev_get_cfg();\n+\tif (idev == NULL)\n+\t\treturn NPA_ERR_ALLOC;\n+\n+\t/* Not the last PCI device */\n+\tif (__atomic_sub_fetch(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST) != 0)\n+\t\treturn 0;\n+\n+\trc |= npa_dev_fini(idev->npa);\n+\trc |= npa_detach(idev->npa->mbox);\n+\tidev_set_defaults(idev);\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_npa_dev_init(struct roc_npa *roc_npa)\n+{\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct npa *npa;\n+\tstruct dev *dev;\n+\tint rc;\n+\n+\tif (roc_npa == NULL || roc_npa->pci_dev == NULL)\n+\t\treturn NPA_ERR_PARAM;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct npa) <= ROC_NPA_MEM_SZ);\n+\tnpa = roc_npa_to_npa_priv(roc_npa);\n+\tmemset(npa, 0, sizeof(*npa));\n+\tpci_dev = roc_npa->pci_dev;\n+\tdev = &npa->dev;\n+\n+\t/* Initialize device */\n+\trc = dev_init(dev, pci_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc device\");\n+\t\tgoto fail;\n+\t}\n+\n+\tnpa->pci_dev = pci_dev;\n+\tdev->drv_inited = true;\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_npa_dev_fini(struct roc_npa *roc_npa)\n+{\n+\tstruct npa *npa = roc_npa_to_npa_priv(roc_npa);\n+\n+\tif (npa == NULL)\n+\t\treturn NPA_ERR_PARAM;\n+\n+\tnpa->dev.drv_inited = false;\n+\treturn dev_fini(&npa->dev, npa->pci_dev);\n+}\ndiff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nnew file mode 100644\nindex 0000000..b9cf847\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_NPA_H_\n+#define _ROC_NPA_H_\n+\n+#define ROC_AURA_ID_MASK (BIT_ULL(16) - 1)\n+\n+struct roc_npa {\n+\tstruct plt_pci_device *pci_dev;\n+\n+#define ROC_NPA_MEM_SZ (1 * 1024)\n+\tuint8_t reserved[ROC_NPA_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa);\n+int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa);\n+\n+#endif /* _ROC_NPA_H_ */\ndiff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h\nnew file mode 100644\nindex 0000000..a2173c4\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_npa_priv.h\n@@ -0,0 +1,59 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_NPA_PRIV_H_\n+#define _ROC_NPA_PRIV_H_\n+\n+enum npa_error_status {\n+\tNPA_ERR_PARAM = -512,\n+\tNPA_ERR_ALLOC = -513,\n+\tNPA_ERR_INVALID_BLOCK_SZ = -514,\n+\tNPA_ERR_AURA_ID_ALLOC = -515,\n+\tNPA_ERR_AURA_POOL_INIT = -516,\n+\tNPA_ERR_AURA_POOL_FINI = -517,\n+\tNPA_ERR_BASE_INVALID = -518,\n+\tNPA_ERR_DEVICE_NOT_BOUNDED = -519,\n+};\n+\n+struct npa_lf {\n+\tstruct plt_intr_handle *intr_handle;\n+\tstruct npa_aura_lim *aura_lim;\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct plt_bitmap *npa_bmp;\n+\tstruct mbox *mbox;\n+\tuint32_t stack_pg_ptrs;\n+\tuint32_t stack_pg_bytes;\n+\tuint16_t npa_msixoff;\n+\tvoid *npa_qint_mem;\n+\tvoid *npa_bmp_mem;\n+\tuint32_t nr_pools;\n+\tuint16_t pf_func;\n+\tuint8_t aura_sz;\n+\tuint32_t qints;\n+\tuintptr_t base;\n+};\n+\n+struct npa_qint {\n+\tstruct npa_lf *lf;\n+\tuint8_t qintx;\n+};\n+\n+struct npa_aura_lim {\n+\tuint64_t ptr_start;\n+\tuint64_t ptr_end;\n+};\n+\n+struct dev;\n+\n+static inline struct npa *\n+roc_npa_to_npa_priv(struct roc_npa *roc_npa)\n+{\n+\treturn (struct npa *)&roc_npa->reserved[0];\n+}\n+\n+/* NPA lf */\n+int npa_lf_init(struct dev *dev, struct plt_pci_device *pci_dev);\n+int npa_lf_fini(void);\n+\n+#endif /* _ROC_NPA_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex b20ae69..4666749 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -30,3 +30,4 @@ plt_init(void)\n \n RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 76b931b..ba6722c 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -126,6 +126,7 @@\n /* Log */\n extern int cnxk_logtype_base;\n extern int cnxk_logtype_mbox;\n+extern int cnxk_logtype_npa;\n \n #define plt_err(fmt, args...) \\\n \tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n@@ -143,6 +144,7 @@ extern int cnxk_logtype_mbox;\n \n #define plt_base_dbg(fmt, ...)\tplt_dbg(base, fmt, ##__VA_ARGS__)\n #define plt_mbox_dbg(fmt, ...)\tplt_dbg(mbox, fmt, ##__VA_ARGS__)\n+#define plt_npa_dbg(fmt, ...)\tplt_dbg(npa, fmt, ##__VA_ARGS__)\n \n #ifdef __cplusplus\n #define CNXK_PCI_ID(subsystem_dev, dev)\t\t\t\t\\\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 090c597..dfd6351 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -11,6 +11,9 @@\n /* Mbox */\n #include \"roc_mbox_priv.h\"\n \n+/* NPA */\n+#include \"roc_npa_priv.h\"\n+\n /* Dev */\n #include \"roc_dev_priv.h\"\n \ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex 81d511e..0a88f78 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -11,9 +11,31 @@ roc_error_msg_get(int errorcode)\n \tconst char *err_msg;\n \n \tswitch (errorcode) {\n+\tcase NPA_ERR_PARAM:\n \tcase UTIL_ERR_PARAM:\n \t\terr_msg = \"Invalid parameter\";\n \t\tbreak;\n+\tcase NPA_ERR_ALLOC:\n+\t\terr_msg = \"NPA alloc failed\";\n+\t\tbreak;\n+\tcase NPA_ERR_INVALID_BLOCK_SZ:\n+\t\terr_msg = \"NPA invalid block size\";\n+\t\tbreak;\n+\tcase NPA_ERR_AURA_ID_ALLOC:\n+\t\terr_msg = \"NPA aura id alloc failed\";\n+\t\tbreak;\n+\tcase NPA_ERR_AURA_POOL_INIT:\n+\t\terr_msg = \"NPA aura pool init failed\";\n+\t\tbreak;\n+\tcase NPA_ERR_AURA_POOL_FINI:\n+\t\terr_msg = \"NPA aura pool fini failed\";\n+\t\tbreak;\n+\tcase NPA_ERR_BASE_INVALID:\n+\t\terr_msg = \"NPA invalid base\";\n+\t\tbreak;\n+\tcase NPA_ERR_DEVICE_NOT_BOUNDED:\n+\t\terr_msg = \"NPA device is not bounded\";\n+\t\tbreak;\n \tcase UTIL_ERR_FS:\n \t\terr_msg = \"file operation failed\";\n \t\tbreak;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex a9d137d..cf34580 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -3,12 +3,17 @@ INTERNAL {\n \n \tcnxk_logtype_base;\n \tcnxk_logtype_mbox;\n+\tcnxk_logtype_npa;\n \tplt_init;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n+\troc_idev_npa_maxpools_get;\n+\troc_idev_npa_maxpools_set;\n \troc_idev_num_lmtlines_get;\n \troc_model;\n+\troc_npa_dev_fini;\n+\troc_npa_dev_init;\n \n \tlocal: *;\n };\n", "prefixes": [ "09/52" ] }