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GET /api/patches/88530/?format=api
{ "id": 88530, "url": "http://patches.dpdk.org/api/patches/88530/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-4-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-4-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-4-ndabilpuram@marvell.com", "date": "2021-03-05T13:38:29", "name": "[03/52] common/cnxk: add model init and IO handling API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aaa171b55914bf9a08c38b66f2c363d243580007", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-4-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88530/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/88530/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4FC9EA0547;\n\tFri, 5 Mar 2021 14:40:01 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2761222A346;\n\tFri, 5 Mar 2021 14:39:48 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id C88A522A351\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:39:46 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125Ddk1B008288 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:39:46 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 370p7p0daa-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:39:40 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:39:38 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:39:38 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 3D5033F703F;\n Fri, 5 Mar 2021 05:39:36 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=v5A3d7XxYh2+nRupZw5CMULpyLI2VwMupmIFv9DFUJU=;\n b=MDQwnd6gykEEfzkJIO6ioUQYeeKbmklA/jd3soqtCdGLe0J2rPwEkS8kMsDzZ8UxZK1N\n P9kH+lQarFM6luLRUrkYP71JJGj6Z/Rhtr1JCORo1ALSpTeM75rq11yhWLx6KNaQwi6d\n 0UQRE2HwmfUYttBRi9NDsf5Jpi+HxAzU++GztpF22+5SHQMMtKfLn6ja0GmtaZKIZiA2\n 9UtOg1lkHgKKVqLmYR8mbEVDw8NuqjHC5/JS1bXEXZR0Z02Nw76czaurkn6H48ynhegN\n Lc2dCPGpkNI1075vJljDSjWvU5z2xpmfEqAGJA/YNhOXwnXjc8TyRNXMTJiMsMHE1t5I PQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Fri, 5 Mar 2021 19:08:29 +0530", "Message-ID": "<20210305133918.8005-4-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 03/52] common/cnxk: add model init and IO\n handling API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd routines for SoC model identification and HW IO handling\nroutines specific to CN9K and CN10K Marvell SoC's.\nThese are based on arm64 ISA and behaviour specific to\nMarvell SoC's.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/meson.build | 4 +-\n drivers/common/cnxk/roc_api.h | 13 +++\n drivers/common/cnxk/roc_io.h | 187 +++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_io_generic.h | 122 +++++++++++++++++++++++\n drivers/common/cnxk/roc_model.c | 148 +++++++++++++++++++++++++++\n drivers/common/cnxk/roc_model.h | 103 +++++++++++++++++++\n drivers/common/cnxk/roc_platform.c | 21 ++++\n drivers/common/cnxk/roc_platform.h | 10 ++\n drivers/common/cnxk/roc_priv.h | 11 +++\n drivers/common/cnxk/roc_util_priv.h | 14 +++\n drivers/common/cnxk/roc_utils.c | 35 +++++++\n drivers/common/cnxk/roc_utils.h | 13 +++\n drivers/common/cnxk/version.map | 5 +\n 13 files changed, 685 insertions(+), 1 deletion(-)\n create mode 100644 drivers/common/cnxk/roc_io.h\n create mode 100644 drivers/common/cnxk/roc_io_generic.h\n create mode 100644 drivers/common/cnxk/roc_model.c\n create mode 100644 drivers/common/cnxk/roc_model.h\n create mode 100644 drivers/common/cnxk/roc_priv.h\n create mode 100644 drivers/common/cnxk/roc_util_priv.h\n create mode 100644 drivers/common/cnxk/roc_utils.c\n create mode 100644 drivers/common/cnxk/roc_utils.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 1f4d705..e5de6cf 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -11,5 +11,7 @@ endif\n \n config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'\n deps = ['eal', 'pci', 'bus_pci', 'mbuf']\n-sources = files('roc_platform.c')\n+sources = files('roc_model.c',\n+\t\t'roc_platform.c',\n+\t\t'roc_utils.c')\n includes += include_directories('../../bus/pci')\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 83a69ac..7dbeb6a 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -29,6 +29,13 @@\n #define ROC_LMT_BASE_PER_CORE_LOG2 \\\n \t(ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2)\n \n+/* IO */\n+#if defined(__aarch64__)\n+#include \"roc_io.h\"\n+#else\n+#include \"roc_io_generic.h\"\n+#endif\n+\n /* PCI IDs */\n #define PCI_VENDOR_ID_CAVIUM\t 0x177D\n #define PCI_DEVID_CNXK_RVU_PF\t 0xA063\n@@ -66,4 +73,10 @@\n #include \"hw/ssow.h\"\n #include \"hw/tim.h\"\n \n+/* Model */\n+#include \"roc_model.h\"\n+\n+/* Utils */\n+#include \"roc_utils.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h\nnew file mode 100644\nindex 0000000..31849fb\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_io.h\n@@ -0,0 +1,187 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_IO_H_\n+#define _ROC_IO_H_\n+\n+#define ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id) \\\n+\tdo { \\\n+\t\t/* 32 Lines per core */ \\\n+\t\tlmt_id = plt_lcore_id() << ROC_LMT_LINES_PER_CORE_LOG2; \\\n+\t\t/* Each line is of 128B */ \\\n+\t\t(lmt_addr) += ((uint64_t)lmt_id << ROC_LMT_LINE_SIZE_LOG2); \\\n+\t} while (0)\n+\n+#define roc_load_pair(val0, val1, addr) \\\n+\t({ \\\n+\t\tasm volatile(\"ldp %x[x0], %x[x1], [%x[p1]]\" \\\n+\t\t\t : [x0] \"=r\"(val0), [x1] \"=r\"(val1) \\\n+\t\t\t : [p1] \"r\"(addr)); \\\n+\t})\n+\n+#define roc_store_pair(val0, val1, addr) \\\n+\t({ \\\n+\t\tasm volatile( \\\n+\t\t\t\"stp %x[x0], %x[x1], [%x[p1], #0]!\" ::[x0] \"r\"(val0), \\\n+\t\t\t[x1] \"r\"(val1), [p1] \"r\"(addr)); \\\n+\t})\n+\n+#define roc_prefetch_store_keep(ptr) \\\n+\t({ asm volatile(\"prfm pstl1keep, [%x0]\\n\" : : \"r\"(ptr)); })\n+\n+#if defined(__clang__)\n+static __plt_always_inline void\n+roc_atomic128_cas_noreturn(uint64_t swap0, uint64_t swap1, int64_t *ptr)\n+{\n+\tregister uint64_t x0 __asm(\"x0\") = swap0;\n+\tregister uint64_t x1 __asm(\"x1\") = swap1;\n+\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"casp %[x0], %[x1], %[x0], %[x1], [%[ptr]]\\n\"\n+\t\t : [x0] \"+r\"(x0), [x1] \"+r\"(x1)\n+\t\t : [ptr] \"r\"(ptr)\n+\t\t : \"memory\");\n+}\n+#else\n+static __plt_always_inline void\n+roc_atomic128_cas_noreturn(uint64_t swap0, uint64_t swap1, uint64_t ptr)\n+{\n+\t__uint128_t wdata = swap0 | ((__uint128_t)swap1 << 64);\n+\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"casp %[wdata], %H[wdata], %[wdata], %H[wdata], [%[ptr]]\\n\"\n+\t\t : [wdata] \"+r\"(wdata)\n+\t\t : [ptr] \"r\"(ptr)\n+\t\t : \"memory\");\n+}\n+#endif\n+\n+static __plt_always_inline uint64_t\n+roc_atomic64_cas(uint64_t compare, uint64_t swap, int64_t *ptr)\n+{\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"cas %[compare], %[swap], [%[ptr]]\\n\"\n+\t\t : [compare] \"+r\"(compare)\n+\t\t : [swap] \"r\"(swap), [ptr] \"r\"(ptr)\n+\t\t : \"memory\");\n+\n+\treturn compare;\n+}\n+\n+static __plt_always_inline uint64_t\n+roc_atomic64_add_nosync(int64_t incr, int64_t *ptr)\n+{\n+\tuint64_t result;\n+\n+\t/* Atomic add with no ordering */\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE \"ldadd %x[i], %x[r], [%[b]]\"\n+\t\t : [r] \"=r\"(result), \"+m\"(*ptr)\n+\t\t : [i] \"r\"(incr), [b] \"r\"(ptr)\n+\t\t : \"memory\");\n+\treturn result;\n+}\n+\n+static __plt_always_inline uint64_t\n+roc_atomic64_add_sync(int64_t incr, int64_t *ptr)\n+{\n+\tuint64_t result;\n+\n+\t/* Atomic add with ordering */\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE \"ldadda %x[i], %x[r], [%[b]]\"\n+\t\t : [r] \"=r\"(result), \"+m\"(*ptr)\n+\t\t : [i] \"r\"(incr), [b] \"r\"(ptr)\n+\t\t : \"memory\");\n+\treturn result;\n+}\n+\n+static __plt_always_inline uint64_t\n+roc_lmt_submit_ldeor(plt_iova_t io_address)\n+{\n+\tuint64_t result;\n+\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE \"ldeor xzr, %x[rf], [%[rs]]\"\n+\t\t : [rf] \"=r\"(result)\n+\t\t : [rs] \"r\"(io_address));\n+\treturn result;\n+}\n+\n+static __plt_always_inline uint64_t\n+roc_lmt_submit_ldeorl(plt_iova_t io_address)\n+{\n+\tuint64_t result;\n+\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE \"ldeorl xzr,%x[rf],[%[rs]]\"\n+\t\t : [rf] \"=r\"(result)\n+\t\t : [rs] \"r\"(io_address));\n+\treturn result;\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_submit_steor(uint64_t data, plt_iova_t io_address)\n+{\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"steor %x[d], [%[rs]]\" ::[d] \"r\"(data),\n+\t\t [rs] \"r\"(io_address));\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_submit_steorl(uint64_t data, plt_iova_t io_address)\n+{\n+\tasm volatile(PLT_CPU_FEATURE_PREAMBLE\n+\t\t \"steorl %x[d], [%[rs]]\" ::[d] \"r\"(data),\n+\t\t [rs] \"r\"(io_address));\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n+{\n+\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n+\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n+\n+\tdst128[0] = src128[0];\n+\tdst128[1] = src128[1];\n+\t/* lmtext receives following value:\n+\t * 1: NIX_SUBDC_EXT needed i.e. tx vlan case\n+\t * 2: NIX_SUBDC_EXT + NIX_SUBDC_MEM i.e. tstamp case\n+\t */\n+\tif (lmtext) {\n+\t\tdst128[2] = src128[2];\n+\t\tif (lmtext > 1)\n+\t\t\tdst128[3] = src128[3];\n+\t}\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)\n+{\n+\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n+\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n+\tuint8_t i;\n+\n+\tfor (i = 0; i < segdw; i++)\n+\t\tdst128[i] = src128[i];\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov_one(void *out, const void *in)\n+{\n+\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n+\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n+\n+\t*dst128 = *src128;\n+}\n+\n+/* Non volatile version of roc_lmt_mov_seg() */\n+static __plt_always_inline void\n+roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)\n+{\n+\tconst __uint128_t *src128 = (const __uint128_t *)in;\n+\t__uint128_t *dst128 = (__uint128_t *)out;\n+\tuint8_t i;\n+\n+\tfor (i = 0; i < segdw; i++)\n+\t\tdst128[i] = src128[i];\n+}\n+\n+#endif /* _ROC_IO_H_ */\ndiff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h\nnew file mode 100644\nindex 0000000..708c7cd\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_io_generic.h\n@@ -0,0 +1,122 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_IO_GENERIC_H_\n+#define _ROC_IO_GENERIC_H_\n+\n+#define ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id) (lmt_id = 0)\n+\n+#define roc_load_pair(val0, val1, addr) \\\n+\tdo { \\\n+\t\tval0 = plt_read64((void *)(addr)); \\\n+\t\tval1 = plt_read64((uint8_t *)(addr) + 8); \\\n+\t} while (0)\n+\n+#define roc_store_pair(val0, val1, addr) \\\n+\tdo { \\\n+\t\tplt_write64(val0, (void *)(addr)); \\\n+\t\tplt_write64(val1, (((uint8_t *)(addr)) + 8)); \\\n+\t} while (0)\n+\n+#define roc_prefetch_store_keep(ptr) \\\n+\tdo { \\\n+\t} while (0)\n+\n+static __plt_always_inline void\n+roc_atomic128_cas_noreturn(uint64_t swap0, uint64_t swap1, uint64_t ptr)\n+{\n+\tPLT_SET_USED(swap0);\n+\tPLT_SET_USED(swap1);\n+\tPLT_SET_USED(ptr);\n+}\n+\n+static __plt_always_inline uint64_t\n+roc_atomic64_cas(uint64_t compare, uint64_t swap, int64_t *ptr)\n+{\n+\tPLT_SET_USED(swap);\n+\tPLT_SET_USED(ptr);\n+\n+\treturn compare;\n+}\n+\n+static inline uint64_t\n+roc_atomic64_add_nosync(int64_t incr, int64_t *ptr)\n+{\n+\tPLT_SET_USED(ptr);\n+\tPLT_SET_USED(incr);\n+\n+\treturn 0;\n+}\n+\n+static inline uint64_t\n+roc_atomic64_add_sync(int64_t incr, int64_t *ptr)\n+{\n+\tPLT_SET_USED(ptr);\n+\tPLT_SET_USED(incr);\n+\n+\treturn 0;\n+}\n+\n+static inline uint64_t\n+roc_lmt_submit_ldeor(plt_iova_t io_address)\n+{\n+\tPLT_SET_USED(io_address);\n+\n+\treturn 0;\n+}\n+\n+static __plt_always_inline uint64_t\n+roc_lmt_submit_ldeorl(plt_iova_t io_address)\n+{\n+\tPLT_SET_USED(io_address);\n+\n+\treturn 0;\n+}\n+\n+static inline void\n+roc_lmt_submit_steor(uint64_t data, plt_iova_t io_address)\n+{\n+\tPLT_SET_USED(data);\n+\tPLT_SET_USED(io_address);\n+}\n+\n+static inline void\n+roc_lmt_submit_steorl(uint64_t data, plt_iova_t io_address)\n+{\n+\tPLT_SET_USED(data);\n+\tPLT_SET_USED(io_address);\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n+{\n+\tPLT_SET_USED(in);\n+\tPLT_SET_USED(lmtext);\n+\tmemset(out, 0, sizeof(__uint128_t) * (lmtext ? lmtext > 1 ? 4 : 3 : 2));\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)\n+{\n+\tPLT_SET_USED(out);\n+\tPLT_SET_USED(in);\n+\tPLT_SET_USED(segdw);\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov_one(void *out, const void *in)\n+{\n+\tPLT_SET_USED(out);\n+\tPLT_SET_USED(in);\n+}\n+\n+static __plt_always_inline void\n+roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)\n+{\n+\tPLT_SET_USED(out);\n+\tPLT_SET_USED(in);\n+\tPLT_SET_USED(segdw);\n+}\n+\n+#endif /* _ROC_IO_GENERIC_H_ */\ndiff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c\nnew file mode 100644\nindex 0000000..c00f90d\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_model.c\n@@ -0,0 +1,148 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+struct roc_model *roc_model;\n+\n+/* RoC and CPU IDs and revisions */\n+#define VENDOR_ARM 0x41 /* 'A' */\n+#define VENDOR_CAVIUM 0x43 /* 'C' */\n+\n+#define PART_106XX 0xD49\n+#define PART_98XX 0xB1\n+#define PART_96XX 0xB2\n+#define PART_95XX 0xB3\n+#define PART_95XXN 0xB4\n+#define PART_95XXMM 0xB5\n+\n+#define MODEL_IMPL_BITS\t 8\n+#define MODEL_IMPL_SHIFT 24\n+#define MODEL_IMPL_MASK\t ((1 << MODEL_IMPL_BITS) - 1)\n+#define MODEL_PART_BITS\t 12\n+#define MODEL_PART_SHIFT 4\n+#define MODEL_PART_MASK\t ((1 << MODEL_PART_BITS) - 1)\n+#define MODEL_MAJOR_BITS 4\n+#define MODEL_MAJOR_SHIFT 20\n+#define MODEL_MAJOR_MASK ((1 << MODEL_MAJOR_BITS) - 1)\n+#define MODEL_MINOR_BITS 4\n+#define MODEL_MINOR_SHIFT 0\n+#define MODEL_MINOR_MASK ((1 << MODEL_MINOR_BITS) - 1)\n+\n+static const struct model_db {\n+\tuint32_t impl;\n+\tuint32_t part;\n+\tuint32_t major;\n+\tuint32_t minor;\n+\tuint64_t flag;\n+\tchar name[ROC_MODEL_STR_LEN_MAX];\n+} model_db[] = {\n+\t{VENDOR_ARM, PART_106XX, 0, 0, ROC_MODEL_CN10K, \"cn10k\"},\n+\t{VENDOR_CAVIUM, PART_98XX, 0, 0, ROC_MODEL_CN98xx_A0, \"cn98xx_a0\"},\n+\t{VENDOR_CAVIUM, PART_96XX, 0, 0, ROC_MODEL_CN96xx_A0, \"cn96xx_a0\"},\n+\t{VENDOR_CAVIUM, PART_96XX, 0, 1, ROC_MODEL_CN96xx_B0, \"cn96xx_b0\"},\n+\t{VENDOR_CAVIUM, PART_96XX, 2, 0, ROC_MODEL_CN96xx_C0, \"cn96xx_c0\"},\n+\t{VENDOR_CAVIUM, PART_95XX, 0, 0, ROC_MODEL_CNF95xx_A0, \"cnf95xx_a0\"},\n+\t{VENDOR_CAVIUM, PART_95XX, 1, 0, ROC_MODEL_CNF95xx_B0, \"cnf95xx_b0\"},\n+\t{VENDOR_CAVIUM, PART_95XXN, 0, 0, ROC_MODEL_CNF95XXN_A0, \"cnf95xxn_a0\"},\n+\t{VENDOR_CAVIUM, PART_95XXMM, 0, 0, ROC_MODEL_CNF95XXMM_A0,\n+\t \"cnf95xxmm_a0\"}\n+};\n+\n+static bool\n+populate_model(struct roc_model *model, uint32_t midr)\n+{\n+\tuint32_t impl, major, part, minor;\n+\tbool found = false;\n+\tsize_t i;\n+\n+\timpl = (midr >> MODEL_IMPL_SHIFT) & MODEL_IMPL_MASK;\n+\tpart = (midr >> MODEL_PART_SHIFT) & MODEL_PART_MASK;\n+\tmajor = (midr >> MODEL_MAJOR_SHIFT) & MODEL_MAJOR_MASK;\n+\tminor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK;\n+\n+\tfor (i = 0; i < PLT_DIM(model_db); i++)\n+\t\tif (model_db[i].impl == impl && model_db[i].part == part &&\n+\t\t model_db[i].major == major && model_db[i].minor == minor) {\n+\t\t\tmodel->flag = model_db[i].flag;\n+\t\t\tstrncpy(model->name, model_db[i].name,\n+\t\t\t\tROC_MODEL_STR_LEN_MAX - 1);\n+\t\t\tfound = true;\n+\t\t\tbreak;\n+\t\t}\n+\tif (!found) {\n+\t\tmodel->flag = 0;\n+\t\tstrncpy(model->name, \"unknown\", ROC_MODEL_STR_LEN_MAX - 1);\n+\t\tplt_err(\"Invalid RoC model (impl=0x%x, part=0x%x)\", impl, part);\n+\t}\n+\n+\treturn found;\n+}\n+\n+static int\n+midr_get(unsigned long *val)\n+{\n+\tconst char *file =\n+\t\t\"/sys/devices/system/cpu/cpu0/regs/identification/midr_el1\";\n+\tint rc = UTIL_ERR_FS;\n+\tchar buf[BUFSIZ];\n+\tchar *end = NULL;\n+\tFILE *f;\n+\n+\tif (val == NULL)\n+\t\tgoto err;\n+\tf = fopen(file, \"r\");\n+\tif (f == NULL)\n+\t\tgoto err;\n+\n+\tif (fgets(buf, sizeof(buf), f) == NULL)\n+\t\tgoto fclose;\n+\n+\t*val = strtoul(buf, &end, 0);\n+\tif ((buf[0] == '\\0') || (end == NULL) || (*end != '\\n'))\n+\t\tgoto fclose;\n+\n+\trc = 0;\n+fclose:\n+\tfclose(f);\n+err:\n+\treturn rc;\n+}\n+\n+static void\n+detect_invalid_config(void)\n+{\n+#ifdef ROC_PLATFORM_CN9K\n+#ifdef ROC_PLATFORM_CN10K\n+\tPLT_STATIC_ASSERT(0);\n+#endif\n+#endif\n+}\n+\n+int\n+roc_model_init(struct roc_model *model)\n+{\n+\tint rc = UTIL_ERR_PARAM;\n+\tunsigned long midr;\n+\n+\tdetect_invalid_config();\n+\n+\tif (!model)\n+\t\tgoto err;\n+\n+\trc = midr_get(&midr);\n+\tif (rc)\n+\t\tgoto err;\n+\n+\trc = UTIL_ERR_INVALID_MODEL;\n+\tif (!populate_model(model, midr))\n+\t\tgoto err;\n+\n+\trc = 0;\n+\tplt_info(\"RoC Model: %s\", model->name);\n+\troc_model = model;\n+err:\n+\treturn rc;\n+}\ndiff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h\nnew file mode 100644\nindex 0000000..5914648\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_model.h\n@@ -0,0 +1,103 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_MODEL_H_\n+#define _ROC_MODEL_H_\n+\n+#include <stdbool.h>\n+\n+extern struct roc_model *roc_model;\n+\n+struct roc_model {\n+#define ROC_MODEL_CN96xx_A0 BIT_ULL(0)\n+#define ROC_MODEL_CN96xx_B0 BIT_ULL(1)\n+#define ROC_MODEL_CN96xx_C0 BIT_ULL(2)\n+#define ROC_MODEL_CNF95xx_A0 BIT_ULL(4)\n+#define ROC_MODEL_CNF95xx_B0 BIT_ULL(6)\n+#define ROC_MODEL_CNF95XXMM_A0 BIT_ULL(8)\n+#define ROC_MODEL_CNF95XXN_A0 BIT_ULL(12)\n+#define ROC_MODEL_CN98xx_A0 BIT_ULL(16)\n+#define ROC_MODEL_CN10K\t BIT_ULL(20)\n+\tuint64_t flag;\n+#define ROC_MODEL_STR_LEN_MAX 128\n+\tchar name[ROC_MODEL_STR_LEN_MAX];\n+} __plt_cache_aligned;\n+\n+#define ROC_MODEL_CN96xx_Ax (ROC_MODEL_CN96xx_A0 | ROC_MODEL_CN96xx_B0)\n+#define ROC_MODEL_CN9K \\\n+\t(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \\\n+\t ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95XXMM_A0 | \\\n+\t ROC_MODEL_CNF95XXN_A0 | ROC_MODEL_CN98xx_A0)\n+\n+/* Runtime variants */\n+static inline uint64_t\n+roc_model_runtime_is_cn9k(void)\n+{\n+\treturn (roc_model->flag & (ROC_MODEL_CN9K));\n+}\n+\n+static inline uint64_t\n+roc_model_runtime_is_cn10k(void)\n+{\n+\treturn (roc_model->flag & (ROC_MODEL_CN10K));\n+}\n+\n+/* Compile time variants */\n+#ifdef ROC_PLATFORM_CN9K\n+#define roc_model_constant_is_cn9k() 1\n+#define roc_model_constant_is_cn10k() 0\n+#else\n+#define roc_model_constant_is_cn9k() 0\n+#define roc_model_constant_is_cn10k() 1\n+#endif\n+\n+/*\n+ * Compile time variants to enable optimized version check when the library\n+ * configured for specific platform version else to fallback to runtime.\n+ */\n+static inline uint64_t\n+roc_model_is_cn9k(void)\n+{\n+#ifdef ROC_PLATFORM_CN9K\n+\treturn 1;\n+#endif\n+#ifdef ROC_PLATFORM_CN10K\n+\treturn 0;\n+#endif\n+\treturn roc_model_runtime_is_cn9k();\n+}\n+\n+static inline uint64_t\n+roc_model_is_cn10k(void)\n+{\n+#ifdef ROC_PLATFORM_CN10K\n+\treturn 1;\n+#endif\n+#ifdef ROC_PLATFORM_CN9K\n+\treturn 0;\n+#endif\n+\treturn roc_model_runtime_is_cn10k();\n+}\n+\n+static inline uint64_t\n+roc_model_is_cn96_A0(void)\n+{\n+\treturn roc_model->flag & ROC_MODEL_CN96xx_A0;\n+}\n+\n+static inline uint64_t\n+roc_model_is_cn96_Ax(void)\n+{\n+\treturn (roc_model->flag & ROC_MODEL_CN96xx_Ax);\n+}\n+\n+static inline uint64_t\n+roc_model_is_cn95_A0(void)\n+{\n+\treturn roc_model->flag & ROC_MODEL_CNF95xx_A0;\n+}\n+\n+int roc_model_init(struct roc_model *model);\n+\n+#endif\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 2c8b91c..072b3e5 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -3,3 +3,24 @@\n */\n \n #include \"roc_api.h\"\n+\n+int\n+plt_init(void)\n+{\n+\tconst struct rte_memzone *mz;\n+\n+\tmz = rte_memzone_lookup(PLT_MODEL_MZ_NAME);\n+\tif (mz == NULL)\n+\t\tmz = rte_memzone_reserve(PLT_MODEL_MZ_NAME,\n+\t\t\t\t\t sizeof(struct roc_model),\n+\t\t\t\t\t SOCKET_ID_ANY, 0);\n+\telse\n+\t\treturn 0;\n+\n+\tif (mz == NULL) {\n+\t\tplt_err(\"Failed to allocate memory for roc_model\");\n+\t\treturn -ENOMEM;\n+\t}\n+\troc_model_init(mz->addr);\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 575a6ac..7477613 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -123,6 +123,13 @@\n \n #define plt_strlcpy rte_strlcpy\n \n+/* Log */\n+#define plt_err(fmt, args...) \\\n+\tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n+#define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt \"\\n\", ##args)\n+#define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt \"\\n\", ##args)\n+#define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt \"\\n\", ##args)\n+\n #ifdef __cplusplus\n #define CNXK_PCI_ID(subsystem_dev, dev)\t\t\t\t\\\n \t{\t\t\t\t\t\t\t\\\n@@ -143,4 +150,7 @@\n \t}\n #endif\n \n+__rte_internal\n+int plt_init(void);\n+\n #endif /* _ROC_PLATFORM_H_ */\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nnew file mode 100644\nindex 0000000..be37c6c\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_PRIV_H_\n+#define _ROC_PRIV_H_\n+\n+/* Utils */\n+#include \"roc_util_priv.h\"\n+\n+#endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_util_priv.h b/drivers/common/cnxk/roc_util_priv.h\nnew file mode 100644\nindex 0000000..f140967\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_util_priv.h\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_UTIL_PRIV_H_\n+#define _ROC_UTIL_PRIV_H_\n+\n+enum util_err_status {\n+\tUTIL_ERR_PARAM = -6000,\n+\tUTIL_ERR_FS,\n+\tUTIL_ERR_INVALID_MODEL,\n+};\n+\n+#endif /* _ROC_UTIL_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nnew file mode 100644\nindex 0000000..bcba7b2\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -0,0 +1,35 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+const char *\n+roc_error_msg_get(int errorcode)\n+{\n+\tconst char *err_msg;\n+\n+\tswitch (errorcode) {\n+\tcase UTIL_ERR_PARAM:\n+\t\terr_msg = \"Invalid parameter\";\n+\t\tbreak;\n+\tcase UTIL_ERR_FS:\n+\t\terr_msg = \"file operation failed\";\n+\t\tbreak;\n+\tcase UTIL_ERR_INVALID_MODEL:\n+\t\terr_msg = \"Invalid RoC model\";\n+\t\tbreak;\n+\tdefault:\n+\t\t/**\n+\t\t * Handle general error (as defined in linux errno.h)\n+\t\t */\n+\t\tif (abs(errorcode) < 300)\n+\t\t\terr_msg = strerror(abs(errorcode));\n+\t\telse\n+\t\t\terr_msg = \"Unknown error code\";\n+\t\tbreak;\n+\t}\n+\n+\treturn err_msg;\n+}\ndiff --git a/drivers/common/cnxk/roc_utils.h b/drivers/common/cnxk/roc_utils.h\nnew file mode 100644\nindex 0000000..7b607a5\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_utils.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#ifndef _ROC_UTILS_H_\n+#define _ROC_UTILS_H_\n+\n+#include \"roc_platform.h\"\n+\n+/* Utils */\n+const char *__roc_api roc_error_msg_get(int errorcode);\n+\n+#endif /* _ROC_UTILS_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex dc012a1..227f2ce 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -1,4 +1,9 @@\n INTERNAL {\n+\tglobal:\n+\n+\tplt_init;\n+\troc_error_msg_get;\n+\troc_model;\n \n \tlocal: *;\n };\n", "prefixes": [ "03/52" ] }