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GET /api/patches/88455/?format=api
{ "id": 88455, "url": "http://patches.dpdk.org/api/patches/88455/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1614843894-43845-10-git-send-email-oulijun@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1614843894-43845-10-git-send-email-oulijun@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1614843894-43845-10-git-send-email-oulijun@huawei.com", "date": "2021-03-04T07:44:49", "name": "[V3,09/14] net/hns3: support RXD advanced layout", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a563ae8aaf29b21ed044e91eca777bd76aa8d9f0", "submitter": { "id": 1675, "url": "http://patches.dpdk.org/api/people/1675/?format=api", "name": "Lijun Ou", "email": "oulijun@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1614843894-43845-10-git-send-email-oulijun@huawei.com/mbox/", "series": [ { "id": 15486, "url": "http://patches.dpdk.org/api/series/15486/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15486", "date": "2021-03-04T07:44:40", "name": "Features and bugfixes for hns3", "version": 3, "mbox": "http://patches.dpdk.org/series/15486/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88455/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88455/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE0ECA0561;\n\tThu, 4 Mar 2021 08:45:43 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AB95E22A32A;\n\tThu, 4 Mar 2021 08:44:30 +0100 (CET)", "from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190])\n by mails.dpdk.org (Postfix) with ESMTP id 4F1F822A2C8\n for <dev@dpdk.org>; Thu, 4 Mar 2021 08:44:17 +0100 (CET)", "from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60])\n by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DrjW16x7DzlSYH;\n Thu, 4 Mar 2021 15:42:05 +0800 (CST)", "from localhost.localdomain (10.69.192.56) by\n DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id\n 14.3.498.0; Thu, 4 Mar 2021 15:44:11 +0800" ], "From": "Lijun Ou <oulijun@huawei.com>", "To": "<ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>, <linuxarm@openeuler.org>", "Date": "Thu, 4 Mar 2021 15:44:49 +0800", "Message-ID": "<1614843894-43845-10-git-send-email-oulijun@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1614843894-43845-1-git-send-email-oulijun@huawei.com>", "References": "<1614693534-27620-1-git-send-email-oulijun@huawei.com>\n <1614843894-43845-1-git-send-email-oulijun@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.69.192.56]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH V3 09/14] net/hns3: support RXD advanced layout", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Chengwen Feng <fengchengwen@huawei.com>\n\nCurrently, the driver get packet type by parse the\nL3_ID/L4_ID/OL3_ID/OL4_ID from Rx descriptor and then lookup multiple\ntables, it's time consuming.\n\nNow Kunpeng930 support advanced RXD layout, which:\n1. Combine OL3_ID/OL4_ID to 8bit PTYPE filed, so the driver get packet\ntype by lookup only one table.\nNote: L3_ID/L4_ID become reserved fields.\n2. The 1588 timestamp located at Rx descriptor instead of query from\nfirmware.\n3. The L3E/L4E/OL3E/OL4E will be zero when L3L4P is zero, so driver\ncould optimize the good checksum calculations (when L3E/L4E is zero\nthen mark PKT_RX_IP_CKSUM_GOOD/PKT_RX_L4_CKSUM_GOOD).\n\nConsidering compatibility, the firmware will report capability of\nRXD advanced layout, the driver will identify and enable it by default.\n\nThis patch only provides basic function: identify and enable the RXD\nadvanced layout, and lookup ptype table if supported.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.c | 8 +-\n drivers/net/hns3/hns3_cmd.h | 5 +\n drivers/net/hns3/hns3_ethdev.c | 2 +\n drivers/net/hns3/hns3_ethdev.h | 16 +++\n drivers/net/hns3/hns3_ethdev_vf.c | 2 +\n drivers/net/hns3/hns3_regs.h | 1 +\n drivers/net/hns3/hns3_rxtx.c | 200 ++++++++++++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_rxtx.h | 11 +++\n 8 files changed, 243 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c\nindex 32cd56b..8b9f075 100644\n--- a/drivers/net/hns3/hns3_cmd.c\n+++ b/drivers/net/hns3/hns3_cmd.c\n@@ -409,8 +409,9 @@ hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)\n \treturn retval;\n }\n \n-static void hns3_parse_capability(struct hns3_hw *hw,\n-\t\t\t\t struct hns3_query_version_cmd *cmd)\n+static void\n+hns3_parse_capability(struct hns3_hw *hw,\n+\t\t struct hns3_query_version_cmd *cmd)\n {\n \tuint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);\n \n@@ -429,6 +430,9 @@ static void hns3_parse_capability(struct hns3_hw *hw,\n \t\thns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B, 1);\n \tif (hns3_get_bit(caps, HNS3_CAPS_STASH_B))\n \t\thns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1);\n+\tif (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B))\n+\t\thns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,\n+\t\t\t 1);\n }\n \n static uint32_t\ndiff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex 7f567cb..6ceb655 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -312,6 +312,11 @@ enum HNS3_CAPS_BITS {\n \tHNS3_CAPS_TQP_TXRX_INDEP_B,\n \tHNS3_CAPS_HW_PAD_B,\n \tHNS3_CAPS_STASH_B,\n+\tHNS3_CAPS_UDP_TUNNEL_CSUM_B,\n+\tHNS3_CAPS_RAS_IMP_B,\n+\tHNS3_CAPS_FEC_B,\n+\tHNS3_CAPS_PAUSE_B,\n+\tHNS3_CAPS_RXD_ADV_LAYOUT_B,\n };\n \n enum HNS3_API_CAP_BITS {\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex a97dee4..b3fd331 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -4970,6 +4970,8 @@ hns3_do_start(struct hns3_adapter *hns, bool reset_queue)\n \t\treturn ret;\n \t}\n \n+\thns3_enable_rxd_adv_layout(hw);\n+\n \tret = hns3_init_queues(hns, reset_queue);\n \tif (ret) {\n \t\tPMD_INIT_LOG(ERR, \"failed to init queues, ret = %d.\", ret);\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex c495802..932600d 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -667,8 +667,13 @@ struct hns3_mp_param {\n #define HNS3_OL2TBL_NUM\t4\n #define HNS3_OL3TBL_NUM\t16\n #define HNS3_OL4TBL_NUM\t16\n+#define HNS3_PTYPE_NUM\t256\n \n struct hns3_ptype_table {\n+\t/*\n+\t * The next fields used to calc packet-type by the\n+\t * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.\n+\t */\n \tuint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];\n \tuint32_t l4table[HNS3_L4TBL_NUM];\n \tuint32_t inner_l2table[HNS3_L2TBL_NUM];\n@@ -677,6 +682,13 @@ struct hns3_ptype_table {\n \tuint32_t ol2table[HNS3_OL2TBL_NUM];\n \tuint32_t ol3table[HNS3_OL3TBL_NUM];\n \tuint32_t ol4table[HNS3_OL4TBL_NUM];\n+\n+\t/*\n+\t * The next field used to calc packet-type by the PTYPE from the Rx\n+\t * descriptor, it functions only when firmware report the capability of\n+\t * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.\n+\t */\n+\tuint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;\n };\n \n #define HNS3_FIXED_MAX_TQP_NUM_MODE\t\t0\n@@ -771,6 +783,7 @@ struct hns3_adapter {\n #define HNS3_DEV_SUPPORT_TX_PUSH_B\t\t0x5\n #define HNS3_DEV_SUPPORT_INDEP_TXRX_B\t\t0x6\n #define HNS3_DEV_SUPPORT_STASH_B\t\t0x7\n+#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B\t0x9\n \n #define hns3_dev_dcb_supported(hw) \\\n \thns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)\n@@ -801,6 +814,9 @@ struct hns3_adapter {\n #define hns3_dev_stash_supported(hw) \\\n \thns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)\n \n+#define hns3_dev_rxd_adv_layout_supported(hw) \\\n+\thns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B)\n+\n #define HNS3_DEV_PRIVATE_TO_HW(adapter) \\\n \t(&((struct hns3_adapter *)adapter)->hw)\n #define HNS3_DEV_PRIVATE_TO_PF(adapter) \\\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 1b8c029..e7f6974 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -2125,6 +2125,8 @@ hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)\n \tif (ret)\n \t\treturn ret;\n \n+\thns3_enable_rxd_adv_layout(hw);\n+\n \tret = hns3_init_queues(hns, reset_queue);\n \tif (ret)\n \t\thns3_err(hw, \"failed to init queues, ret = %d.\", ret);\ndiff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h\nindex 39fc5d1..0540554 100644\n--- a/drivers/net/hns3/hns3_regs.h\n+++ b/drivers/net/hns3/hns3_regs.h\n@@ -36,6 +36,7 @@\n #define HNS3_GLOBAL_RESET_REG\t\t0x20A00\n #define HNS3_FUN_RST_ING\t\t0x20C00\n #define HNS3_GRO_EN_REG\t\t\t0x28000\n+#define HNS3_RXD_ADV_LAYOUT_EN_REG\t0x28008\n \n /* Vector0 register bits for reset */\n #define HNS3_VECTOR0_FUNCRESET_INT_B\t0\ndiff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex 2099006..00167c4 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -1802,6 +1802,7 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,\n \t\t\t\t HNS3_PORT_BASE_VLAN_ENABLE;\n \telse\n \t\trxq->pvid_sw_discard_en = false;\n+\trxq->ptype_en = hns3_dev_rxd_adv_layout_supported(hw) ? true : false;\n \trxq->configured = true;\n \trxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +\n \t\t\t\tidx * HNS3_TQP_REG_SIZE);\n@@ -1987,6 +1988,193 @@ hns3_init_tunnel_ptype_tbl(struct hns3_ptype_table *tbl)\n \ttbl->ol4table[2] = RTE_PTYPE_TUNNEL_NVGRE;\n }\n \n+static void\n+hns3_init_adv_layout_ptype(struct hns3_ptype_table *tbl)\n+{\n+\tuint32_t *ptype = tbl->ptype;\n+\n+\t/* Non-tunnel L2 */\n+\tptype[1] = RTE_PTYPE_L2_ETHER_ARP;\n+\tptype[3] = RTE_PTYPE_L2_ETHER_LLDP;\n+\tptype[8] = RTE_PTYPE_L2_ETHER_TIMESYNC;\n+\n+\t/* Non-tunnel IPv4 */\n+\tptype[17] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_FRAG;\n+\tptype[18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_NONFRAG;\n+\tptype[19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_UDP;\n+\tptype[20] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_TCP;\n+\t/* The next ptype is GRE over IPv4 */\n+\tptype[21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;\n+\tptype[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_SCTP;\n+\tptype[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_IGMP;\n+\tptype[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_ICMP;\n+\t/* The next ptype is PTP over IPv4 + UDP */\n+\tptype[25] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_UDP;\n+\n+\t/* IPv4 --> GRE/Teredo/VXLAN */\n+\tptype[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT;\n+\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC */\n+\tptype[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;\n+\n+\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */\n+\tptype[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_FRAG;\n+\tptype[32] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_NONFRAG;\n+\tptype[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_UDP;\n+\tptype[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_TCP;\n+\tptype[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_SCTP;\n+\t/* The next ptype's inner L4 is IGMP */\n+\tptype[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;\n+\tptype[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_ICMP;\n+\n+\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */\n+\tptype[39] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_FRAG;\n+\tptype[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_NONFRAG;\n+\tptype[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_UDP;\n+\tptype[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_TCP;\n+\tptype[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_SCTP;\n+\t/* The next ptype's inner L4 is IGMP */\n+\tptype[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;\n+\tptype[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_ICMP;\n+\n+\t/* Non-tunnel IPv6 */\n+\tptype[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_FRAG;\n+\tptype[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_NONFRAG;\n+\tptype[113] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_UDP;\n+\tptype[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_TCP;\n+\t/* The next ptype is GRE over IPv6 */\n+\tptype[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;\n+\tptype[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_SCTP;\n+\tptype[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_IGMP;\n+\tptype[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_ICMP;\n+\t/* Special for PTP over IPv6 + UDP */\n+\tptype[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_L4_UDP;\n+\n+\t/* IPv6 --> GRE/Teredo/VXLAN */\n+\tptype[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT;\n+\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC */\n+\tptype[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER;\n+\n+\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */\n+\tptype[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_FRAG;\n+\tptype[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_NONFRAG;\n+\tptype[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_UDP;\n+\tptype[128] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_TCP;\n+\tptype[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_SCTP;\n+\t/* The next ptype's inner L4 is IGMP */\n+\tptype[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;\n+\tptype[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_ICMP;\n+\n+\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */\n+\tptype[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_FRAG;\n+\tptype[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_NONFRAG;\n+\tptype[135] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_UDP;\n+\tptype[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_TCP;\n+\tptype[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_SCTP;\n+\t/* The next ptype's inner L4 is IGMP */\n+\tptype[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;\n+\tptype[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n+\t\t RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n+\t\t RTE_PTYPE_INNER_L4_ICMP;\n+}\n+\n void\n hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)\n {\n@@ -1997,6 +2185,7 @@ hns3_init_rx_ptype_tble(struct rte_eth_dev *dev)\n \n \thns3_init_non_tunnel_ptype_tbl(tbl);\n \thns3_init_tunnel_ptype_tbl(tbl);\n+\thns3_init_adv_layout_ptype(tbl);\n }\n \n static inline void\n@@ -4012,3 +4201,14 @@ hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \telse\n \t\treturn fbd_num - driver_hold_bd_num;\n }\n+\n+void\n+hns3_enable_rxd_adv_layout(struct hns3_hw *hw)\n+{\n+\t/*\n+\t * If the hardware support rxd advanced layout, then driver enable it\n+\t * default.\n+\t */\n+\tif (hns3_dev_rxd_adv_layout_supported(hw))\n+\t\thns3_write_dev(hw, HNS3_RXD_ADV_LAYOUT_EN_REG, 1);\n+}\ndiff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h\nindex 7118bd4..9adeb24 100644\n--- a/drivers/net/hns3/hns3_rxtx.h\n+++ b/drivers/net/hns3/hns3_rxtx.h\n@@ -88,6 +88,8 @@\n #define HNS3_RXD_OL3ID_M\t\t\t(0xf << HNS3_RXD_OL3ID_S)\n #define HNS3_RXD_OL4ID_S\t\t\t8\n #define HNS3_RXD_OL4ID_M\t\t\t(0xf << HNS3_RXD_OL4ID_S)\n+#define HNS3_RXD_PTYPE_S\t\t\t4\n+#define HNS3_RXD_PTYPE_M\t\t\t(0xff << HNS3_RXD_PTYPE_S)\n #define HNS3_RXD_FBHI_S\t\t\t\t12\n #define HNS3_RXD_FBHI_M\t\t\t\t(0x3 << HNS3_RXD_FBHI_S)\n #define HNS3_RXD_FBLI_S\t\t\t\t14\n@@ -328,6 +330,7 @@ struct hns3_rx_queue {\n \t * point, the pvid_sw_discard_en will be false.\n \t */\n \tbool pvid_sw_discard_en;\n+\tbool ptype_en; /* indicate if the ptype field enabled */\n \tbool enabled; /* indicate if Rx queue has been enabled */\n \n \tstruct hns3_rx_basic_stats basic_stats;\n@@ -609,6 +612,13 @@ hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info,\n \tconst struct hns3_ptype_table * const ptype_tbl = rxq->ptype_tbl;\n \tuint32_t l2id, l3id, l4id;\n \tuint32_t ol3id, ol4id, ol2id;\n+\tuint32_t ptype;\n+\n+\tif (rxq->ptype_en) {\n+\t\tptype = hns3_get_field(ol_info, HNS3_RXD_PTYPE_M,\n+\t\t\t\t HNS3_RXD_PTYPE_S);\n+\t\treturn ptype_tbl->ptype[ptype];\n+\t}\n \n \tol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);\n \tol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);\n@@ -707,5 +717,6 @@ int hns3_start_all_rxqs(struct rte_eth_dev *dev);\n void hns3_stop_all_txqs(struct rte_eth_dev *dev);\n void hns3_restore_tqp_enable_state(struct hns3_hw *hw);\n int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt);\n+void hns3_enable_rxd_adv_layout(struct hns3_hw *hw);\n \n #endif /* _HNS3_RXTX_H_ */\n", "prefixes": [ "V3", "09/14" ] }