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GET /api/patches/88451/?format=api
{ "id": 88451, "url": "http://patches.dpdk.org/api/patches/88451/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1614843894-43845-3-git-send-email-oulijun@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1614843894-43845-3-git-send-email-oulijun@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1614843894-43845-3-git-send-email-oulijun@huawei.com", "date": "2021-03-04T07:44:42", "name": "[V3,02/14] net/hns3: add more registers to dump", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5737fd601ab821432060cf83bfae23e32dfc92a8", "submitter": { "id": 1675, "url": "http://patches.dpdk.org/api/people/1675/?format=api", "name": "Lijun Ou", "email": "oulijun@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1614843894-43845-3-git-send-email-oulijun@huawei.com/mbox/", "series": [ { "id": 15486, "url": "http://patches.dpdk.org/api/series/15486/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15486", "date": "2021-03-04T07:44:40", "name": "Features and bugfixes for hns3", "version": 3, "mbox": "http://patches.dpdk.org/series/15486/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88451/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88451/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5FEDEA0561;\n\tThu, 4 Mar 2021 08:45:14 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 099E522A2F3;\n\tThu, 4 Mar 2021 08:44:26 +0100 (CET)", "from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190])\n by mails.dpdk.org (Postfix) with ESMTP id 4B8E522A2C7\n for <dev@dpdk.org>; Thu, 4 Mar 2021 08:44:17 +0100 (CET)", "from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60])\n by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DrjW205cSzlSLM;\n Thu, 4 Mar 2021 15:42:06 +0800 (CST)", "from localhost.localdomain (10.69.192.56) by\n DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id\n 14.3.498.0; Thu, 4 Mar 2021 15:44:09 +0800" ], "From": "Lijun Ou <oulijun@huawei.com>", "To": "<ferruh.yigit@intel.com>", "CC": "<dev@dpdk.org>, <linuxarm@openeuler.org>", "Date": "Thu, 4 Mar 2021 15:44:42 +0800", "Message-ID": "<1614843894-43845-3-git-send-email-oulijun@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1614843894-43845-1-git-send-email-oulijun@huawei.com>", "References": "<1614693534-27620-1-git-send-email-oulijun@huawei.com>\n <1614843894-43845-1-git-send-email-oulijun@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.69.192.56]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH V3 02/14] net/hns3: add more registers to dump", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Chengchang Tang <tangchengchang@huawei.com>\n\nThis patch makes more registers dumped in the dump_reg API to help\nloacte the fault.\n\nSigned-off-by: Chengchang Tang <tangchengchang@huawei.com>\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.h | 13 ++++\n drivers/net/hns3/hns3_regs.c | 171 ++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 180 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex ff424a0..2e23f99 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -95,6 +95,19 @@ enum hns3_opcode_type {\n \tHNS3_OPC_QUERY_REG_NUM = 0x0040,\n \tHNS3_OPC_QUERY_32_BIT_REG = 0x0041,\n \tHNS3_OPC_QUERY_64_BIT_REG = 0x0042,\n+\tHNS3_OPC_DFX_BD_NUM = 0x0043,\n+\tHNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044,\n+\tHNS3_OPC_DFX_SSU_REG_0 = 0x0045,\n+\tHNS3_OPC_DFX_SSU_REG_1 = 0x0046,\n+\tHNS3_OPC_DFX_IGU_EGU_REG = 0x0047,\n+\tHNS3_OPC_DFX_RPU_REG_0 = 0x0048,\n+\tHNS3_OPC_DFX_RPU_REG_1 = 0x0049,\n+\tHNS3_OPC_DFX_NCSI_REG = 0x004A,\n+\tHNS3_OPC_DFX_RTC_REG = 0x004B,\n+\tHNS3_OPC_DFX_PPP_REG = 0x004C,\n+\tHNS3_OPC_DFX_RCB_REG = 0x004D,\n+\tHNS3_OPC_DFX_TQP_REG = 0x004E,\n+\tHNS3_OPC_DFX_SSU_REG_2 = 0x004F,\n \n \tHNS3_OPC_QUERY_DEV_SPECS = 0x0050,\n \ndiff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c\nindex 84f3157..4022bb9 100644\n--- a/drivers/net/hns3/hns3_regs.c\n+++ b/drivers/net/hns3/hns3_regs.c\n@@ -15,6 +15,8 @@\n #define REG_NUM_PER_LINE\t4\n #define REG_LEN_PER_LINE\t(REG_NUM_PER_LINE * sizeof(uint32_t))\n \n+static int hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *length);\n+\n static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,\n \t\t\t\t\t HNS3_CMDQ_TX_ADDR_H_REG,\n \t\t\t\t\t HNS3_CMDQ_TX_DEPTH_REG,\n@@ -77,6 +79,21 @@ static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,\n \t\t\t\t\t HNS3_TQP_INTR_GL2_REG,\n \t\t\t\t\t HNS3_TQP_INTR_RL_REG};\n \n+static const uint32_t hns3_dfx_reg_opcode_list[] = {\n+\tHNS3_OPC_DFX_BIOS_COMMON_REG,\n+\tHNS3_OPC_DFX_SSU_REG_0,\n+\tHNS3_OPC_DFX_SSU_REG_1,\n+\tHNS3_OPC_DFX_IGU_EGU_REG,\n+\tHNS3_OPC_DFX_RPU_REG_0,\n+\tHNS3_OPC_DFX_RPU_REG_1,\n+\tHNS3_OPC_DFX_NCSI_REG,\n+\tHNS3_OPC_DFX_RTC_REG,\n+\tHNS3_OPC_DFX_PPP_REG,\n+\tHNS3_OPC_DFX_RCB_REG,\n+\tHNS3_OPC_DFX_TQP_REG,\n+\tHNS3_OPC_DFX_SSU_REG_2\n+};\n+\n static int\n hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,\n \t\t uint32_t *regs_num_64_bit)\n@@ -123,14 +140,21 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)\n \tif (!hns->is_vf) {\n \t\tret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);\n \t\tif (ret) {\n-\t\t\thns3_err(hw, \"Get register number failed, ret = %d.\",\n-\t\t\t\t ret);\n-\t\t\treturn -ENOTSUP;\n+\t\t\thns3_err(hw, \"fail to get the number of registers, \"\n+\t\t\t\t \"ret = %d.\", ret);\n+\t\t\treturn ret;\n \t\t}\n \t\tdfx_reg_lines = regs_num_32_bit * sizeof(uint32_t) /\n \t\t\t\t\tREG_LEN_PER_LINE + 1;\n \t\tdfx_reg_lines += regs_num_64_bit * sizeof(uint64_t) /\n \t\t\t\t\tREG_LEN_PER_LINE + 1;\n+\n+\t\tret = hns3_get_dfx_reg_line(hw, &dfx_reg_lines);\n+\t\tif (ret) {\n+\t\t\thns3_err(hw, \"fail to get the number of dfx registers, \"\n+\t\t\t\t \"ret = %d.\", ret);\n+\t\t\treturn ret;\n+\t\t}\n \t\tlen += dfx_reg_lines * REG_NUM_PER_LINE;\n \t}\n \n@@ -310,6 +334,144 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)\n \treturn data - origin_data_ptr;\n }\n \n+static int\n+hns3_get_dfx_reg_bd_num(struct hns3_hw *hw, uint32_t *bd_num_list,\n+\t\t\tuint32_t list_size)\n+{\n+#define HNS3_GET_DFX_REG_BD_NUM_SIZE\t4\n+\tstruct hns3_cmd_desc desc[HNS3_GET_DFX_REG_BD_NUM_SIZE];\n+\tuint32_t index, desc_index;\n+\tuint32_t bd_num;\n+\tuint32_t i;\n+\tint ret;\n+\n+\tfor (i = 0; i < HNS3_GET_DFX_REG_BD_NUM_SIZE - 1; i++) {\n+\t\thns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true);\n+\t\tdesc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\t}\n+\t/* The last BD does not need a next flag */\n+\thns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_DFX_BD_NUM, true);\n+\n+\tret = hns3_cmd_send(hw, desc, HNS3_GET_DFX_REG_BD_NUM_SIZE);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to get dfx bd num, ret = %d.\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* The first data in the first BD is a reserved field */\n+\tfor (i = 1; i <= list_size; i++) {\n+\t\tdesc_index = i / HNS3_CMD_DESC_DATA_NUM;\n+\t\tindex = i % HNS3_CMD_DESC_DATA_NUM;\n+\t\tbd_num = rte_le_to_cpu_32(desc[desc_index].data[index]);\n+\t\tbd_num_list[i - 1] = bd_num;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3_dfx_reg_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc,\n+\t\t\tint bd_num, uint32_t opcode)\n+{\n+\tint ret;\n+\tint i;\n+\n+\tfor (i = 0; i < bd_num - 1; i++) {\n+\t\thns3_cmd_setup_basic_desc(&desc[i], opcode, true);\n+\t\tdesc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\t}\n+\t/* The last BD does not need a next flag */\n+\thns3_cmd_setup_basic_desc(&desc[i], opcode, true);\n+\n+\tret = hns3_cmd_send(hw, desc, bd_num);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to query dfx registers, opcode = 0x%04X, \"\n+\t\t\t \"ret = %d.\\n\", opcode, ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3_dfx_reg_fetch_data(struct hns3_cmd_desc *desc, int bd_num, uint32_t *reg)\n+{\n+\tint desc_index;\n+\tint reg_num;\n+\tint index;\n+\tint i;\n+\n+\treg_num = bd_num * HNS3_CMD_DESC_DATA_NUM;\n+\tfor (i = 0; i < reg_num; i++) {\n+\t\tdesc_index = i / HNS3_CMD_DESC_DATA_NUM;\n+\t\tindex = i % HNS3_CMD_DESC_DATA_NUM;\n+\t\t*reg++ = desc[desc_index].data[index];\n+\t}\n+\treg_num += hns3_insert_reg_separator(reg_num, reg);\n+\n+\treturn reg_num;\n+}\n+\n+static int\n+hns3_get_dfx_reg_line(struct hns3_hw *hw, uint32_t *lines)\n+{\n+\tint opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);\n+\tuint32_t bd_num_list[opcode_num];\n+\tuint32_t bd_num, data_len;\n+\tint ret;\n+\tint i;\n+\n+\tret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < opcode_num; i++) {\n+\t\tbd_num = bd_num_list[i];\n+\t\tdata_len = bd_num * HNS3_CMD_DESC_DATA_NUM * sizeof(uint32_t);\n+\t\t*lines += data_len / REG_LEN_PER_LINE + 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3_get_dfx_regs(struct hns3_hw *hw, void **data)\n+{\n+\tint opcode_num = RTE_DIM(hns3_dfx_reg_opcode_list);\n+\tuint32_t max_bd_num, bd_num, opcode;\n+\tuint32_t bd_num_list[opcode_num];\n+\tstruct hns3_cmd_desc *cmd_descs;\n+\tuint32_t *reg_val = (uint32_t *)*data;\n+\tint ret;\n+\tint i;\n+\n+\tret = hns3_get_dfx_reg_bd_num(hw, bd_num_list, opcode_num);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmax_bd_num = 0;\n+\tfor (i = 0; i < opcode_num; i++)\n+\t\tmax_bd_num = RTE_MAX(bd_num_list[i], max_bd_num);\n+\n+\tcmd_descs = rte_zmalloc(NULL, sizeof(*cmd_descs) * max_bd_num, 0);\n+\tif (cmd_descs == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i < opcode_num; i++) {\n+\t\topcode = hns3_dfx_reg_opcode_list[i];\n+\t\tbd_num = bd_num_list[i];\n+\t\tif (bd_num == 0)\n+\t\t\tcontinue;\n+\t\tret = hns3_dfx_reg_cmd_send(hw, cmd_descs, bd_num, opcode);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t\treg_val += hns3_dfx_reg_fetch_data(cmd_descs, bd_num, reg_val);\n+\t}\n+\trte_free(cmd_descs);\n+\t*data = (void *)reg_val;\n+\n+\treturn ret;\n+}\n+\n int\n hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n {\n@@ -371,5 +533,6 @@ hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n \tdata += regs_num_64_bit * HNS3_64_BIT_REG_SIZE;\n \tdata += hns3_insert_reg_separator(regs_num_64_bit *\n \t\t\t\t\t HNS3_64_BIT_REG_SIZE, data);\n-\treturn ret;\n+\n+\treturn hns3_get_dfx_regs(hw, (void **)&data);\n }\n", "prefixes": [ "V3", "02/14" ] }