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GET /api/patches/88446/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 88446,
    "url": "http://patches.dpdk.org/api/patches/88446/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1614843894-43845-14-git-send-email-oulijun@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1614843894-43845-14-git-send-email-oulijun@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1614843894-43845-14-git-send-email-oulijun@huawei.com",
    "date": "2021-03-04T07:44:53",
    "name": "[V3,13/14] net/hns3: add process for MAC interrupt",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "f3aa840fef4f17ae0589d8250f181158e78b3998",
    "submitter": {
        "id": 1675,
        "url": "http://patches.dpdk.org/api/people/1675/?format=api",
        "name": "Lijun Ou",
        "email": "oulijun@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1614843894-43845-14-git-send-email-oulijun@huawei.com/mbox/",
    "series": [
        {
            "id": 15486,
            "url": "http://patches.dpdk.org/api/series/15486/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15486",
            "date": "2021-03-04T07:44:40",
            "name": "Features and bugfixes for hns3",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/15486/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/88446/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/88446/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C2485A0561;\n\tThu,  4 Mar 2021 08:44:33 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 98D8E22A2CE;\n\tThu,  4 Mar 2021 08:44:19 +0100 (CET)",
            "from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190])\n by mails.dpdk.org (Postfix) with ESMTP id E1A914069B\n for <dev@dpdk.org>; Thu,  4 Mar 2021 08:44:15 +0100 (CET)",
            "from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60])\n by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DrjW14V8HzlQKF;\n Thu,  4 Mar 2021 15:42:05 +0800 (CST)",
            "from localhost.localdomain (10.69.192.56) by\n DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id\n 14.3.498.0; Thu, 4 Mar 2021 15:44:12 +0800"
        ],
        "From": "Lijun Ou <oulijun@huawei.com>",
        "To": "<ferruh.yigit@intel.com>",
        "CC": "<dev@dpdk.org>, <linuxarm@openeuler.org>",
        "Date": "Thu, 4 Mar 2021 15:44:53 +0800",
        "Message-ID": "<1614843894-43845-14-git-send-email-oulijun@huawei.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1614843894-43845-1-git-send-email-oulijun@huawei.com>",
        "References": "<1614693534-27620-1-git-send-email-oulijun@huawei.com>\n <1614843894-43845-1-git-send-email-oulijun@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.69.192.56]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH V3 13/14] net/hns3: add process for MAC interrupt",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Hongbo Zheng <zhenghongbo3@huawei.com>\n\nTNL is the abbreviation of tunnel, which means port\nhere. MAC TNL interrupt indicates the MAC status\nreport of the network port, which will be generated\nwhen the MAC status changes.\n\nThis patch enables MAC TNL interrupt reporting, and\nqueries and prints the corresponding MAC status when\nthe interrupt is received, then clear the MAC interrupt\nstatus. Because this interrupt uses the same interrupt\nas RAS, the interrupt log is adjusted.\n\nSigned-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\nV1->V2:\n- add more information for commit log\n---\n drivers/net/hns3/hns3_cmd.h    |  3 +++\n drivers/net/hns3/hns3_ethdev.c | 57 ++++++++++++++++++++++++++++++++++++------\n drivers/net/hns3/hns3_intr.c   | 20 +++++++++++++++\n drivers/net/hns3/hns3_intr.h   |  4 +++\n 4 files changed, 76 insertions(+), 8 deletions(-)",
    "diff": "diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex 6ceb655..094bf7e 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -116,6 +116,9 @@ enum hns3_opcode_type {\n \tHNS3_OPC_QUERY_LINK_STATUS      = 0x0307,\n \tHNS3_OPC_CONFIG_MAX_FRM_SIZE    = 0x0308,\n \tHNS3_OPC_CONFIG_SPEED_DUP       = 0x0309,\n+\tHNS3_OPC_QUERY_MAC_TNL_INT      = 0x0310,\n+\tHNS3_OPC_MAC_TNL_INT_EN         = 0x0311,\n+\tHNS3_OPC_CLEAR_MAC_TNL_INT      = 0x0312,\n \tHNS3_OPC_CONFIG_FEC_MODE        = 0x031A,\n \n \t/* PFC/Pause commands */\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 8300fea..9cbcc13 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -217,9 +217,6 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \t\tgoto out;\n \t}\n \n-\tif (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))\n-\t\thns3_warn(hw, \"vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x\",\n-\t\t\t  vector0_int_stats, cmdq_src_val, hw_err_src_reg);\n \tval = vector0_int_stats;\n \tret = HNS3_VECTOR0_EVENT_OTHER;\n out:\n@@ -258,6 +255,34 @@ hns3_clear_all_event_cause(struct hns3_hw *hw)\n }\n \n static void\n+hns3_handle_mac_tnl(struct hns3_hw *hw)\n+{\n+\tstruct hns3_cmd_desc desc;\n+\tuint32_t status;\n+\tint ret;\n+\n+\t/* query and clear mac tnl interruptions */\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret) {\n+\t\thns3_err(hw, \"failed to query mac tnl int, ret = %d.\", ret);\n+\t\treturn;\n+\t}\n+\n+\tstatus = rte_le_to_cpu_32(desc.data[0]);\n+\tif (status) {\n+\t\thns3_warn(hw, \"mac tnl int occurs, status = 0x%x.\", status);\n+\t\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,\n+\t\t\t\t\t  false);\n+\t\tdesc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);\n+\t\tret = hns3_cmd_send(hw, &desc, 1);\n+\t\tif (ret)\n+\t\t\thns3_err(hw, \"failed to clear mac tnl int, ret = %d.\",\n+\t\t\t\t ret);\n+\t}\n+}\n+\n+static void\n hns3_interrupt_handler(void *param)\n {\n \tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n@@ -265,24 +290,36 @@ hns3_interrupt_handler(void *param)\n \tstruct hns3_hw *hw = &hns->hw;\n \tenum hns3_evt_cause event_cause;\n \tuint32_t clearval = 0;\n+\tuint32_t vector0_int;\n+\tuint32_t ras_int;\n+\tuint32_t cmdq_int;\n \n \t/* Disable interrupt */\n \thns3_pf_disable_irq0(hw);\n \n \tevent_cause = hns3_check_event_cause(hns, &clearval);\n+\tvector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);\n+\tras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);\n+\tcmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);\n \t/* vector 0 interrupt is shared with reset and mailbox source events. */\n \tif (event_cause == HNS3_VECTOR0_EVENT_ERR) {\n-\t\thns3_warn(hw, \"Received err interrupt\");\n+\t\thns3_warn(hw, \"received interrupt: vector0_int_stat:0x%x \"\n+\t\t\t  \"ras_int_stat:0x%x cmdq_int_stat:0x%x\",\n+\t\t\t  vector0_int, ras_int, cmdq_int);\n \t\thns3_handle_msix_error(hns, &hw->reset.request);\n \t\thns3_handle_ras_error(hns, &hw->reset.request);\n+\t\thns3_handle_mac_tnl(hw);\n \t\thns3_schedule_reset(hns);\n \t} else if (event_cause == HNS3_VECTOR0_EVENT_RST) {\n-\t\thns3_warn(hw, \"Received reset interrupt\");\n+\t\thns3_warn(hw, \"received reset interrupt\");\n \t\thns3_schedule_reset(hns);\n-\t} else if (event_cause == HNS3_VECTOR0_EVENT_MBX)\n+\t} else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {\n \t\thns3_dev_handle_mbx_msg(hw);\n-\telse\n-\t\thns3_err(hw, \"Received unknown event\");\n+\t} else {\n+\t\thns3_warn(hw, \"received unknown event: vector0_int_stat:0x%x \"\n+\t\t\t  \"ras_int_stat:0x%x cmdq_int_stat:0x%x\",\n+\t\t\t  vector0_int, ras_int, cmdq_int);\n+\t}\n \n \thns3_clear_event_cause(hw, event_cause, clearval);\n \t/* Enable interrupt if it is not cause by reset */\n@@ -4639,6 +4676,8 @@ hns3_update_link_status(struct hns3_hw *hw)\n \tif (state != hw->mac.link_status) {\n \t\thw->mac.link_status = state;\n \t\thns3_warn(hw, \"Link status change to %s!\", state ? \"up\" : \"down\");\n+\t\thns3_config_mac_tnl_int(hw,\n+\t\t\t\t\tstate == ETH_LINK_UP ? true : false);\n \t\treturn true;\n \t}\n \n@@ -4957,6 +4996,7 @@ hns3_uninit_pf(struct rte_eth_dev *eth_dev)\n \t(void)hns3_firmware_compat_config(hw, false);\n \thns3_uninit_umv_space(hw);\n \thns3_tqp_stats_uninit(hw);\n+\thns3_config_mac_tnl_int(hw, false);\n \thns3_pf_disable_irq0(hw);\n \trte_intr_disable(&pci_dev->intr_handle);\n \thns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,\n@@ -5282,6 +5322,7 @@ hns3_dev_stop(struct rte_eth_dev *dev)\n \trte_spinlock_lock(&hw->lock);\n \tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {\n \t\thns3_tm_dev_stop_proc(hw);\n+\t\thns3_config_mac_tnl_int(hw, false);\n \t\thns3_stop_tqps(hw);\n \t\thns3_do_stop(hns);\n \t\thns3_unmap_rx_interrupt(dev);\ndiff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c\nindex 88ce4c6..2563504 100644\n--- a/drivers/net/hns3/hns3_intr.c\n+++ b/drivers/net/hns3/hns3_intr.c\n@@ -1248,6 +1248,26 @@ enable_ssu_err_intr(struct hns3_adapter *hns, bool en)\n \treturn ret;\n }\n \n+void\n+hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en)\n+{\n+\tstruct hns3_cmd_desc desc;\n+\tint ret;\n+\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_TNL_INT_EN, false);\n+\tif (en)\n+\t\tdesc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN);\n+\telse\n+\t\tdesc.data[0] = 0;\n+\n+\tdesc.data[1] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN_MASK);\n+\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret)\n+\t\thns3_err(hw, \"fail to %s mac tnl intr, ret = %d\",\n+\t\t\t en ? \"enable\" : \"disable\", ret);\n+}\n+\n static int\n config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)\n {\ndiff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h\nindex 19de1aa..c569a9d 100644\n--- a/drivers/net/hns3/hns3_intr.h\n+++ b/drivers/net/hns3/hns3_intr.h\n@@ -22,6 +22,9 @@\n \n #define HNS3_MAC_COMMON_ERR_INT_EN\t\t0x107FF\n #define HNS3_MAC_COMMON_ERR_INT_EN_MASK\t\t0x107FF\n+#define HNS3_MAC_TNL_INT_EN\t\t\tGENMASK(9, 0)\n+#define HNS3_MAC_TNL_INT_EN_MASK\t\tGENMASK(9, 0)\n+#define HNS3_MAC_TNL_INT_CLR\t\t\tGENMASK(9, 0)\n \n #define HNS3_IMP_TCM_ECC_ERR_INT_EN\t\t0xFFFF0000\n #define HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK\t0xFFFF0000\n@@ -99,6 +102,7 @@ struct hns3_hw_error_desc {\n int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);\n void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);\n void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);\n+void hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en);\n \n void hns3_intr_unregister(const struct rte_intr_handle *hdl,\n \t\t\t  rte_intr_callback_fn cb_fn, void *cb_arg);\n",
    "prefixes": [
        "V3",
        "13/14"
    ]
}