Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 88036,
    "url": "http://patches.dpdk.org/api/patches/88036/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210220220957.4583-7-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210220220957.4583-7-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210220220957.4583-7-pbhagavatula@marvell.com",
    "date": "2021-02-20T22:09:55",
    "name": "[6/7] app/eventdev: add event vector mode in pipeline test",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ae5a0db469ef9e98a97b8c8e13cd3a90e2e8d669",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210220220957.4583-7-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 15316,
            "url": "http://patches.dpdk.org/api/series/15316/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15316",
            "date": "2021-02-20T22:09:49",
            "name": "Introduce event vectorization",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/15316/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/88036/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/88036/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 81DE9A0524;\n\tSat, 20 Feb 2021 23:10:55 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BD9D822A24F;\n\tSat, 20 Feb 2021 23:10:42 +0100 (CET)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 1080640696\n for <dev@dpdk.org>; Sat, 20 Feb 2021 23:10:40 +0100 (CET)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 11KM8QXc006956; Sat, 20 Feb 2021 14:10:40 -0800",
            "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 36u0nw8vvp-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 20 Feb 2021 14:10:40 -0800",
            "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 20 Feb 2021 14:10:38 -0800",
            "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 20 Feb 2021 14:10:38 -0800",
            "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 20 Feb 2021 14:10:38 -0800",
            "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 460783F7043;\n Sat, 20 Feb 2021 14:10:33 -0800 (PST)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=xg9wk2lqwmUFI7s3H29NDEb1FednsXqh1UD0c/JqDGE=;\n b=dZoZ3aJPej2f3X+Ru8tJhZ9j2L+exPzbWUDDx4tYjWfPnS7J+i69k0xL5hKSMY+kThNa\n Ewu2Z2vgALfE3R66i6Dw7wbck1i0P46SZYE8573RqEze/EMK3h793Jbw5adMKsP1eop9\n gepjdVgkCrjyBHp1T5rMr6vnisP79DBHwCGPSaqXTrUUPRD8EZYV5X50XpMtgBjfhT+6\n AhXkMI1sU3OHTcIi2dQjdqy94T/Hdfln4QRv9shDF/sFIcQsqJeZJF9NI87U7BScyG4i\n DDiXgqTnefgT9SHGn7TSPD06a9znWjGZJQJBjVl1IHjFmO0Df+j2M7BCE9sArrubtujM mw==",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, <jay.jayatheerthan@intel.com>,\n <erik.g.carrillo@intel.com>, <abhinandan.gujjar@intel.com>,\n <timothy.mcdaniel@intel.com>, <hemant.agrawal@nxp.com>,\n <harry.van.haaren@intel.com>, <mattias.ronnblom@ericsson.com>,\n <liang.j.ma@intel.com>",
        "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "Date": "Sun, 21 Feb 2021 03:39:55 +0530",
        "Message-ID": "<20210220220957.4583-7-pbhagavatula@marvell.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210220220957.4583-1-pbhagavatula@marvell.com>",
        "References": "<20210220220957.4583-1-pbhagavatula@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-02-20_03:2021-02-18,\n 2021-02-20 signatures=0",
        "Subject": "[dpdk-dev] [PATCH 6/7] app/eventdev: add event vector mode in\n pipeline test",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd event vector support in pipeline tests. By default this mode\nis disabled, it can be enabled by using the option --enable_vector.\nexample:\n\tdpdk-test-eventdev -l 7-23 -s 0xff00 -- --prod_type_ethdev\n\t--nb_pkts=0 --verbose 2 --test=pipeline_atq --stlist=a\n\t--wlcores=20-23  --enable_vector\n\nAddtional options to configure vector size and vector timeout are\nalso implemented and can be used by specifying --vector_size and\n--vector_tmo_ns\n\nThis patch also adds a new option to set the number of Rx queues\nconfigured per event eth rx adapter.\nexample:\n\tdpdk-test-eventdev -l 7-23 -s 0xff00 -- --prod_type_ethdev\n\t--nb_pkts=0 --verbose 2 --test=pipeline_atq --stlist=a\n\t--wlcores=20-23  --nb_eth_queues 4\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n app/test-eventdev/evt_common.h           |   4 +\n app/test-eventdev/evt_options.c          |  52 ++++\n app/test-eventdev/evt_options.h          |   4 +\n app/test-eventdev/test_pipeline_atq.c    | 310 ++++++++++++++++++++--\n app/test-eventdev/test_pipeline_common.c |  69 ++++-\n app/test-eventdev/test_pipeline_common.h |  18 ++\n app/test-eventdev/test_pipeline_queue.c  | 320 +++++++++++++++++++++--\n doc/guides/tools/testeventdev.rst        |  28 ++\n 8 files changed, 751 insertions(+), 54 deletions(-)",
    "diff": "diff --git a/app/test-eventdev/evt_common.h b/app/test-eventdev/evt_common.h\nindex a1da1cf11..0e228258e 100644\n--- a/app/test-eventdev/evt_common.h\n+++ b/app/test-eventdev/evt_common.h\n@@ -58,16 +58,20 @@ struct evt_options {\n \tuint8_t sched_type_list[EVT_MAX_STAGES];\n \tuint16_t mbuf_sz;\n \tuint16_t wkr_deq_dep;\n+\tuint16_t vector_size;\n+\tuint16_t eth_queues;\n \tuint32_t nb_flows;\n \tuint32_t tx_first;\n \tuint32_t max_pkt_sz;\n \tuint32_t deq_tmo_nsec;\n \tuint32_t q_priority:1;\n \tuint32_t fwd_latency:1;\n+\tuint32_t ena_vector : 1;\n \tuint64_t nb_pkts;\n \tuint64_t nb_timers;\n \tuint64_t expiry_nsec;\n \tuint64_t max_tmo_nsec;\n+\tuint64_t vector_tmo_nsec;\n \tuint64_t timer_tick_nsec;\n \tuint64_t optm_timer_tick_nsec;\n \tenum evt_prod_type prod_type;\ndiff --git a/app/test-eventdev/evt_options.c b/app/test-eventdev/evt_options.c\nindex 0d04ea9f8..0d5540574 100644\n--- a/app/test-eventdev/evt_options.c\n+++ b/app/test-eventdev/evt_options.c\n@@ -34,6 +34,9 @@ evt_options_default(struct evt_options *opt)\n \topt->max_tmo_nsec = 1E5;  /* 100000ns ~100us */\n \topt->expiry_nsec = 1E4;   /* 10000ns ~10us */\n \topt->prod_type = EVT_PROD_TYPE_SYNT;\n+\topt->eth_queues = 1;\n+\topt->vector_size = 64;\n+\topt->vector_tmo_nsec = 100E3;\n }\n \n typedef int (*option_parser_t)(struct evt_options *opt,\n@@ -257,6 +260,43 @@ evt_parse_max_pkt_sz(struct evt_options *opt, const char *arg)\n \treturn ret;\n }\n \n+static int\n+evt_parse_ena_vector(struct evt_options *opt, const char *arg __rte_unused)\n+{\n+\topt->ena_vector = 1;\n+\treturn 0;\n+}\n+\n+static int\n+evt_parse_vector_size(struct evt_options *opt, const char *arg)\n+{\n+\tint ret;\n+\n+\tret = parser_read_uint16(&(opt->vector_size), arg);\n+\n+\treturn ret;\n+}\n+\n+static int\n+evt_parse_vector_tmo_ns(struct evt_options *opt, const char *arg)\n+{\n+\tint ret;\n+\n+\tret = parser_read_uint64(&(opt->vector_tmo_nsec), arg);\n+\n+\treturn ret;\n+}\n+\n+static int\n+evt_parse_eth_queues(struct evt_options *opt, const char *arg)\n+{\n+\tint ret;\n+\n+\tret = parser_read_uint16(&(opt->eth_queues), arg);\n+\n+\treturn ret;\n+}\n+\n static void\n usage(char *program)\n {\n@@ -289,6 +329,10 @@ usage(char *program)\n \t\t\"\\t--expiry_nsec      : event timer expiry ns.\\n\"\n \t\t\"\\t--mbuf_sz          : packet mbuf size.\\n\"\n \t\t\"\\t--max_pkt_sz       : max packet size.\\n\"\n+\t\t\"\\t--nb_eth_queues    : number of ethernet Rx queues.\\n\"\n+\t\t\"\\t--enable_vector    : enable event vectorization.\\n\"\n+\t\t\"\\t--vector_size      : Max vector size.\\n\"\n+\t\t\"\\t--vector_tmo_ns    : Max vector timeout in nanoseconds\\n\"\n \t\t);\n \tprintf(\"available tests:\\n\");\n \tevt_test_dump_names();\n@@ -360,6 +404,10 @@ static struct option lgopts[] = {\n \t{ EVT_EXPIRY_NSEC,         1, 0, 0 },\n \t{ EVT_MBUF_SZ,             1, 0, 0 },\n \t{ EVT_MAX_PKT_SZ,          1, 0, 0 },\n+\t{ EVT_NB_ETH_QUEUES,       1, 0, 0 },\n+\t{ EVT_ENA_VECTOR,          0, 0, 0 },\n+\t{ EVT_VECTOR_SZ,           1, 0, 0 },\n+\t{ EVT_VECTOR_TMO,          1, 0, 0 },\n \t{ EVT_HELP,                0, 0, 0 },\n \t{ NULL,                    0, 0, 0 }\n };\n@@ -394,6 +442,10 @@ evt_opts_parse_long(int opt_idx, struct evt_options *opt)\n \t\t{ EVT_EXPIRY_NSEC, evt_parse_expiry_nsec},\n \t\t{ EVT_MBUF_SZ, evt_parse_mbuf_sz},\n \t\t{ EVT_MAX_PKT_SZ, evt_parse_max_pkt_sz},\n+\t\t{ EVT_NB_ETH_QUEUES, evt_parse_eth_queues},\n+\t\t{ EVT_ENA_VECTOR, evt_parse_ena_vector},\n+\t\t{ EVT_VECTOR_SZ, evt_parse_vector_size},\n+\t\t{ EVT_VECTOR_TMO, evt_parse_vector_tmo_ns},\n \t};\n \n \tfor (i = 0; i < RTE_DIM(parsermap); i++) {\ndiff --git a/app/test-eventdev/evt_options.h b/app/test-eventdev/evt_options.h\nindex 748e54fae..1cea2a3e1 100644\n--- a/app/test-eventdev/evt_options.h\n+++ b/app/test-eventdev/evt_options.h\n@@ -42,6 +42,10 @@\n #define EVT_EXPIRY_NSEC          (\"expiry_nsec\")\n #define EVT_MBUF_SZ              (\"mbuf_sz\")\n #define EVT_MAX_PKT_SZ           (\"max_pkt_sz\")\n+#define EVT_NB_ETH_QUEUES        (\"nb_eth_queues\")\n+#define EVT_ENA_VECTOR           (\"enable_vector\")\n+#define EVT_VECTOR_SZ            (\"vector_size\")\n+#define EVT_VECTOR_TMO           (\"vector_tmo_ns\")\n #define EVT_HELP                 (\"help\")\n \n void evt_options_default(struct evt_options *opt);\ndiff --git a/app/test-eventdev/test_pipeline_atq.c b/app/test-eventdev/test_pipeline_atq.c\nindex 0872b25b5..84dd4f44e 100644\n--- a/app/test-eventdev/test_pipeline_atq.c\n+++ b/app/test-eventdev/test_pipeline_atq.c\n@@ -15,6 +15,8 @@ pipeline_atq_nb_event_queues(struct evt_options *opt)\n \treturn rte_eth_dev_count_avail();\n }\n \n+typedef int (*pipeline_atq_worker_t)(void *arg);\n+\n static __rte_noinline int\n pipeline_atq_worker_single_stage_tx(void *arg)\n {\n@@ -113,6 +115,112 @@ pipeline_atq_worker_single_stage_burst_fwd(void *arg)\n \treturn 0;\n }\n \n+static __rte_noinline int\n+pipeline_atq_worker_single_stage_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\t\tvector_sz = ev.vec->nb_elem;\n+\t\tpipeline_event_tx_vector(dev, port, &ev);\n+\t\tw->processed_pkts += vector_sz;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_atq_worker_single_stage_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tvector_sz = ev.vec->nb_elem;\n+\t\tev.queue_id = tx_queue[ev.vec->port];\n+\t\tev.vec->queue = 0;\n+\t\tpipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\tw->processed_pkts += vector_sz;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_atq_worker_single_stage_burst_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\t\tvector_sz = 0;\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tvector_sz += ev[i].vec->nb_elem;\n+\t\t\tev[i].vec->queue = 0;\n+\t\t}\n+\n+\t\tpipeline_event_tx_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += vector_sz;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_atq_worker_single_stage_burst_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tvector_sz = 0;\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tev[i].queue_id = tx_queue[ev[i].vec->port];\n+\t\t\tev[i].vec->queue = 0;\n+\t\t\tvector_sz += ev[i].vec->nb_elem;\n+\t\t\tpipeline_fwd_event_vector(&ev[i],\n+\t\t\t\t\t\t  RTE_SCHED_TYPE_ATOMIC);\n+\t\t}\n+\n+\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += vector_sz;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static __rte_noinline int\n pipeline_atq_worker_multi_stage_tx(void *arg)\n {\n@@ -245,6 +353,147 @@ pipeline_atq_worker_multi_stage_burst_fwd(void *arg)\n \treturn 0;\n }\n \n+static __rte_noinline int\n+pipeline_atq_worker_multi_stage_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_INIT;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tcq_id = ev.sub_event_type % nb_stages;\n+\n+\t\tif (cq_id == last_queue) {\n+\t\t\tvector_sz = ev.vec->nb_elem;\n+\t\t\tpipeline_event_tx_vector(dev, port, &ev);\n+\t\t\tw->processed_pkts += vector_sz;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tev.sub_event_type++;\n+\t\tpipeline_fwd_event_vector(&ev, sched_type_list[cq_id]);\n+\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_atq_worker_multi_stage_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tcq_id = ev.sub_event_type % nb_stages;\n+\n+\t\tif (cq_id == last_queue) {\n+\t\t\tev.queue_id = tx_queue[ev.vec->port];\n+\t\t\tev.vec->queue = 0;\n+\t\t\tvector_sz = ev.vec->nb_elem;\n+\t\t\tpipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\t\tw->processed_pkts += vector_sz;\n+\t\t} else {\n+\t\t\tev.sub_event_type++;\n+\t\t\tpipeline_fwd_event_vector(&ev, sched_type_list[cq_id]);\n+\t\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_atq_worker_multi_stage_burst_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tcq_id = ev[i].sub_event_type % nb_stages;\n+\n+\t\t\tif (cq_id == last_queue) {\n+\t\t\t\tvector_sz = ev[i].vec->nb_elem;\n+\t\t\t\tpipeline_event_tx_vector(dev, port, &ev[i]);\n+\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n+\t\t\t\tw->processed_pkts += vector_sz;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tev[i].sub_event_type++;\n+\t\t\tpipeline_fwd_event_vector(&ev[i],\n+\t\t\t\t\t\t  sched_type_list[cq_id]);\n+\t\t}\n+\n+\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_atq_worker_multi_stage_burst_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tcq_id = ev[i].sub_event_type % nb_stages;\n+\n+\t\t\tif (cq_id == last_queue) {\n+\t\t\t\tvector_sz = ev[i].vec->nb_elem;\n+\t\t\t\tev[i].queue_id = tx_queue[ev[i].vec->port];\n+\t\t\t\tev[i].vec->queue = 0;\n+\t\t\t\tpipeline_fwd_event_vector(\n+\t\t\t\t\t&ev[i], RTE_SCHED_TYPE_ATOMIC);\n+\t\t\t\tw->processed_pkts += vector_sz;\n+\t\t\t} else {\n+\t\t\t\tev[i].sub_event_type++;\n+\t\t\t\tpipeline_fwd_event_vector(\n+\t\t\t\t\t&ev[i], sched_type_list[cq_id]);\n+\t\t\t}\n+\t\t}\n+\n+\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n worker_wrapper(void *arg)\n {\n@@ -253,27 +502,36 @@ worker_wrapper(void *arg)\n \tconst bool burst = evt_has_burst_mode(w->dev_id);\n \tconst bool internal_port = w->t->internal_port;\n \tconst uint8_t nb_stages = opt->nb_stages;\n-\tRTE_SET_USED(opt);\n+\t/*vector/burst/internal_port*/\n+\tconst pipeline_atq_worker_t\n+\tpipeline_atq_worker_single_stage[2][2][2] = {\n+\t\t[0][0][0] = pipeline_atq_worker_single_stage_fwd,\n+\t\t[0][0][1] = pipeline_atq_worker_single_stage_tx,\n+\t\t[0][1][0] = pipeline_atq_worker_single_stage_burst_fwd,\n+\t\t[0][1][1] = pipeline_atq_worker_single_stage_burst_tx,\n+\t\t[1][0][0] = pipeline_atq_worker_single_stage_fwd_vector,\n+\t\t[1][0][1] = pipeline_atq_worker_single_stage_tx_vector,\n+\t\t[1][1][0] = pipeline_atq_worker_single_stage_burst_fwd_vector,\n+\t\t[1][1][1] = pipeline_atq_worker_single_stage_burst_tx_vector,\n+\t};\n+\tconst pipeline_atq_worker_t\n+\tpipeline_atq_worker_multi_stage[2][2][2] = {\n+\t\t[0][0][0] = pipeline_atq_worker_multi_stage_fwd,\n+\t\t[0][0][1] = pipeline_atq_worker_multi_stage_tx,\n+\t\t[0][1][0] = pipeline_atq_worker_multi_stage_burst_fwd,\n+\t\t[0][1][1] = pipeline_atq_worker_multi_stage_burst_tx,\n+\t\t[1][0][0] = pipeline_atq_worker_multi_stage_fwd_vector,\n+\t\t[1][0][1] = pipeline_atq_worker_multi_stage_tx_vector,\n+\t\t[1][1][0] = pipeline_atq_worker_multi_stage_burst_fwd_vector,\n+\t\t[1][1][1] = pipeline_atq_worker_multi_stage_burst_tx_vector,\n+\t};\n \n-\tif (nb_stages == 1) {\n-\t\tif (!burst && internal_port)\n-\t\t\treturn pipeline_atq_worker_single_stage_tx(arg);\n-\t\telse if (!burst && !internal_port)\n-\t\t\treturn pipeline_atq_worker_single_stage_fwd(arg);\n-\t\telse if (burst && internal_port)\n-\t\t\treturn pipeline_atq_worker_single_stage_burst_tx(arg);\n-\t\telse if (burst && !internal_port)\n-\t\t\treturn pipeline_atq_worker_single_stage_burst_fwd(arg);\n-\t} else {\n-\t\tif (!burst && internal_port)\n-\t\t\treturn pipeline_atq_worker_multi_stage_tx(arg);\n-\t\telse if (!burst && !internal_port)\n-\t\t\treturn pipeline_atq_worker_multi_stage_fwd(arg);\n-\t\tif (burst && internal_port)\n-\t\t\treturn pipeline_atq_worker_multi_stage_burst_tx(arg);\n-\t\telse if (burst && !internal_port)\n-\t\t\treturn pipeline_atq_worker_multi_stage_burst_fwd(arg);\n-\t}\n+\tif (nb_stages == 1)\n+\t\treturn (pipeline_atq_worker_single_stage[opt->ena_vector][burst]\n+\t\t\t\t\t\t\t[internal_port])(arg);\n+\telse\n+\t\treturn (pipeline_atq_worker_multi_stage[opt->ena_vector][burst]\n+\t\t\t\t\t\t       [internal_port])(arg);\n \n \trte_panic(\"invalid worker\\n\");\n }\n@@ -290,7 +548,7 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \tint ret;\n \tint nb_ports;\n \tint nb_queues;\n-\tuint8_t queue;\n+\tuint8_t queue, is_prod;\n \tuint8_t tx_evqueue_id[RTE_MAX_ETHPORTS];\n \tuint8_t queue_arr[RTE_EVENT_MAX_QUEUES_PER_DEV];\n \tuint8_t nb_worker_queues = 0;\n@@ -330,15 +588,19 @@ pipeline_atq_eventdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\tq_conf.event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;\n \n \t\tif (!t->internal_port) {\n+\t\t\tis_prod = false;\n \t\t\tRTE_ETH_FOREACH_DEV(prod) {\n \t\t\t\tif (queue == tx_evqueue_id[prod]) {\n \t\t\t\t\tq_conf.event_queue_cfg =\n \t\t\t\t\t\tRTE_EVENT_QUEUE_CFG_SINGLE_LINK;\n-\t\t\t\t} else {\n-\t\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n-\t\t\t\t\tnb_worker_queues++;\n+\t\t\t\t\tis_prod = true;\n+\t\t\t\t\tbreak;\n \t\t\t\t}\n \t\t\t}\n+\t\t\tif (!is_prod) {\n+\t\t\t\tqueue_arr[nb_worker_queues] = queue;\n+\t\t\t\tnb_worker_queues++;\n+\t\t\t}\n \t\t}\n \n \t\tret = rte_event_queue_setup(opt->dev_id, queue, &q_conf);\ndiff --git a/app/test-eventdev/test_pipeline_common.c b/app/test-eventdev/test_pipeline_common.c\nindex b47d76743..89f73be86 100644\n--- a/app/test-eventdev/test_pipeline_common.c\n+++ b/app/test-eventdev/test_pipeline_common.c\n@@ -36,6 +36,12 @@ pipeline_opt_dump(struct evt_options *opt, uint8_t nb_queues)\n \tevt_dump_queue_priority(opt);\n \tevt_dump_sched_type_list(opt);\n \tevt_dump_producer_type(opt);\n+\tevt_dump(\"nb_eth_rx_queues\", \"%d\", opt->eth_queues);\n+\tevt_dump(\"event_vector\", \"%d\", opt->ena_vector);\n+\tif (opt->ena_vector) {\n+\t\tevt_dump(\"vector_size\", \"%d\", opt->vector_size);\n+\t\tevt_dump(\"vector_tmo_ns\", \"%ld\", opt->vector_tmo_nsec);\n+\t}\n }\n \n static inline uint64_t\n@@ -163,7 +169,7 @@ pipeline_opt_check(struct evt_options *opt, uint64_t nb_queues)\n int\n pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n {\n-\tuint16_t i;\n+\tuint16_t i, j;\n \tint ret;\n \tuint8_t nb_queues = 1;\n \tstruct test_pipeline *t = evt_test_priv(test);\n@@ -210,6 +216,16 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\tif (!(caps & RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT))\n \t\t\tt->internal_port = 0;\n \n+\t\tret = rte_event_eth_rx_adapter_caps_get(opt->dev_id, i, &caps);\n+\t\tif (ret != 0) {\n+\t\t\tevt_err(\"failed to get event tx adapter[%d] caps\", i);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (!(caps & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT))\n+\t\t\tlocal_port_conf.rxmode.offloads |=\n+\t\t\t\tDEV_RX_OFFLOAD_RSS_HASH;\n+\n \t\tret = rte_eth_dev_info_get(i, &dev_info);\n \t\tif (ret != 0) {\n \t\t\tevt_err(\"Error during getting device (port %u) info: %s\\n\",\n@@ -236,19 +252,22 @@ pipeline_ethdev_setup(struct evt_test *test, struct evt_options *opt)\n \t\t\t\tlocal_port_conf.rx_adv_conf.rss_conf.rss_hf);\n \t\t}\n \n-\t\tif (rte_eth_dev_configure(i, nb_queues, nb_queues,\n-\t\t\t\t\t&local_port_conf)\n-\t\t\t\t< 0) {\n+\t\tif (rte_eth_dev_configure(i, opt->eth_queues, nb_queues,\n+\t\t\t\t\t  &local_port_conf) < 0) {\n \t\t\tevt_err(\"Failed to configure eth port [%d]\", i);\n \t\t\treturn -EINVAL;\n \t\t}\n \n-\t\tif (rte_eth_rx_queue_setup(i, 0, NB_RX_DESC,\n-\t\t\t\trte_socket_id(), &rx_conf, t->pool) < 0) {\n-\t\t\tevt_err(\"Failed to setup eth port [%d] rx_queue: %d.\",\n+\t\tfor (j = 0; j < opt->eth_queues; j++) {\n+\t\t\tif (rte_eth_rx_queue_setup(i, j, NB_RX_DESC,\n+\t\t\t\t\t\t   rte_socket_id(), &rx_conf,\n+\t\t\t\t\t\t   t->pool) < 0) {\n+\t\t\t\tevt_err(\"Failed to setup eth port [%d] rx_queue: %d.\",\n \t\t\t\t\ti, 0);\n-\t\t\treturn -EINVAL;\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n \t\t}\n+\n \t\tif (rte_eth_tx_queue_setup(i, 0, NB_TX_DESC,\n \t\t\t\t\trte_socket_id(), NULL) < 0) {\n \t\t\tevt_err(\"Failed to setup eth port [%d] tx_queue: %d.\",\n@@ -310,11 +329,24 @@ pipeline_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride,\n {\n \tint ret = 0;\n \tuint16_t prod;\n+\tstruct rte_mempool *vector_pool = NULL;\n \tstruct rte_event_eth_rx_adapter_queue_conf queue_conf;\n \n \tmemset(&queue_conf, 0,\n \t\t\tsizeof(struct rte_event_eth_rx_adapter_queue_conf));\n \tqueue_conf.ev.sched_type = opt->sched_type_list[0];\n+\tif (opt->ena_vector) {\n+\t\tunsigned int nb_elem = (opt->pool_sz / opt->vector_size) << 1;\n+\n+\t\tnb_elem = nb_elem ? nb_elem : 1;\n+\t\tvector_pool = rte_event_vector_pool_create(\n+\t\t\t\"vector_pool\", nb_elem, 0, opt->vector_size,\n+\t\t\topt->socket_id);\n+\t\tif (vector_pool == NULL) {\n+\t\t\tevt_err(\"failed to create event vector pool\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n \tRTE_ETH_FOREACH_DEV(prod) {\n \t\tuint32_t cap;\n \n@@ -326,6 +358,19 @@ pipeline_event_rx_adapter_setup(struct evt_options *opt, uint8_t stride,\n \t\t\t\t\topt->dev_id);\n \t\t\treturn ret;\n \t\t}\n+\t\tif (opt->ena_vector) {\n+\t\t\tif (cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR) {\n+\t\t\t\tqueue_conf.vector_sz = opt->vector_size;\n+\t\t\t\tqueue_conf.vector_timeout_ns =\n+\t\t\t\t\topt->vector_tmo_nsec;\n+\t\t\t\tqueue_conf.rx_queue_flags |=\n+\t\t\t\tRTE_EVENT_ETH_RX_ADAPTER_QUEUE_EVENT_VECTOR;\n+\t\t\t\tqueue_conf.vector_mp = vector_pool;\n+\t\t\t} else {\n+\t\t\t\tevt_err(\"Rx adapter doesn't support event vector\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t}\n \t\tqueue_conf.ev.queue_id = prod * stride;\n \t\tret = rte_event_eth_rx_adapter_create(prod, opt->dev_id,\n \t\t\t\t&prod_conf);\n@@ -378,6 +423,14 @@ pipeline_event_tx_adapter_setup(struct evt_options *opt,\n \t\t\treturn ret;\n \t\t}\n \n+\t\tif (opt->ena_vector) {\n+\t\t\tif (!(cap &\n+\t\t\t      RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR)) {\n+\t\t\t\tevt_err(\"Tx adapter doesn't support event vector\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t}\n+\n \t\tret = rte_event_eth_tx_adapter_create(consm, opt->dev_id,\n \t\t\t\t&port_conf);\n \t\tif (ret) {\ndiff --git a/app/test-eventdev/test_pipeline_common.h b/app/test-eventdev/test_pipeline_common.h\nindex 6e73c6ab2..800a90616 100644\n--- a/app/test-eventdev/test_pipeline_common.h\n+++ b/app/test-eventdev/test_pipeline_common.h\n@@ -101,6 +101,14 @@ pipeline_fwd_event(struct rte_event *ev, uint8_t sched)\n \tev->sched_type = sched;\n }\n \n+static __rte_always_inline void\n+pipeline_fwd_event_vector(struct rte_event *ev, uint8_t sched)\n+{\n+\tev->event_type = RTE_EVENT_TYPE_CPU_VECTOR;\n+\tev->op = RTE_EVENT_OP_FORWARD;\n+\tev->sched_type = sched;\n+}\n+\n static __rte_always_inline void\n pipeline_event_tx(const uint8_t dev, const uint8_t port,\n \t\tstruct rte_event * const ev)\n@@ -110,6 +118,16 @@ pipeline_event_tx(const uint8_t dev, const uint8_t port,\n \t\trte_pause();\n }\n \n+static __rte_always_inline void\n+pipeline_event_tx_vector(const uint8_t dev, const uint8_t port,\n+\t\t\t struct rte_event *const ev)\n+{\n+\tev->vec->queue = 0;\n+\n+\twhile (!rte_event_eth_tx_adapter_enqueue(dev, port, ev, 1, 0))\n+\t\trte_pause();\n+}\n+\n static __rte_always_inline void\n pipeline_event_tx_burst(const uint8_t dev, const uint8_t port,\n \t\tstruct rte_event *ev, const uint16_t nb_rx)\ndiff --git a/app/test-eventdev/test_pipeline_queue.c b/app/test-eventdev/test_pipeline_queue.c\nindex 9a9febb19..f6cc3e358 100644\n--- a/app/test-eventdev/test_pipeline_queue.c\n+++ b/app/test-eventdev/test_pipeline_queue.c\n@@ -15,6 +15,8 @@ pipeline_queue_nb_event_queues(struct evt_options *opt)\n \treturn (eth_count * opt->nb_stages) + eth_count;\n }\n \n+typedef int (*pipeline_queue_worker_t)(void *arg);\n+\n static __rte_noinline int\n pipeline_queue_worker_single_stage_tx(void *arg)\n {\n@@ -126,6 +128,125 @@ pipeline_queue_worker_single_stage_burst_fwd(void *arg)\n \treturn 0;\n }\n \n+static __rte_noinline int\n+pipeline_queue_worker_single_stage_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {\n+\t\t\tvector_sz = ev.vec->nb_elem;\n+\t\t\tpipeline_event_tx_vector(dev, port, &ev);\n+\t\t\tw->processed_pkts += vector_sz;\n+\t\t} else {\n+\t\t\tev.queue_id++;\n+\t\t\tpipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_queue_worker_single_stage_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tev.queue_id = tx_queue[ev.vec->port];\n+\t\tev.vec->queue = 0;\n+\t\tvector_sz = ev.vec->nb_elem;\n+\t\tpipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t\tw->processed_pkts += vector_sz;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_queue_worker_single_stage_burst_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tif (ev[i].sched_type == RTE_SCHED_TYPE_ATOMIC) {\n+\t\t\t\tvector_sz = ev[i].vec->nb_elem;\n+\t\t\t\tpipeline_event_tx_vector(dev, port, &ev[i]);\n+\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n+\t\t\t\tw->processed_pkts += vector_sz;\n+\t\t\t} else {\n+\t\t\t\tev[i].queue_id++;\n+\t\t\t\tpipeline_fwd_event_vector(\n+\t\t\t\t\t&ev[i], RTE_SCHED_TYPE_ATOMIC);\n+\t\t\t}\n+\t\t}\n+\n+\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_queue_worker_single_stage_burst_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_SINGLE_STAGE_BURST_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tvector_sz = 0;\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tev[i].queue_id = tx_queue[ev[i].vec->port];\n+\t\t\tev[i].vec->queue = 0;\n+\t\t\tvector_sz += ev[i].vec->nb_elem;\n+\t\t\tpipeline_fwd_event_vector(&ev[i],\n+\t\t\t\t\t\t  RTE_SCHED_TYPE_ATOMIC);\n+\t\t}\n+\n+\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t\tw->processed_pkts += vector_sz;\n+\t}\n+\n+\treturn 0;\n+}\n \n static __rte_noinline int\n pipeline_queue_worker_multi_stage_tx(void *arg)\n@@ -267,6 +388,151 @@ pipeline_queue_worker_multi_stage_burst_fwd(void *arg)\n \treturn 0;\n }\n \n+static __rte_noinline int\n+pipeline_queue_worker_multi_stage_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tcq_id = ev.queue_id % nb_stages;\n+\n+\t\tif (ev.queue_id == tx_queue[ev.vec->port]) {\n+\t\t\tvector_sz = ev.vec->nb_elem;\n+\t\t\tpipeline_event_tx_vector(dev, port, &ev);\n+\t\t\tw->processed_pkts += vector_sz;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tev.queue_id++;\n+\t\tpipeline_fwd_event_vector(&ev, cq_id != last_queue\n+\t\t\t\t\t\t       ? sched_type_list[cq_id]\n+\t\t\t\t\t\t       : RTE_SCHED_TYPE_ATOMIC);\n+\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_queue_worker_multi_stage_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t event = rte_event_dequeue_burst(dev, port, &ev, 1, 0);\n+\n+\t\tif (!event) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tcq_id = ev.queue_id % nb_stages;\n+\n+\t\tif (cq_id == last_queue) {\n+\t\t\tvector_sz = ev.vec->nb_elem;\n+\t\t\tev.queue_id = tx_queue[ev.vec->port];\n+\t\t\tpipeline_fwd_event_vector(&ev, RTE_SCHED_TYPE_ATOMIC);\n+\t\t\tw->processed_pkts += vector_sz;\n+\t\t} else {\n+\t\t\tev.queue_id++;\n+\t\t\tpipeline_fwd_event_vector(&ev, sched_type_list[cq_id]);\n+\t\t}\n+\n+\t\tpipeline_event_enqueue(dev, port, &ev);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_queue_worker_multi_stage_burst_tx_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tcq_id = ev[i].queue_id % nb_stages;\n+\n+\t\t\tif (ev[i].queue_id == tx_queue[ev[i].vec->port]) {\n+\t\t\t\tvector_sz = ev[i].vec->nb_elem;\n+\t\t\t\tpipeline_event_tx_vector(dev, port, &ev[i]);\n+\t\t\t\tev[i].op = RTE_EVENT_OP_RELEASE;\n+\t\t\t\tw->processed_pkts += vector_sz;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tev[i].queue_id++;\n+\t\t\tpipeline_fwd_event_vector(\n+\t\t\t\t&ev[i], cq_id != last_queue\n+\t\t\t\t\t\t? sched_type_list[cq_id]\n+\t\t\t\t\t\t: RTE_SCHED_TYPE_ATOMIC);\n+\t\t}\n+\n+\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline int\n+pipeline_queue_worker_multi_stage_burst_fwd_vector(void *arg)\n+{\n+\tPIPELINE_WORKER_MULTI_STAGE_BURST_INIT;\n+\tconst uint8_t *tx_queue = t->tx_evqueue_id;\n+\tuint16_t vector_sz;\n+\n+\twhile (!t->done) {\n+\t\tuint16_t nb_rx =\n+\t\t\trte_event_dequeue_burst(dev, port, ev, BURST_SIZE, 0);\n+\n+\t\tif (!nb_rx) {\n+\t\t\trte_pause();\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tfor (i = 0; i < nb_rx; i++) {\n+\t\t\tcq_id = ev[i].queue_id % nb_stages;\n+\n+\t\t\tif (cq_id == last_queue) {\n+\t\t\t\tev[i].queue_id = tx_queue[ev[i].vec->port];\n+\t\t\t\tvector_sz = ev[i].vec->nb_elem;\n+\t\t\t\tpipeline_fwd_event_vector(\n+\t\t\t\t\t&ev[i], RTE_SCHED_TYPE_ATOMIC);\n+\t\t\t\tw->processed_pkts += vector_sz;\n+\t\t\t} else {\n+\t\t\t\tev[i].queue_id++;\n+\t\t\t\tpipeline_fwd_event_vector(\n+\t\t\t\t\t&ev[i], sched_type_list[cq_id]);\n+\t\t\t}\n+\t\t}\n+\n+\t\tpipeline_event_enqueue_burst(dev, port, ev, nb_rx);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n worker_wrapper(void *arg)\n {\n@@ -275,29 +541,39 @@ worker_wrapper(void *arg)\n \tconst bool burst = evt_has_burst_mode(w->dev_id);\n \tconst bool internal_port = w->t->internal_port;\n \tconst uint8_t nb_stages = opt->nb_stages;\n-\tRTE_SET_USED(opt);\n-\n-\tif (nb_stages == 1) {\n-\t\tif (!burst && internal_port)\n-\t\t\treturn pipeline_queue_worker_single_stage_tx(arg);\n-\t\telse if (!burst && !internal_port)\n-\t\t\treturn pipeline_queue_worker_single_stage_fwd(arg);\n-\t\telse if (burst && internal_port)\n-\t\t\treturn pipeline_queue_worker_single_stage_burst_tx(arg);\n-\t\telse if (burst && !internal_port)\n-\t\t\treturn pipeline_queue_worker_single_stage_burst_fwd(\n-\t\t\t\t\targ);\n-\t} else {\n-\t\tif (!burst && internal_port)\n-\t\t\treturn pipeline_queue_worker_multi_stage_tx(arg);\n-\t\telse if (!burst && !internal_port)\n-\t\t\treturn pipeline_queue_worker_multi_stage_fwd(arg);\n-\t\telse if (burst && internal_port)\n-\t\t\treturn pipeline_queue_worker_multi_stage_burst_tx(arg);\n-\t\telse if (burst && !internal_port)\n-\t\t\treturn pipeline_queue_worker_multi_stage_burst_fwd(arg);\n+\t/*vector/burst/internal_port*/\n+\tconst pipeline_queue_worker_t\n+\tpipeline_queue_worker_single_stage[2][2][2] = {\n+\t\t[0][0][0] = pipeline_queue_worker_single_stage_fwd,\n+\t\t[0][0][1] = pipeline_queue_worker_single_stage_tx,\n+\t\t[0][1][0] = pipeline_queue_worker_single_stage_burst_fwd,\n+\t\t[0][1][1] = pipeline_queue_worker_single_stage_burst_tx,\n+\t\t[1][0][0] = pipeline_queue_worker_single_stage_fwd_vector,\n+\t\t[1][0][1] = pipeline_queue_worker_single_stage_tx_vector,\n+\t\t[1][1][0] = pipeline_queue_worker_single_stage_burst_fwd_vector,\n+\t\t[1][1][1] = pipeline_queue_worker_single_stage_burst_tx_vector,\n+\t};\n+\tconst pipeline_queue_worker_t\n+\tpipeline_queue_worker_multi_stage[2][2][2] = {\n+\t\t[0][0][0] = pipeline_queue_worker_multi_stage_fwd,\n+\t\t[0][0][1] = pipeline_queue_worker_multi_stage_tx,\n+\t\t[0][1][0] = pipeline_queue_worker_multi_stage_burst_fwd,\n+\t\t[0][1][1] = pipeline_queue_worker_multi_stage_burst_tx,\n+\t\t[1][0][0] = pipeline_queue_worker_multi_stage_fwd_vector,\n+\t\t[1][0][1] = pipeline_queue_worker_multi_stage_tx_vector,\n+\t\t[1][1][0] = pipeline_queue_worker_multi_stage_burst_fwd_vector,\n+\t\t[1][1][1] = pipeline_queue_worker_multi_stage_burst_tx_vector,\n+\t};\n+\n+\tif (nb_stages == 1)\n+\t\treturn (pipeline_queue_worker_single_stage[opt->ena_vector]\n+\t\t\t\t\t\t\t  [burst]\n+\t\t\t\t\t\t\t  [internal_port])(arg);\n+\telse\n+\t\treturn (pipeline_queue_worker_multi_stage[opt->ena_vector]\n+\t\t\t\t\t\t\t [burst]\n+\t\t\t\t\t\t\t [internal_port])(arg);\n \n-\t}\n \trte_panic(\"invalid worker\\n\");\n }\n \ndiff --git a/doc/guides/tools/testeventdev.rst b/doc/guides/tools/testeventdev.rst\nindex ad1788a3d..691cf706e 100644\n--- a/doc/guides/tools/testeventdev.rst\n+++ b/doc/guides/tools/testeventdev.rst\n@@ -158,6 +158,26 @@ The following are the application command-line options:\n        Set max packet mbuf size. Can be used configure Rx/Tx scatter gather.\n        Only applicable for `pipeline_atq` and `pipeline_queue` tests.\n \n+* ``--nb_eth_queues``\n+\n+       Configure multiple Rx queues per each ethernet port.\n+       Only applicable for `pipeline_atq` and `pipeline_queue` tests.\n+\n+* ``--enable_vector``\n+\n+       Enable event vector for Rx/Tx adapters.\n+       Only applicable for `pipeline_atq` and `pipeline_queue` tests.\n+\n+* ``--vector_size``\n+\n+       Vector size to configure for the Rx adapter.\n+       Only applicable for `pipeline_atq` and `pipeline_queue` tests.\n+\n+* ``--vector_tmo_ns``\n+\n+       Vector timeout nanoseconds to be configured for the Rx adapter.\n+       Only applicable for `pipeline_atq` and `pipeline_queue` tests.\n+\n \n Eventdev Tests\n --------------\n@@ -607,6 +627,10 @@ Supported application command line options are following::\n         --worker_deq_depth\n         --prod_type_ethdev\n         --deq_tmo_nsec\n+        --nb_eth_queues\n+        --enable_vector\n+        --vector_size\n+        --vector_tmo_ns\n \n \n .. Note::\n@@ -699,6 +723,10 @@ Supported application command line options are following::\n         --worker_deq_depth\n         --prod_type_ethdev\n         --deq_tmo_nsec\n+        --nb_eth_queues\n+        --enable_vector\n+        --vector_size\n+        --vector_tmo_ns\n \n \n .. Note::\n",
    "prefixes": [
        "6/7"
    ]
}