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GET /api/patches/88007/?format=api
{ "id": 88007, "url": "http://patches.dpdk.org/api/patches/88007/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210219101422.19121-4-rmody@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210219101422.19121-4-rmody@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210219101422.19121-4-rmody@marvell.com", "date": "2021-02-19T10:14:18", "name": "[3/7] net/qede/base: add OS abstracted changes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "218c83def1b0bd3d29f76e1ae1694aed5b4e1f12", "submitter": { "id": 1211, "url": "http://patches.dpdk.org/api/people/1211/?format=api", "name": "Rasesh Mody", "email": "rmody@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210219101422.19121-4-rmody@marvell.com/mbox/", "series": [ { "id": 15303, "url": "http://patches.dpdk.org/api/series/15303/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15303", "date": "2021-02-19T10:14:15", "name": "net/qede: add support for new HW", "version": 1, "mbox": "http://patches.dpdk.org/series/15303/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88007/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/88007/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C6C41A054A;\n\tFri, 19 Feb 2021 11:15:08 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B349B1608CA;\n\tFri, 19 Feb 2021 11:15:08 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id D99B61608C9\n for <dev@dpdk.org>; Fri, 19 Feb 2021 11:15:07 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 11JAF7Pu019574; Fri, 19 Feb 2021 02:15:07 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 36sesvvtd9-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Fri, 19 Feb 2021 02:15:07 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 19 Feb 2021 02:15:05 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 19 Feb 2021 02:15:04 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 19 Feb 2021 02:15:04 -0800", "from irv1user08.caveonetworks.com (unknown [10.104.116.105])\n by maili.marvell.com (Postfix) with ESMTP id 8A8953F7043;\n Fri, 19 Feb 2021 02:15:04 -0800 (PST)", "(from rmody@localhost)\n by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id 11JAF4Er019197;\n Fri, 19 Feb 2021 02:15:04 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=h/spyC+1K0scA+FOCIsINZhS6M0dHjMEWunjPEmpLyM=;\n b=eWyIVled1w7cXfe9eeHrMVHexdDfIc0ok1c/0Zl+mff/0RI09LT3C9ZUaK0+BAx+l+fV\n j20BD3zPQkO4s3LnyORT/6Y+L9KZgIZ2WBZ7Zu8/kNdA8NutR7atOxCiktA6/nY3VhB/\n sIohke+U/Ll6HC/RaxTtUWipSR/2fok8I6+YS0bhernYIDSG75WXJG0FtTI172pU8LZ7\n dHHm6DD1wmKhadaoH1zdXb+kpHlSX0XXNIK6+xq4tQk0aIwtSQ2q/MlIk2GRnR+CeArh\n I/XX9LDMurJgh2jAiYvFp54ahVUUsWOwO7+HftOE/3nUAFKH/VZ9bKce6Gh+K8VOKRVd dg==", "X-Authentication-Warning": "irv1user08.caveonetworks.com: rmody set sender to\n rmody@marvell.com using -f", "From": "Rasesh Mody <rmody@marvell.com>", "To": "<jerinj@marvell.com>, <ferruh.yigit@intel.com>", "CC": "Rasesh Mody <rmody@marvell.com>, <dev@dpdk.org>,\n <GR-Everest-DPDK-Dev@marvell.com>, Igor Russkikh <irusskikh@marvell.com>", "Date": "Fri, 19 Feb 2021 02:14:18 -0800", "Message-ID": "<20210219101422.19121-4-rmody@marvell.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20210219101422.19121-1-rmody@marvell.com>", "References": "<20210219101422.19121-1-rmody@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-02-19_04:2021-02-18,\n 2021-02-19 signatures=0", "Subject": "[dpdk-dev] [PATCH 3/7] net/qede/base: add OS abstracted changes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The patch includes OS abstracted changes required to support new\nhardware and the new feature supported by it. It also adds new bit\nops to RTE library.\n\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\n---\n drivers/net/qede/base/bcm_osal.c | 2 +-\n drivers/net/qede/base/bcm_osal.h | 39 ++++++++++++++++++---\n lib/librte_eal/include/rte_bitops.h | 54 ++++++++++++++++++++++++++++-\n 3 files changed, 88 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c\nindex 2c59397e0..23a84795f 100644\n--- a/drivers/net/qede/base/bcm_osal.c\n+++ b/drivers/net/qede/base/bcm_osal.c\n@@ -121,7 +121,7 @@ void qede_vf_fill_driver_data(struct ecore_hwfn *hwfn,\n \t\t\t struct ecore_vf_acquire_sw_info *vf_sw_info)\n {\n \tvf_sw_info->os_type = VFPF_ACQUIRE_OS_LINUX_USERSPACE;\n-\tvf_sw_info->override_fw_version = 1;\n+\t/* TODO - fill driver version */\n }\n \n void *osal_dma_alloc_coherent(struct ecore_dev *p_dev,\ndiff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex c5b539928..38b7fff67 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -47,9 +47,10 @@ void qed_link_update(struct ecore_hwfn *hwfn);\n #endif\n #endif\n \n-#define OSAL_WARN(arg1, arg2, arg3, ...) (0)\n-\n-#define UNUSED(x)\t(void)(x)\n+#define UNUSED1(a)\t\t(void)(a)\n+#define UNUSED2(a, b)\t\t((void)(a), UNUSED1(b))\n+#define UNUSED3(a, b, c)\t((void)(a), UNUSED2(b, c))\n+#define UNUSED4(a, b, c, d)\t((void)(a), UNUSED3(b, c, d))\n \n /* Memory Types */\n typedef uint8_t u8;\n@@ -167,9 +168,8 @@ typedef pthread_mutex_t osal_mutex_t;\n #define OSAL_SPIN_UNLOCK(lock) rte_spinlock_unlock(lock)\n #define OSAL_SPIN_LOCK_IRQSAVE(lock, flags)\t\\\n \tdo {\t\t\t\t\t\\\n-\t\tUNUSED(lock);\t\t\t\\\n \t\tflags = 0;\t\t\t\\\n-\t\tUNUSED(flags);\t\t\t\\\n+\t\tUNUSED2(lock, flags);\t\t\\\n \t} while (0)\n #define OSAL_SPIN_UNLOCK_IRQSAVE(lock, flags) nothing\n #define OSAL_SPIN_LOCK_ALLOC(hwfn, lock) nothing\n@@ -326,6 +326,18 @@ typedef struct osal_list_t {\n #define OSAL_GET_BIT(bit, bitmap) \\\n \trte_bit_relaxed_get32(bit, bitmap)\n \n+#define OSAL_TEST_BIT(bit, bitmap) \\\n+\tOSAL_GET_BIT(bit, bitmap)\n+\n+#define OSAL_TEST_AND_CLEAR_BIT(bit, bitmap) \\\n+\trte_bit_relaxed_test_and_clear32(bit, bitmap)\n+\n+#define OSAL_TEST_AND_FLIP_BIT(bit, bitmap) \\\n+\trte_bit_relaxed_test_and_flip32(bit, bitmap)\n+\n+#define OSAL_NON_ATOMIC_SET_BIT(bit, bitmap) \\\n+\trte_bit_relaxed_set32(bit, bitmap)\n+\n u32 qede_find_first_bit(unsigned long *, u32);\n #define OSAL_FIND_FIRST_BIT(bitmap, length) \\\n \tqede_find_first_bit(bitmap, length)\n@@ -342,7 +354,10 @@ u32 qede_find_first_zero_bit(u32 *bitmap, u32 length);\n #define OSAL_BITMAP_WEIGHT(bitmap, count) 0\n \n #define OSAL_LINK_UPDATE(hwfn) qed_link_update(hwfn)\n+#define OSAL_BW_UPDATE(hwfn, ptt) nothing\n #define OSAL_TRANSCEIVER_UPDATE(hwfn) nothing\n+#define OSAL_TRANSCEIVER_TX_FAULT(hwfn) nothing\n+#define OSAL_TRANSCEIVER_RX_LOS(hwfn) nothing\n #define OSAL_DCBX_AEN(hwfn, mib_type) nothing\n \n /* SR-IOV channel */\n@@ -366,6 +381,8 @@ void osal_vf_flr_update(struct ecore_hwfn *p_hwfn);\n #define OSAL_IOV_VF_MSG_TYPE(hwfn, vfid, vf_msg_type) nothing\n #define OSAL_IOV_PF_RESP_TYPE(hwfn, vfid, pf_resp_type) nothing\n #define OSAL_IOV_VF_VPORT_STOP(hwfn, vf) nothing\n+#define OSAL_IOV_DB_REC_HANDLER(hwfn) nothing\n+#define OSAL_IOV_BULLETIN_UPDATE(hwfn) nothing\n \n u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len,\n \t\t u8 *input_buf, u32 max_size, u8 *unzip_buf);\n@@ -412,16 +429,20 @@ u32 qede_osal_log2(u32);\n \n #define OFFSETOF(str, field) __builtin_offsetof(str, field)\n #define OSAL_ASSERT(is_assert) assert(is_assert)\n+#define OSAL_WARN(condition, format, ...) (0)\n #define OSAL_BEFORE_PF_START(file, engine) nothing\n #define OSAL_AFTER_PF_STOP(file, engine) nothing\n+#define OSAL_GCD(a, b) (1)\n \n /* Endian macros */\n #define OSAL_CPU_TO_BE32(val) rte_cpu_to_be_32(val)\n+#define OSAL_CPU_TO_BE16(val) rte_cpu_to_be_16(val)\n #define OSAL_BE32_TO_CPU(val) rte_be_to_cpu_32(val)\n #define OSAL_CPU_TO_LE32(val) rte_cpu_to_le_32(val)\n #define OSAL_CPU_TO_LE16(val) rte_cpu_to_le_16(val)\n #define OSAL_LE32_TO_CPU(val) rte_le_to_cpu_32(val)\n #define OSAL_LE16_TO_CPU(val) rte_le_to_cpu_16(val)\n+#define OSAL_BE16_TO_CPU(val) rte_be_to_cpu_16(val)\n #define OSAL_CPU_TO_BE64(val) rte_cpu_to_be_64(val)\n \n #define OSAL_ARRAY_SIZE(arr) RTE_DIM(arr)\n@@ -432,6 +453,7 @@ u32 qede_osal_log2(u32);\n #define OSAL_STRLEN(string) strlen(string)\n #define OSAL_STRCPY(dst, string) strcpy(dst, string)\n #define OSAL_STRNCPY(dst, string, len) strncpy(dst, string, len)\n+#define OSAL_STRLCPY(dst, string, len) strlcpy(dst, string, len)\n #define OSAL_STRCMP(str1, str2) strcmp(str1, str2)\n #define OSAL_STRTOUL(str, base, res) 0\n \n@@ -463,6 +485,7 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length);\n #define OSAL_MFW_FILL_TLV_DATA(type, buf, data) (0)\n #define OSAL_HW_INFO_CHANGE(p_hwfn, change) nothing\n #define OSAL_MFW_CMD_PREEMPT(p_hwfn) nothing\n+#define OSAL_NUM_FUNCS_IS_SET(p_hwfn) nothing\n #define OSAL_PF_VALIDATE_MODIFY_TUNN_CONFIG(p_hwfn, mask, b_update, tunn) 0\n \n #define OSAL_DIV_S64(a, b)\t((a) / (b))\n@@ -478,4 +501,10 @@ enum dbg_status\tqed_dbg_alloc_user_data(struct ecore_hwfn *p_hwfn,\n \tqed_dbg_alloc_user_data(p_hwfn, user_data_ptr)\n #define OSAL_DB_REC_OCCURRED(p_hwfn) nothing\n \n+typedef int osal_va_list;\n+#define OSAL_VA_START(A, B) UNUSED2(A, B)\n+#define OSAL_VA_END(A) UNUSED1(A)\n+#define OSAL_VSNPRINTF(A, ...) 0\n+#define OSAL_INT_DBG_STORE(P_DEV, ...) nothing\n+\n #endif /* __BCM_OSAL_H */\ndiff --git a/lib/librte_eal/include/rte_bitops.h b/lib/librte_eal/include/rte_bitops.h\nindex 141e8ea73..9a39dd13c 100644\n--- a/lib/librte_eal/include/rte_bitops.h\n+++ b/lib/librte_eal/include/rte_bitops.h\n@@ -54,7 +54,7 @@ rte_bit_relaxed_get32(unsigned int nr, volatile uint32_t *addr)\n {\n \tRTE_ASSERT(nr < 32);\n \n-\tuint32_t mask = UINT32_C(1) << nr;\n+\tuint32_t mask = RTE_BIT32(nr);\n \treturn (*addr) & mask;\n }\n \n@@ -152,6 +152,32 @@ rte_bit_relaxed_test_and_clear32(unsigned int nr, volatile uint32_t *addr)\n \treturn val & mask;\n }\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 32-bit value, then flip it to 0 without\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and flip.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint32_t\n+rte_bit_relaxed_test_and_flip32(unsigned int nr, volatile uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = RTE_BIT32(nr);\n+\tuint32_t val = *addr;\n+\t*addr = val ^ mask;\n+\treturn val & mask;\n+}\n+\n /*------------------------ 64-bit relaxed operations ------------------------*/\n \n /**\n@@ -271,4 +297,30 @@ rte_bit_relaxed_test_and_clear64(unsigned int nr, volatile uint64_t *addr)\n \treturn val & mask;\n }\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 64-bit value, then flip it to 0 without\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and flip.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint64_t\n+rte_bit_relaxed_test_and_flip64(unsigned int nr, volatile uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = RTE_BIT64(nr);\n+\tuint64_t val = *addr;\n+\t*addr = val ^ mask;\n+\treturn val & mask;\n+}\n+\n #endif /* _RTE_BITOPS_H_ */\n", "prefixes": [ "3/7" ] }