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GET /api/patches/87959/?format=api
{ "id": 87959, "url": "http://patches.dpdk.org/api/patches/87959/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210216204646.24196-5-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210216204646.24196-5-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210216204646.24196-5-cristian.dumitrescu@intel.com", "date": "2021-02-16T20:46:46", "name": "[v3,5/5] table: add wildcard match table type", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "07e57e241e725e8efef53576eebff92f3c135541", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210216204646.24196-5-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 15273, "url": "http://patches.dpdk.org/api/series/15273/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15273", "date": "2021-02-16T20:46:42", "name": "[v3,1/5] pipeline: improve table entry helpers", "version": 3, "mbox": "http://patches.dpdk.org/series/15273/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/87959/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/87959/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 28B9CA054D;\n\tTue, 16 Feb 2021 21:47:15 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7794416081D;\n\tTue, 16 Feb 2021 21:46:56 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 1BAED1607F8\n for <dev@dpdk.org>; Tue, 16 Feb 2021 21:46:52 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Feb 2021 12:46:51 -0800", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga001.fm.intel.com with ESMTP; 16 Feb 2021 12:46:51 -0800" ], "IronPort-SDR": [ "\n pbDCEqofoZPUzQVCH6lbO7HABzDnC8/dG7/TLiRqZ/lxkyeZ1DGEELGGeIpPUyJU+LXlwPjYLO\n ZwEOFg3ecoFQ==", "\n 0yClna0vSdJ0jUHGpR3IeNoboDpvJsMdqCfKVzHIjy7VxDrDWhUXBZA8xGPenkxclBh0V3As8b\n gVRVaLJ3Qr6A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9897\"; a=\"247078508\"", "E=Sophos;i=\"5.81,184,1610438400\"; d=\"scan'208\";a=\"247078508\"", "E=Sophos;i=\"5.81,184,1610438400\"; d=\"scan'208\";a=\"493443119\"" ], "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Cc": "Churchill Khangar <churchill.khangar@intel.com>", "Date": "Tue, 16 Feb 2021 20:46:46 +0000", "Message-Id": "<20210216204646.24196-5-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210216204646.24196-1-cristian.dumitrescu@intel.com>", "References": "<20210216202127.22803-1-cristian.dumitrescu@intel.com>\n <20210216204646.24196-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 5/5] table: add wildcard match table type", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add the widlcard match/ACL table type for the SWX pipeline, which is\nused under the hood by the table instruction.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\nSigned-off-by: Churchill Khangar <churchill.khangar@intel.com>\n---\n doc/api/doxy-api-index.md | 1 +\n examples/pipeline/obj.c | 8 +\n lib/librte_table/meson.build | 8 +-\n lib/librte_table/rte_swx_table_wm.c | 470 ++++++++++++++++++++++++++++\n lib/librte_table/rte_swx_table_wm.h | 27 ++\n lib/librte_table/version.map | 3 +\n 6 files changed, 515 insertions(+), 2 deletions(-)\n create mode 100644 lib/librte_table/rte_swx_table_wm.c\n create mode 100644 lib/librte_table/rte_swx_table_wm.h", "diff": "diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md\nindex 748514e24..94e9937be 100644\n--- a/doc/api/doxy-api-index.md\n+++ b/doc/api/doxy-api-index.md\n@@ -187,6 +187,7 @@ The public API headers are grouped by topics:\n * SWX table:\n [table] (@ref rte_swx_table.h),\n [table_em] (@ref rte_swx_table_em.h)\n+ [table_wm] (@ref rte_swx_table_wm.h)\n * [graph] (@ref rte_graph.h):\n [graph_worker] (@ref rte_graph_worker.h)\n * graph_nodes:\ndiff --git a/examples/pipeline/obj.c b/examples/pipeline/obj.c\nindex 84bbcf2b2..7be61228b 100644\n--- a/examples/pipeline/obj.c\n+++ b/examples/pipeline/obj.c\n@@ -11,6 +11,7 @@\n #include <rte_swx_port_ethdev.h>\n #include <rte_swx_port_source_sink.h>\n #include <rte_swx_table_em.h>\n+#include <rte_swx_table_wm.h>\n #include <rte_swx_pipeline.h>\n #include <rte_swx_ctl.h>\n \n@@ -415,6 +416,13 @@ pipeline_create(struct obj *obj, const char *name, int numa_node)\n \tif (status)\n \t\tgoto error;\n \n+\tstatus = rte_swx_pipeline_table_type_register(p,\n+\t\t\"wildcard\",\n+\t\tRTE_SWX_TABLE_MATCH_WILDCARD,\n+\t\t&rte_swx_table_wildcard_match_ops);\n+\tif (status)\n+\t\tgoto error;\n+\n \t/* Node allocation */\n \tpipeline = calloc(1, sizeof(struct pipeline));\n \tif (pipeline == NULL)\ndiff --git a/lib/librte_table/meson.build b/lib/librte_table/meson.build\nindex aa1e1d038..007ffe013 100644\n--- a/lib/librte_table/meson.build\n+++ b/lib/librte_table/meson.build\n@@ -12,7 +12,9 @@ sources = files('rte_table_acl.c',\n \t\t'rte_table_hash_lru.c',\n \t\t'rte_table_array.c',\n \t\t'rte_table_stub.c',\n-\t\t'rte_swx_table_em.c',)\n+\t\t'rte_swx_table_em.c',\n+\t\t'rte_swx_table_wm.c',\n+\t\t)\n headers = files('rte_table.h',\n \t\t'rte_table_acl.h',\n \t\t'rte_table_lpm.h',\n@@ -24,7 +26,9 @@ headers = files('rte_table.h',\n \t\t'rte_table_array.h',\n \t\t'rte_table_stub.h',\n \t\t'rte_swx_table.h',\n-\t\t'rte_swx_table_em.h',)\n+\t\t'rte_swx_table_em.h',\n+\t\t'rte_swx_table_wm.h',\n+\t\t)\n deps += ['mbuf', 'port', 'lpm', 'hash', 'acl']\n \n indirect_headers += files('rte_lru_x86.h',\ndiff --git a/lib/librte_table/rte_swx_table_wm.c b/lib/librte_table/rte_swx_table_wm.c\nnew file mode 100644\nindex 000000000..9924231b3\n--- /dev/null\n+++ b/lib/librte_table/rte_swx_table_wm.c\n@@ -0,0 +1,470 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+#include <stdlib.h>\n+#include <string.h>\n+#include <stdio.h>\n+#include <errno.h>\n+\n+#include <rte_common.h>\n+#include <rte_prefetch.h>\n+#include <rte_cycles.h>\n+#include <rte_acl.h>\n+\n+#include \"rte_swx_table_wm.h\"\n+\n+#ifndef RTE_SWX_TABLE_EM_USE_HUGE_PAGES\n+#define RTE_SWX_TABLE_EM_USE_HUGE_PAGES 1\n+#endif\n+\n+#if RTE_SWX_TABLE_EM_USE_HUGE_PAGES\n+\n+#include <rte_malloc.h>\n+\n+static void *\n+env_malloc(size_t size, size_t alignment, int numa_node)\n+{\n+\treturn rte_zmalloc_socket(NULL, size, alignment, numa_node);\n+}\n+\n+static void\n+env_free(void *start, size_t size __rte_unused)\n+{\n+\trte_free(start);\n+}\n+\n+#else\n+\n+#include <numa.h>\n+\n+static void *\n+env_malloc(size_t size, size_t alignment __rte_unused, int numa_node)\n+{\n+\treturn numa_alloc_onnode(size, numa_node);\n+}\n+\n+static void\n+env_free(void *start, size_t size)\n+{\n+\tnuma_free(start, size);\n+}\n+\n+#endif\n+\n+static char *get_unique_name(void)\n+{\n+\tchar *name;\n+\tuint64_t *tsc;\n+\n+\tname = calloc(7, 1);\n+\tif (!name)\n+\t\treturn NULL;\n+\n+\ttsc = (uint64_t *) name;\n+\t*tsc = rte_get_tsc_cycles();\n+\treturn name;\n+}\n+\n+static uint32_t\n+count_entries(struct rte_swx_table_entry_list *entries)\n+{\n+\tstruct rte_swx_table_entry *entry;\n+\tuint32_t n_entries = 0;\n+\n+\tif (!entries)\n+\t\treturn 0;\n+\n+\tTAILQ_FOREACH(entry, entries, node)\n+\t\tn_entries++;\n+\n+\treturn n_entries;\n+}\n+\n+static int\n+acl_table_cfg_get(struct rte_acl_config *cfg, struct rte_swx_table_params *p)\n+{\n+\tuint32_t byte_id = 0, field_id = 0;\n+\n+\t/* cfg->num_categories. */\n+\tcfg->num_categories = 1;\n+\n+\t/* cfg->defs and cfg->num_fields. */\n+\tfor (byte_id = 0; byte_id < p->key_size; ) {\n+\t\tuint32_t field_size = field_id ? 4 : 1;\n+\t\tuint8_t byte = p->key_mask0 ? p->key_mask0[byte_id] : 0xFF;\n+\n+\t\tif (!byte) {\n+\t\t\tbyte_id++;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (field_id == RTE_ACL_MAX_FIELDS)\n+\t\t\treturn -1;\n+\n+\t\tcfg->defs[field_id].type = RTE_ACL_FIELD_TYPE_BITMASK;\n+\t\tcfg->defs[field_id].size = field_size;\n+\t\tcfg->defs[field_id].field_index = field_id;\n+\t\tcfg->defs[field_id].input_index = field_id;\n+\t\tcfg->defs[field_id].offset = p->key_offset + byte_id;\n+\n+\t\tfield_id++;\n+\t\tbyte_id += field_size;\n+\t}\n+\n+\tif (!field_id)\n+\t\treturn -1;\n+\n+\tcfg->num_fields = field_id;\n+\n+\t/* cfg->max_size. */\n+\tcfg->max_size = 0;\n+\n+\treturn 0;\n+}\n+\n+static void\n+acl_table_rule_field8(uint8_t *value,\n+\tuint8_t *mask,\n+\tuint8_t *key_mask0,\n+\tuint8_t *key_mask,\n+\tuint8_t *key,\n+\tuint32_t offset)\n+{\n+\tuint8_t km0, km;\n+\n+\tkm0 = key_mask0 ? key_mask0[offset] : 0xFF;\n+\tkm = key_mask ? key_mask[offset] : 0xFF;\n+\n+\t*value = key[offset];\n+\t*mask = km0 & km;\n+}\n+\n+static void\n+acl_table_rule_field32(uint32_t *value,\n+\tuint32_t *mask,\n+\tuint8_t *key_mask0,\n+\tuint8_t *key_mask,\n+\tuint8_t *key,\n+\tuint32_t key_size,\n+\tuint32_t offset)\n+{\n+\tuint32_t km0[4], km[4], k[4];\n+\tuint32_t byte_id;\n+\n+\t/* Byte 0 = MSB, byte 3 = LSB. */\n+\tfor (byte_id = 0; byte_id < 4; byte_id++) {\n+\t\tif (offset + byte_id >= key_size) {\n+\t\t\tkm0[byte_id] = 0;\n+\t\t\tkm[byte_id] = 0;\n+\t\t\tk[byte_id] = 0;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tkm0[byte_id] = key_mask0 ? key_mask0[offset + byte_id] : 0xFF;\n+\t\tkm[byte_id] = key_mask ? key_mask[offset + byte_id] : 0xFF;\n+\t\tk[byte_id] = key[offset + byte_id];\n+\t}\n+\n+\t*value = (k[0] << 24) |\n+\t\t (k[1] << 16) |\n+\t\t (k[2] << 8) |\n+\t\t k[3];\n+\n+\t*mask = ((km[0] & km0[0]) << 24) |\n+\t\t((km[1] & km0[1]) << 16) |\n+\t\t((km[2] & km0[2]) << 8) |\n+\t\t(km[3] & km0[3]);\n+}\n+\n+RTE_ACL_RULE_DEF(acl_rule, RTE_ACL_MAX_FIELDS);\n+\n+static struct rte_acl_rule *\n+acl_table_rules_get(struct rte_acl_config *acl_cfg,\n+\tstruct rte_swx_table_params *p,\n+\tstruct rte_swx_table_entry_list *entries,\n+\tuint32_t n_entries)\n+{\n+\tstruct rte_swx_table_entry *entry;\n+\tuint8_t *memory;\n+\tuint32_t acl_rule_size = RTE_ACL_RULE_SZ(acl_cfg->num_fields);\n+\tuint32_t n_fields = acl_cfg->num_fields;\n+\tuint32_t rule_id;\n+\n+\tif (!n_entries)\n+\t\treturn NULL;\n+\n+\tmemory = malloc(n_entries * acl_rule_size);\n+\tif (!memory)\n+\t\treturn NULL;\n+\n+\trule_id = 0;\n+\tTAILQ_FOREACH(entry, entries, node) {\n+\t\tuint8_t *m = &memory[rule_id * acl_rule_size];\n+\t\tstruct acl_rule *acl_rule = (struct acl_rule *)m;\n+\t\tuint32_t field_id;\n+\n+\t\tacl_rule->data.category_mask = 1;\n+\t\tacl_rule->data.priority = RTE_ACL_MAX_PRIORITY -\n+\t\t\tentry->key_priority;\n+\t\tacl_rule->data.userdata = rule_id + 1;\n+\n+\t\tfor (field_id = 0; field_id < n_fields; field_id++) {\n+\t\t\tstruct rte_acl_field *f = &acl_rule->field[field_id];\n+\t\t\tuint32_t size = acl_cfg->defs[field_id].size;\n+\t\t\tuint32_t offset = acl_cfg->defs[field_id].offset -\n+\t\t\t\tp->key_offset;\n+\n+\t\t\tif (size == 1) {\n+\t\t\t\tuint8_t value, mask;\n+\n+\t\t\t\tacl_table_rule_field8(&value,\n+\t\t\t\t\t\t &mask,\n+\t\t\t\t\t\t p->key_mask0,\n+\t\t\t\t\t\t entry->key_mask,\n+\t\t\t\t\t\t entry->key,\n+\t\t\t\t\t\t offset);\n+\n+\t\t\t\tf->value.u8 = value;\n+\t\t\t\tf->mask_range.u8 = mask;\n+\t\t\t} else {\n+\t\t\t\tuint32_t value, mask;\n+\n+\t\t\t\tacl_table_rule_field32(&value,\n+\t\t\t\t\t\t &mask,\n+\t\t\t\t\t\t p->key_mask0,\n+\t\t\t\t\t\t entry->key_mask,\n+\t\t\t\t\t\t entry->key,\n+\t\t\t\t\t\t p->key_size,\n+\t\t\t\t\t\t offset);\n+\n+\t\t\t\tf->value.u32 = value;\n+\t\t\t\tf->mask_range.u32 = mask;\n+\t\t\t}\n+\t\t}\n+\n+\t\trule_id++;\n+\t}\n+\n+\treturn (struct rte_acl_rule *)memory;\n+}\n+\n+/* When the table to be created has no rules, the expected behavior is to always\n+ * get lookup miss for any input key. To achieve this, we add a single bogus\n+ * rule to the table with the rule user data set to 0, i.e. the value returned\n+ * when lookup miss takes place. Whether lookup hit (the bogus rule is hit) or\n+ * miss, a user data of 0 is returned, which for the ACL library is equivalent\n+ * to lookup miss.\n+ */\n+static struct rte_acl_rule *\n+acl_table_rules_default_get(struct rte_acl_config *acl_cfg)\n+{\n+\tstruct rte_acl_rule *acl_rule;\n+\tuint32_t acl_rule_size = RTE_ACL_RULE_SZ(acl_cfg->num_fields);\n+\n+\tacl_rule = calloc(1, acl_rule_size);\n+\tif (!acl_rule)\n+\t\treturn NULL;\n+\n+\tacl_rule->data.category_mask = 1;\n+\tacl_rule->data.priority = RTE_ACL_MAX_PRIORITY;\n+\tacl_rule->data.userdata = 0;\n+\n+\tmemset(&acl_rule[1], 0xFF, acl_rule_size - sizeof(struct rte_acl_rule));\n+\n+\treturn acl_rule;\n+}\n+\n+static struct rte_acl_ctx *\n+acl_table_create(struct rte_swx_table_params *params,\n+\tstruct rte_swx_table_entry_list *entries,\n+\tuint32_t n_entries,\n+\tint numa_node)\n+{\n+\tstruct rte_acl_param acl_params = {0};\n+\tstruct rte_acl_config acl_cfg = {0};\n+\tstruct rte_acl_ctx *acl_ctx = NULL;\n+\tstruct rte_acl_rule *acl_rules = NULL;\n+\tchar *name = NULL;\n+\tint status = 0;\n+\n+\t/* ACL config data structures. */\n+\tname = get_unique_name();\n+\tif (!name) {\n+\t\tstatus = -1;\n+\t\tgoto free_resources;\n+\t}\n+\n+\tstatus = acl_table_cfg_get(&acl_cfg, params);\n+\tif (status)\n+\t\tgoto free_resources;\n+\n+\tacl_rules = n_entries ?\n+\t\tacl_table_rules_get(&acl_cfg, params, entries, n_entries) :\n+\t\tacl_table_rules_default_get(&acl_cfg);\n+\tif (!acl_rules) {\n+\t\tstatus = -1;\n+\t\tgoto free_resources;\n+\t}\n+\n+\tn_entries = n_entries ? n_entries : 1;\n+\n+\t/* ACL create. */\n+\tacl_params.name = name;\n+\tacl_params.socket_id = numa_node;\n+\tacl_params.rule_size = RTE_ACL_RULE_SZ(acl_cfg.num_fields);\n+\tacl_params.max_rule_num = n_entries;\n+\n+\tacl_ctx = rte_acl_create(&acl_params);\n+\tif (!acl_ctx) {\n+\t\tstatus = -1;\n+\t\tgoto free_resources;\n+\t}\n+\n+\t/* ACL add rules. */\n+\tstatus = rte_acl_add_rules(acl_ctx, acl_rules, n_entries);\n+\tif (status)\n+\t\tgoto free_resources;\n+\n+\t/* ACL build. */\n+\tstatus = rte_acl_build(acl_ctx, &acl_cfg);\n+\n+free_resources:\n+\tif (status && acl_ctx)\n+\t\trte_acl_free(acl_ctx);\n+\n+\tfree(acl_rules);\n+\n+\tfree(name);\n+\n+\treturn status ? NULL : acl_ctx;\n+}\n+\n+static void\n+entry_data_copy(uint8_t *data,\n+\tstruct rte_swx_table_entry_list *entries,\n+\tuint32_t n_entries,\n+\tuint32_t entry_data_size)\n+{\n+\tstruct rte_swx_table_entry *entry;\n+\tuint32_t i = 0;\n+\n+\tif (!n_entries)\n+\t\treturn;\n+\n+\tTAILQ_FOREACH(entry, entries, node) {\n+\t\tuint64_t *d = (uint64_t *)&data[i * entry_data_size];\n+\n+\t\td[0] = entry->action_id;\n+\t\tmemcpy(&d[1], entry->action_data, entry_data_size - 8);\n+\n+\t\ti++;\n+\t}\n+}\n+\n+struct table {\n+\tstruct rte_acl_ctx *acl_ctx;\n+\tuint8_t *data;\n+\tsize_t total_size;\n+\tuint32_t entry_data_size;\n+};\n+\n+static void\n+table_free(void *table)\n+{\n+\tstruct table *t = table;\n+\n+\tif (!t)\n+\t\treturn;\n+\n+\tif (t->acl_ctx)\n+\t\trte_acl_free(t->acl_ctx);\n+\tenv_free(t, t->total_size);\n+}\n+\n+static void *\n+table_create(struct rte_swx_table_params *params,\n+\t struct rte_swx_table_entry_list *entries,\n+\t const char *args __rte_unused,\n+\t int numa_node)\n+{\n+\tstruct table *t = NULL;\n+\tsize_t meta_sz, data_sz, total_size;\n+\tuint32_t entry_data_size;\n+\tuint32_t n_entries = count_entries(entries);\n+\n+\t/* Check input arguments. */\n+\tif (!params || !params->key_size)\n+\t\tgoto error;\n+\n+\t/* Memory allocation and initialization. */\n+\tentry_data_size = 8 + params->action_data_size;\n+\tmeta_sz = sizeof(struct table);\n+\tdata_sz = n_entries * entry_data_size;\n+\ttotal_size = meta_sz + data_sz;\n+\n+\tt = env_malloc(total_size, RTE_CACHE_LINE_SIZE, numa_node);\n+\tif (!t)\n+\t\tgoto error;\n+\n+\tmemset(t, 0, total_size);\n+\tt->entry_data_size = entry_data_size;\n+\tt->total_size = total_size;\n+\tt->data = (uint8_t *)&t[1];\n+\n+\tt->acl_ctx = acl_table_create(params, entries, n_entries, numa_node);\n+\tif (!t->acl_ctx)\n+\t\tgoto error;\n+\n+\tentry_data_copy(t->data, entries, n_entries, entry_data_size);\n+\n+\treturn t;\n+\n+error:\n+\ttable_free(t);\n+\treturn NULL;\n+}\n+\n+struct mailbox {\n+\n+};\n+\n+static uint64_t\n+table_mailbox_size_get(void)\n+{\n+\treturn sizeof(struct mailbox);\n+}\n+\n+static int\n+table_lookup(void *table,\n+\t void *mailbox __rte_unused,\n+\t const uint8_t **key,\n+\t uint64_t *action_id,\n+\t uint8_t **action_data,\n+\t int *hit)\n+{\n+\tstruct table *t = table;\n+\tuint8_t *data;\n+\tuint32_t user_data;\n+\n+\trte_acl_classify(t->acl_ctx, key, &user_data, 1, 1);\n+\tif (!user_data) {\n+\t\t*hit = 0;\n+\t\treturn 1;\n+\t}\n+\n+\tdata = &t->data[(user_data - 1) * t->entry_data_size];\n+\t*action_id = ((uint64_t *)data)[0];\n+\t*action_data = &data[8];\n+\t*hit = 1;\n+\treturn 1;\n+}\n+\n+struct rte_swx_table_ops rte_swx_table_wildcard_match_ops = {\n+\t.footprint_get = NULL,\n+\t.mailbox_size_get = table_mailbox_size_get,\n+\t.create = table_create,\n+\t.add = NULL,\n+\t.del = NULL,\n+\t.lkp = (rte_swx_table_lookup_t)table_lookup,\n+\t.free = table_free,\n+};\ndiff --git a/lib/librte_table/rte_swx_table_wm.h b/lib/librte_table/rte_swx_table_wm.h\nnew file mode 100644\nindex 000000000..a716536ca\n--- /dev/null\n+++ b/lib/librte_table/rte_swx_table_wm.h\n@@ -0,0 +1,27 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+#ifndef __INCLUDE_RTE_SWX_TABLE_WM_H__\n+#define __INCLUDE_RTE_SWX_TABLE_WM_H__\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * @file\n+ * RTE SWX Wildcard Match Table\n+ */\n+\n+#include <stdint.h>\n+\n+#include <rte_swx_table.h>\n+\n+/** Wildcard match table operations. */\n+extern struct rte_swx_table_ops rte_swx_table_wildcard_match_ops;\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\ndiff --git a/lib/librte_table/version.map b/lib/librte_table/version.map\nindex bea2252a4..eb0291ac4 100644\n--- a/lib/librte_table/version.map\n+++ b/lib/librte_table/version.map\n@@ -25,4 +25,7 @@ EXPERIMENTAL {\n \t# added in 20.11\n \trte_swx_table_exact_match_ops;\n \trte_swx_table_exact_match_unoptimized_ops;\n+\n+\t# added in 21.05\n+\trte_swx_table_wildcard_match_ops;\n };\n", "prefixes": [ "v3", "5/5" ] }